cvs.zerfleddert.de Git - proxmark3-svn/blob - armsrc/util.c

   1 //-----------------------------------------------------------------------------
   2 // Jonathan Westhues, Sept 2005
   3 //
   4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
   5 // at your option, any later version. See the LICENSE.txt file for the text of
   6 // the license.
   7 //-----------------------------------------------------------------------------
   8 // Utility functions used in many places, not specific to any piece of code.
   9 //-----------------------------------------------------------------------------
  10
  11 #include "proxmark3.h"
  12 #include "util.h"
  13 #include "string.h"
  14 #include "apps.h"
  15 #include "BigBuf.h"
  16
  17
  18
  19 void print_result(char *name, uint8_t *buf, size_t len) {
  20    uint8_t *p = buf;
  21
  22    if ( len % 16 == 0 ) {
  23            for(; p-buf < len; p += 16)
  24            Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
  25                                 name,
  26                                 p-buf,
  27                                 len,
  28                                 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]
  29            );
  30    }
  31    else {
  32    for(; p-buf < len; p += 8)
  33            Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name, p-buf, len, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
  34    }
  35 }
  36
  37 size_t nbytes(size_t nbits) {
  38         return (nbits >> 3)+((nbits % 8) > 0);
  39 }
  40
  41 uint32_t SwapBits(uint32_t value, int nrbits) {
  42         int i;
  43         uint32_t newvalue = 0;
  44         for(i = 0; i < nrbits; i++) {
  45                 newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
  46         }
  47         return newvalue;
  48 }
  49
  50 void num_to_bytes(uint64_t n, size_t len, uint8_t* dest)
  51 {
  52         while (len--) {
  53                 dest[len] = (uint8_t) n;
  54                 n >>= 8;
  55         }
  56 }
  57
  58 uint64_t bytes_to_num(uint8_t* src, size_t len)
  59 {
  60         uint64_t num = 0;
  61         while (len--)
  62         {
  63                 num = (num << 8) | (*src);
  64                 src++;
  65         }
  66         return num;
  67 }
  68
  69 // RotateLeft - Ultralight, Desfire
  70 void rol(uint8_t *data, const size_t len){
  71         uint8_t first = data[0];
  72         for (size_t i = 0; i < len-1; i++) {
  73                 data[i] = data[i+1];
  74         }
  75         data[len-1] = first;
  76 }
  77 void lsl (uint8_t *data, size_t len) {
  78         for (size_t n = 0; n < len - 1; n++) {
  79                 data[n] = (data[n] << 1) | (data[n+1] >> 7);
  80         }
  81         data[len - 1] <<= 1;
  82 }
  83
  84 void LEDsoff()
  85 {
  86         LED_A_OFF();
  87         LED_B_OFF();
  88         LED_C_OFF();
  89         LED_D_OFF();
  90 }
  91
  92 void LEDson()
  93 {
  94         LED_A_ON();
  95         LED_B_ON();
  96         LED_C_ON();
  97         LED_D_ON();
  98 }
  99
 100 void LEDsinvert()
 101 {
 102         LED_A_INV();
 103         LED_B_INV();
 104         LED_C_INV();
 105         LED_D_INV();
 106 }
 107
 108 // LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
 109 void LED(int led, int ms)
 110 {
 111         if (led & LED_RED)
 112                 LED_C_ON();
 113         if (led & LED_ORANGE)
 114                 LED_A_ON();
 115         if (led & LED_GREEN)
 116                 LED_B_ON();
 117         if (led & LED_RED2)
 118                 LED_D_ON();
 119
 120         if (!ms)
 121                 return;
 122
 123         SpinDelay(ms);
 124
 125         if (led & LED_RED)
 126                 LED_C_OFF();
 127         if (led & LED_ORANGE)
 128                 LED_A_OFF();
 129         if (led & LED_GREEN)
 130                 LED_B_OFF();
 131         if (led & LED_RED2)
 132                 LED_D_OFF();
 133 }
 134
 135
 136 // Determine if a button is double clicked, single clicked,
 137 // not clicked, or held down (for ms || 1sec)
 138 // In general, don't use this function unless you expect a
 139 // double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
 140 int BUTTON_CLICKED(int ms) {
 141         // Up to 500ms in between clicks to mean a double click
 142         int ticks = (48000 * (ms ? ms : 1000)) >> 10;
 143
 144         // If we're not even pressed, forget about it!
 145         if (!BUTTON_PRESS())
 146                 return BUTTON_NO_CLICK;
 147
 148         // Borrow a PWM unit for my real-time clock
 149         AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
 150         // 48 MHz / 1024 gives 46.875 kHz
 151         AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
 152         AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
 153         AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
 154
 155         uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
 156
 157         int letoff = 0;
 158         for(;;)
 159         {
 160                 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
 161
 162                 // We haven't let off the button yet
 163                 if (!letoff)
 164                 {
 165                         // We just let it off!
 166                         if (!BUTTON_PRESS())
 167                         {
 168                                 letoff = 1;
 169
 170                                 // reset our timer for 500ms
 171                                 start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
 172                                 ticks = (48000 * (500)) >> 10;
 173                         }
 174
 175                         // Still haven't let it off
 176                         else
 177                                 // Have we held down a full second?
 178                                 if (now == (uint16_t)(start + ticks))
 179                                         return BUTTON_HOLD;
 180                 }
 181
 182                 // We already let off, did we click again?
 183                 else
 184                         // Sweet, double click!
 185                         if (BUTTON_PRESS())
 186                                 return BUTTON_DOUBLE_CLICK;
 187
 188                         // Have we ran out of time to double click?
 189                         else
 190                                 if (now == (uint16_t)(start + ticks))
 191                                         // At least we did a single click
 192                                         return BUTTON_SINGLE_CLICK;
 193
 194                 WDT_HIT();
 195         }
 196
 197         // We should never get here
 198         return BUTTON_ERROR;
 199 }
 200
 201 // Determine if a button is held down
 202 int BUTTON_HELD(int ms) {
 203         // If button is held for one second
 204         int ticks = (48000 * (ms ? ms : 1000)) >> 10;
 205
 206         // If we're not even pressed, forget about it!
 207         if (!BUTTON_PRESS())
 208                 return BUTTON_NO_CLICK;
 209
 210         // Borrow a PWM unit for my real-time clock
 211         AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
 212         // 48 MHz / 1024 gives 46.875 kHz
 213         AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
 214         AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
 215         AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
 216
 217         uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
 218
 219         for(;;) {
 220                 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
 221
 222                 // As soon as our button let go, we didn't hold long enough
 223                 if (!BUTTON_PRESS())
 224                         return BUTTON_SINGLE_CLICK;
 225
 226                 // Have we waited the full second?
 227                 else if (now == (uint16_t)(start + ticks))
 228                                 return BUTTON_HOLD;
 229
 230                 WDT_HIT();
 231         }
 232
 233         // We should never get here
 234         return BUTTON_ERROR;
 235 }
 236
 237 // attempt at high resolution microsecond timer
 238 // beware: timer counts in 21.3uS increments (1024/48Mhz)
 239 void SpinDelayUs(int us) {
 240         int ticks = (48*us) >> 10;
 241
 242         // Borrow a PWM unit for my real-time clock
 243         AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
 244         // 48 MHz / 1024 gives 46.875 kHz
 245         AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
 246         AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
 247         AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
 248
 249         uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
 250
 251         for(;;) {
 252                 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
 253                 if (now == (uint16_t)(start + ticks))
 254                         return;
 255
 256                 WDT_HIT();
 257         }
 258 }
 259
 260 void SpinDelay(int ms) {
 261   // convert to uS and call microsecond delay function
 262         SpinDelayUs(ms*1000);
 263 }
 264
 265 /* Similar to FpgaGatherVersion this formats stored version information
 266  * into a string representation. It takes a pointer to the struct version_information,
 267  * verifies the magic properties, then stores a formatted string, prefixed by
 268  * prefix in dst.
 269  */
 270 void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information)
 271 {
 272         struct version_information *v = (struct version_information*)version_information;
 273         dst[0] = 0;
 274         strncat(dst, prefix, len-1);
 275         if(v->magic != VERSION_INFORMATION_MAGIC) {
 276                 strncat(dst, "Missing/Invalid version information\n", len - strlen(dst) - 1);
 277                 return;
 278         }
 279         if(v->versionversion != 1) {
 280                 strncat(dst, "Version information not understood\n", len - strlen(dst) - 1);
 281                 return;
 282         }
 283         if(!v->present) {
 284                 strncat(dst, "Version information not available\n", len - strlen(dst) - 1);
 285                 return;
 286         }
 287
 288         strncat(dst, v->gitversion, len - strlen(dst) - 1);
 289         if(v->clean == 0) {
 290                 strncat(dst, "-unclean", len - strlen(dst) - 1);
 291         } else if(v->clean == 2) {
 292                 strncat(dst, "-suspect", len - strlen(dst) - 1);
 293         }
 294
 295         strncat(dst, " ", len - strlen(dst) - 1);
 296         strncat(dst, v->buildtime, len - strlen(dst) - 1);
 297         strncat(dst, "\n", len - strlen(dst) - 1);
 298 }
 299
 300
 301 //  -------------------------------------------------------------------------
 302 //  timer lib
 303 //  -------------------------------------------------------------------------
 304 //  test procedure:
 305 //
 306 //  ti = GetTickCount();
 307 //  SpinDelay(1000);
 308 //  ti = GetTickCount() - ti;
 309 //  Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
 310
 311 void StartTickCount() {
 312         // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
 313         // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
 314         uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff;     // = 16 * main clock frequency (16MHz) / slow clock frequency
 315         // set RealTimeCounter divider to count at 1kHz:
 316         AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf);
 317         // note: worst case precision is approx 2.5%
 318 }
 319
 320
 321 /*
 322 * Get the current count.
 323 */
 324 uint32_t RAMFUNC GetTickCount(void) {
 325         return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
 326 }
 327
 328
 329 //  -------------------------------------------------------------------------
 330 //  microseconds timer
 331 //  -------------------------------------------------------------------------
 332 void StartCountUS(void) {
 333         AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
 334 //  AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
 335         AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
 336
 337         // fast clock
 338         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
 339         AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
 340                                                                                                                 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
 341                                                                                                                 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
 342         AT91C_BASE_TC0->TC_RA = 1;
 343         AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
 344
 345         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable
 346         AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
 347
 348         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
 349         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
 350         AT91C_BASE_TCB->TCB_BCR = 1;
 351         }
 352
 353
 354 uint32_t RAMFUNC GetCountUS(void) {
 355         return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); //was  /15) * 10);
 356 }
 357
 358
 359 static uint32_t GlobalUsCounter = 0;
 360
 361 uint32_t RAMFUNC GetDeltaCountUS(void) {
 362         uint32_t g_cnt = GetCountUS();
 363         uint32_t g_res = g_cnt - GlobalUsCounter;
 364         GlobalUsCounter = g_cnt;
 365         return g_res;
 366 }
 367
 368
 369 //  -------------------------------------------------------------------------
 370 //  Timer for iso14443 commands. Uses ssp_clk from FPGA
 371 //  -------------------------------------------------------------------------
 372 void StartCountSspClk(void) {
 373         AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers
 374         AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1       // XC0 Clock = TIOA1
 375                                                         | AT91C_TCB_TC1XC1S_NONE        // XC1 Clock = none
 376                                                         | AT91C_TCB_TC2XC2S_TIOA0;      // XC2 Clock = TIOA0
 377
 378         // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
 379         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;               // disable TC1
 380         AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
 381                                                         | AT91C_TC_CPCSTOP              // Stop clock on RC compare
 382                                                         | AT91C_TC_EEVTEDG_RISING       // Trigger on rising edge of Event
 383                                                         | AT91C_TC_EEVT_TIOB            // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16 ... 13,56MHz/4)
 384                                                         | AT91C_TC_ENETRG               // Enable external trigger event
 385                                                         | AT91C_TC_WAVESEL_UP           // Upmode without automatic trigger on RC compare
 386                                                         | AT91C_TC_WAVE                 // Waveform Mode
 387                                                         | AT91C_TC_AEEVT_SET            // Set TIOA1 on external event
 388                                                         | AT91C_TC_ACPC_CLEAR;          // Clear TIOA1 on RC Compare
 389         AT91C_BASE_TC1->TC_RC = 1;                              // RC Compare value = 1; pulse width to TC0
 390
 391         // use TC0 to count TIOA1 pulses
 392         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;               // disable TC0
 393         AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0              // TC0 clock = XC0 clock = TIOA1
 394                                                         | AT91C_TC_WAVE                 // Waveform Mode
 395                                                         | AT91C_TC_WAVESEL_UP           // just count
 396                                                         | AT91C_TC_ACPA_CLEAR           // Clear TIOA0 on RA Compare
 397                                                         | AT91C_TC_ACPC_SET;            // Set TIOA0 on RC Compare
 398         AT91C_BASE_TC0->TC_RA = 1;                              // RA Compare value = 1; pulse width to TC2
 399         AT91C_BASE_TC0->TC_RC = 0;                              // RC Compare value = 0; increment TC2 on overflow
 400
 401         // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
 402         AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS;               // disable TC2
 403         AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2              // TC2 clock = XC2 clock = TIOA0
 404                                                         | AT91C_TC_WAVE                 // Waveform Mode
 405                                                         | AT91C_TC_WAVESEL_UP;          // just count
 406
 407         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;                // enable TC0
 408         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;                // enable TC1
 409         AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;                // enable TC2
 410
 411         //
 412         // synchronize the counter with the ssp_frame signal. Note: FPGA must be in a FPGA mode with SSC transfer, otherwise SSC_FRAME and SSC_CLK signals would not be present
 413         //
 414         while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);      // wait for ssp_frame to be low
 415         while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
 416         while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK));     // wait for ssp_clk to go high; 1st ssp_clk after start of frame
 417         while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);        // wait for ssp_clk to go low;
 418         while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK));     // wait for ssp_clk to go high; 2nd ssp_clk after start of frame
 419         if ((AT91C_BASE_SSC->SSC_RFMR & SSC_FRAME_MODE_BITS_IN_WORD(32)) == SSC_FRAME_MODE_BITS_IN_WORD(16)) { // 16bit frame
 420                 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);    // wait for ssp_clk to go low;
 421                 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high; 3rd ssp_clk after start of frame
 422                 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);    // wait for ssp_clk to go low;
 423                 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high; 4th ssp_clk after start of frame
 424                 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);    // wait for ssp_clk to go low;
 425                 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high; 5th ssp_clk after start of frame
 426                 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);    // wait for ssp_clk to go low;
 427                 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high; 6th ssp_clk after start of frame
 428         }
 429         // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
 430         AT91C_BASE_TCB->TCB_BCR = 1;                            // assert Sync (set all timers to 0 on next active clock edge)
 431         // at the next (3rd/7th) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
 432         // at the next (4th/8th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
 433         // whenever the last three/four bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
 434
 435         // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
 436         // we can use the counter.
 437         while (AT91C_BASE_TC0->TC_CV < 0xFFFF);
 438         // Note: needs one more SSP_CLK cycle (1.18 us) until TC2 resets. Don't call GetCountSspClk() that soon.
 439 }
 440
 441
 442 void ResetSspClk(void) {
 443         //enable clock of timer and software trigger
 444         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 445         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 446         AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 447         while (AT91C_BASE_TC2->TC_CV > 0);
 448 }
 449
 450 uint32_t GetCountSspClk(){
 451         uint32_t hi, lo;
 452
 453         do {
 454                 hi = AT91C_BASE_TC2->TC_CV;
 455                 lo = AT91C_BASE_TC0->TC_CV;
 456         } while (hi != AT91C_BASE_TC2->TC_CV);
 457
 458         return (hi << 16) | lo;
 459 }
 460
 461 //  -------------------------------------------------------------------------
 462 //  Timer for bitbanging, or LF stuff when you need a very precis timer
 463 //  1us = 1.5ticks
 464 //  -------------------------------------------------------------------------
 465 void StartTicks(void){
 466         // initialization of the timer
 467         AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1);
 468         AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
 469
 470         // disable TC0 and TC1 for re-configuration
 471         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
 472         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
 473
 474         // first configure TC1 (higher, 0xFFFF0000) 16 bit counter
 475         AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // just connect to TIOA0 from TC0
 476         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // re-enable timer and wait for TC0
 477
 478         // second configure TC0 (lower, 0x0000FFFF) 16 bit counter
 479         AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32
 480                                                          AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO |
 481                                                          AT91C_TC_ACPA_CLEAR | // RA comperator clears TIOA (carry bit)
 482                                                          AT91C_TC_ACPC_SET |   // RC comperator sets TIOA (carry bit)
 483                                                          AT91C_TC_ASWTRG_SET;  // SWTriger sets TIOA (carry bit)
 484         AT91C_BASE_TC0->TC_RC  = 0; // set TIOA (carry bit) on overflow, return to zero
 485         AT91C_BASE_TC0->TC_RA  = 1; // clear carry bit on next clock cycle
 486         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // reset and re-enable timer
 487
 488         // synchronized startup procedure
 489         while (AT91C_BASE_TC0->TC_CV > 0); // wait until TC0 returned to zero
 490         while (AT91C_BASE_TC0->TC_CV < 2); // and has started (TC_CV > TC_RA, now TC1 is cleared)
 491
 492         // return to zero
 493         AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
 494         AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
 495         while (AT91C_BASE_TC0->TC_CV > 0);
 496 }
 497
 498
 499 uint32_t GetTicks(void) {
 500         uint32_t hi, lo;
 501
 502         do {
 503                 hi = AT91C_BASE_TC1->TC_CV;
 504                 lo = AT91C_BASE_TC0->TC_CV;
 505         } while(hi != AT91C_BASE_TC1->TC_CV);
 506
 507         return (hi << 16) | lo;
 508 }
 509
 510
 511 // Wait - Spindelay in ticks.
 512 // if called with a high number, this will trigger the WDT...
 513 void WaitTicks(uint32_t ticks){
 514         if ( ticks == 0 ) return;
 515         ticks += GetTicks();
 516         while (GetTicks() < ticks);
 517 }
 518
 519
 520 // Wait / Spindelay in us (microseconds)
 521 // 1us = 1.5ticks.
 522 void WaitUS(uint16_t us){
 523         WaitTicks( (uint32_t)us * 3 / 2 ) ;
 524 }
 525
 526
 527 void WaitMS(uint16_t ms){
 528         WaitTicks( (uint32_t)ms * 1500 );
 529 }
 530
 531
 532 // Starts Clock and waits until its reset
 533 void ResetTicks(void){
 534         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 535         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 536         while (AT91C_BASE_TC0->TC_CV > 0);
 537 }
 538
 539
 540 void ResetTimer(AT91PS_TC timer){
 541         timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 542         while(timer->TC_CV > 0) ;
 543 }
 544
 545
 546 // stop clock
 547 void StopTicks(void){
 548         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
 549         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
 550 }
 551
 552
 553 static uint64_t next_random = 1;
 554
 555 /* Generates a (non-cryptographically secure) 32-bit random number.
 556  *
 557  * We don't have an implementation of the "rand" function or a clock to seed it
 558  * with, so we just call GetTickCount the first time to seed ourselves.
 559  */
 560 uint32_t prand() {
 561         if (next_random == 1) {
 562                 next_random = GetTickCount();
 563         }
 564
 565         next_random = next_random * 6364136223846793005 + 1;
 566         return (uint32_t)(next_random >> 32) % 0xffffffff;
 567 }