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FIX: Much of my added extra legic code is commented away now.
[proxmark3-svn] / armsrc / legicrf.c
1 //-----------------------------------------------------------------------------
2 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // LEGIC RF simulation code
9 //-----------------------------------------------------------------------------
10 #include "legicrf.h"
11
12 static struct legic_frame {
13 int bits;
14 uint32_t data;
15 } current_frame;
16
17 static enum {
18 STATE_DISCON,
19 STATE_IV,
20 STATE_CON,
21 } legic_state;
22
23 static crc_t legic_crc;
24 static int legic_read_count;
25 static uint32_t legic_prng_bc;
26 static uint32_t legic_prng_iv;
27
28 static int legic_phase_drift;
29 static int legic_frame_drift;
30 static int legic_reqresp_drift;
31
32 AT91PS_TC timer;
33 AT91PS_TC prng_timer;
34
35 /*
36 static void setup_timer(void) {
37 // Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
38 // this it won't be terribly accurate but should be good enough.
39 //
40 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
41 timer = AT91C_BASE_TC1;
42 timer->TC_CCR = AT91C_TC_CLKDIS;
43 timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
44 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
45
46 //
47 // Set up Timer 2 to use for measuring time between frames in
48 // tag simulation mode. Runs 4x faster as Timer 1
49 //
50 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);
51 prng_timer = AT91C_BASE_TC2;
52 prng_timer->TC_CCR = AT91C_TC_CLKDIS;
53 prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
54 prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
55 }
56
57 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
58 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
59
60 // fast clock
61 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
62 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
63 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
64 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
65 AT91C_BASE_TC0->TC_RA = 1;
66 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
67
68 */
69
70 // At TIMER_CLOCK3 (MCK/32)
71 //#define RWD_TIME_1 150 /* RWD_TIME_PAUSE off, 80us on = 100us */
72 //#define RWD_TIME_0 90 /* RWD_TIME_PAUSE off, 40us on = 60us */
73 //#define RWD_TIME_PAUSE 30 /* 20us */
74
75 // testing calculating in (us) microseconds.
76 #define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks
77 #define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks
78 #define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */
79 #define TAG_BIT_PERIOD 150 // 100us == 100 * 1.5 == 150ticks
80 #define TAG_FRAME_WAIT 495 // 330us from READER frame end to TAG frame start. 330 * 1.5 == 495
81
82 #define RWD_TIME_FUZZ 20 // rather generous 13us, since the peak detector + hysteresis fuzz quite a bit
83
84 #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
85 #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
86
87 #define OFFSET_LOG 1024
88
89 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
90
91 #ifndef SHORT_COIL
92 # define SHORT_COIL LOW(GPIO_SSC_DOUT);
93 #endif
94 #ifndef OPEN_COIL
95 # define OPEN_COIL HIGH(GPIO_SSC_DOUT);
96 #endif
97
98 uint32_t sendFrameStop = 0;
99
100 // Pause pulse, off in 20us / 30ticks,
101 // ONE / ZERO bit pulse,
102 // one == 80us / 120ticks
103 // zero == 40us / 60ticks
104 #ifndef COIL_PULSE
105 # define COIL_PULSE(x) \
106 do { \
107 SHORT_COIL; \
108 WaitTicks( (RWD_TIME_PAUSE) ); \
109 OPEN_COIL; \
110 WaitTicks((x)); \
111 } while (0)
112 #endif
113
114 // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
115 // Historically it used to be FREE_BUFFER_SIZE, which was 2744.
116 #define LEGIC_CARD_MEMSIZE 1024
117 static uint8_t* cardmem;
118
119 static void frame_append_bit(struct legic_frame * const f, uint8_t bit) {
120 // Overflow, won't happen
121 if (f->bits >= 31) return;
122
123 f->data |= (bit << f->bits);
124 f->bits++;
125 }
126
127 static void frame_clean(struct legic_frame * const f) {
128 f->data = 0;
129 f->bits = 0;
130 }
131
132 // Prng works when waiting in 99.1us cycles.
133 // and while sending/receiving in bit frames (100, 60)
134 /*static void CalibratePrng( uint32_t time){
135 // Calculate Cycles based on timer 100us
136 uint32_t i = (time - sendFrameStop) / 100 ;
137
138 // substract cycles of finished frames
139 int k = i - legic_prng_count()+1;
140
141 // substract current frame length, rewind to beginning
142 if ( k > 0 )
143 legic_prng_forward(k);
144 }
145 */
146
147 /* Generate Keystream */
148 uint32_t get_key_stream(int skip, int count) {
149 uint32_t key = 0;
150 int i;
151
152 // Use int to enlarge timer tc to 32bit
153 legic_prng_bc += prng_timer->TC_CV;
154
155 // reset the prng timer.
156 ResetTimer(prng_timer);
157
158 /* If skip == -1, forward prng time based */
159 if(skip == -1) {
160 i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */
161 i -= legic_prng_count(); /* substract cycles of finished frames */
162 i -= count; /* substract current frame length, rewind to beginning */
163 legic_prng_forward(i);
164 } else {
165 legic_prng_forward(skip);
166 }
167
168 i = (count == 6) ? -1 : legic_read_count;
169
170 /* Write Time Data into LOG */
171 // uint8_t *BigBuf = BigBuf_get_addr();
172 // BigBuf[OFFSET_LOG+128+i] = legic_prng_count();
173 // BigBuf[OFFSET_LOG+256+i*4] = (legic_prng_bc >> 0) & 0xff;
174 // BigBuf[OFFSET_LOG+256+i*4+1] = (legic_prng_bc >> 8) & 0xff;
175 // BigBuf[OFFSET_LOG+256+i*4+2] = (legic_prng_bc >>16) & 0xff;
176 // BigBuf[OFFSET_LOG+256+i*4+3] = (legic_prng_bc >>24) & 0xff;
177 // BigBuf[OFFSET_LOG+384+i] = count;
178
179 /* Generate KeyStream */
180 for(i=0; i<count; i++) {
181 key |= legic_prng_get_bit() << i;
182 legic_prng_forward(1);
183 }
184 return key;
185 }
186
187 /* Send a frame in tag mode, the FPGA must have been set up by
188 * LegicRfSimulate
189 */
190 void frame_send_tag(uint16_t response, uint8_t bits, uint8_t crypt) {
191 /* Bitbang the response */
192 LOW(GPIO_SSC_DOUT);
193 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
194 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
195
196 /* Use time to crypt frame */
197 if(crypt) {
198 legic_prng_forward(2); /* TAG_FRAME_WAIT -> shift by 2 */
199 response ^= legic_prng_get_bits(bits);
200 }
201
202 /* Wait for the frame start */
203 WaitUS( TAG_FRAME_WAIT );
204
205 uint8_t bit = 0;
206 for(int i = 0; i < bits; i++) {
207
208 bit = response & 1;
209 response >>= 1;
210
211 if (bit)
212 HIGH(GPIO_SSC_DOUT);
213 else
214 LOW(GPIO_SSC_DOUT);
215
216 WaitUS(100);
217 }
218 LOW(GPIO_SSC_DOUT);
219 }
220
221 /* Send a frame in reader mode, the FPGA must have been set up by
222 * LegicRfReader
223 */
224 void frame_sendAsReader(uint32_t data, uint8_t bits){
225
226 uint32_t starttime = GET_TICKS, send = 0;
227 uint16_t mask = 1;
228 uint8_t prngstart = legic_prng_count() ;
229
230 // xor lsfr onto data.
231 send = data ^ legic_prng_get_bits(bits);
232
233 for (; mask < BITMASK(bits); mask <<= 1) {
234 if (send & mask) {
235 COIL_PULSE(RWD_TIME_1);
236 } else {
237 COIL_PULSE(RWD_TIME_0);
238 }
239 }
240
241 // Final pause to mark the end of the frame
242 COIL_PULSE(0);
243
244 sendFrameStop = GET_TICKS;
245 uint8_t cmdbytes[] = {
246 bits,
247 BYTEx(data, 0),
248 BYTEx(data, 1),
249 BYTEx(send, 0),
250 BYTEx(send, 1),
251 prngstart,
252 legic_prng_count()
253 };
254 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, sendFrameStop, NULL, TRUE);
255 }
256
257 /* Receive a frame from the card in reader emulation mode, the FPGA and
258 * timer must have been set up by LegicRfReader and frame_sendAsReader.
259 *
260 * The LEGIC RF protocol from card to reader does not include explicit
261 * frame start/stop information or length information. The reader must
262 * know beforehand how many bits it wants to receive. (Notably: a card
263 * sending a stream of 0-bits is indistinguishable from no card present.)
264 *
265 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
266 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
267 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
268 * for edges. Count the edges in each bit interval. If they are approximately
269 * 0 this was a 0-bit, if they are approximately equal to the number of edges
270 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
271 * timer that's still running from frame_sendAsReader in order to get a synchronization
272 * with the frame that we just sent.
273 *
274 * FIXME: Because we're relying on the hysteresis to just do the right thing
275 * the range is severely reduced (and you'll probably also need a good antenna).
276 * So this should be fixed some time in the future for a proper receiver.
277 */
278 static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) {
279
280 frame_clean(f);
281 if ( bits > 32 ) return;
282
283 uint8_t i = bits, edges = 0;
284 uint16_t lsfr = 0;
285 uint32_t the_bit = 1, next_bit_at = 0, data;
286
287 int old_level = 0, level = 0;
288
289 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
290 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
291
292 // calibrate the prng.
293 //
294 legic_prng_forward(2);
295
296 // precompute the cipher
297 uint8_t prngstart = legic_prng_count() ;
298
299 data = lsfr = legic_prng_get_bits(bits);
300
301 //FIXED time between sending frame and now listening frame. 330us
302 // 387 = 0x19 0001 1001
303 // 480 = 0x19
304 // 500 = 0x1C 0001 1100
305 uint32_t starttime = GET_TICKS;
306 //uint16_t mywait = TAG_FRAME_WAIT - (starttime - sendFrameStop);
307 //uint16_t mywait = 495 - (starttime - sendFrameStop);
308 if ( bits == 6) {
309 //Dbprintf("6 WAIT %d", 495 - 9 - 9 );
310 WaitTicks( 495 - 9 - 9 );
311 } else {
312 //Dbprintf("x WAIT %d", mywait );
313 //WaitTicks( mywait );
314 WaitTicks( 450 );
315 }
316
317 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
318
319 while ( i-- ){
320 edges = 0;
321 uint8_t adjust = 0;
322 while ( GET_TICKS < next_bit_at) {
323
324 level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
325
326 if (level != old_level)
327 ++edges;
328
329 old_level = level;
330
331 if(edges > 20 && adjust == 0) {
332 next_bit_at -= 15;
333 adjust = 1;
334 }
335 }
336
337 next_bit_at += TAG_BIT_PERIOD;
338
339 // We expect 42 edges == ONE
340 //if (edges > 20 && edges < 64)
341 if ( edges > 20 )
342 data ^= the_bit;
343
344 the_bit <<= 1;
345 }
346
347 // output
348 f->data = data;
349 f->bits = bits;
350
351 uint8_t cmdbytes[] = {
352 bits,
353 BYTEx(data,0),
354 BYTEx(data,1),
355 BYTEx(data, 0) ^ BYTEx(lsfr,0),
356 BYTEx(data, 1) ^ BYTEx(lsfr,1),
357 prngstart,
358 legic_prng_count()
359 };
360 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
361 }
362
363 // Setup pm3 as a Legic Reader
364 static uint32_t setup_phase_reader(uint8_t iv) {
365
366 // Switch on carrier and let the tag charge for 1ms
367 HIGH(GPIO_SSC_DOUT);
368 WaitUS(1000);
369
370 ResetTicks();
371
372 // no keystream yet
373 legic_prng_init(0);
374
375 // send IV handshake
376 frame_sendAsReader(iv, 7);
377
378 // Now both tag and reader has same IV. Prng can start.
379 legic_prng_init(iv);
380
381 frame_receiveAsReader(&current_frame, 6);
382
383 // fixed delay before sending ack.
384 WaitTicks(366); // 244us
385 legic_prng_forward(1); //240us / 100 == 2.4 iterations
386
387 // Send obsfuscated acknowledgment frame.
388 // 0x19 = 0x18 MIM22, 0x01 LSB READCMD
389 // 0x39 = 0x38 MIM256, MIM1024 0x01 LSB READCMD
390 switch ( current_frame.data ) {
391 case 0x0D: frame_sendAsReader(0x19, 6); break;
392 case 0x1D:
393 case 0x3D: frame_sendAsReader(0x39, 6); break;
394 default: break;
395 }
396 return current_frame.data;
397 }
398
399 static void LegicCommonInit(void) {
400
401 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
402 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
403 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
404
405 /* Bitbang the transmitter */
406 LOW(GPIO_SSC_DOUT);
407 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
408 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
409
410 // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
411 cardmem = BigBuf_malloc(LEGIC_CARD_MEMSIZE);
412 memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE);
413
414 clear_trace();
415 set_tracing(TRUE);
416 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
417
418 StartTicks();
419 }
420
421 // Switch off carrier, make sure tag is reset
422 static void switch_off_tag_rwd(void) {
423 LOW(GPIO_SSC_DOUT);
424 WaitUS(20);
425 WDT_HIT();
426 set_tracing(FALSE);
427 }
428
429 // calculate crc4 for a legic READ command
430 // 5,8,10 address size.
431 static uint32_t legic4Crc(uint8_t legicCmd, uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
432 crc_clear(&legic_crc);
433 //uint32_t temp = (value << cmd_sz) | (byte_index << 1) | legicCmd;
434 //crc_update(&legic_crc, temp, cmd_sz + 8 );
435 crc_update(&legic_crc, 1, 1); /* CMD_READ */
436 crc_update(&legic_crc, byte_index, cmd_sz-1);
437 crc_update(&legic_crc, value, 8);
438 return crc_finish(&legic_crc);
439 }
440
441 int legic_read_byte(int byte_index, int cmd_sz) {
442
443 uint8_t byte = 0, crc = 0, calcCrc = 0;
444 uint32_t cmd = (byte_index << 1) | LEGIC_READ;
445
446 // (us)| ticks
447 // -------------
448 // 330 | 495
449 // 460 | 690
450 // 258 | 387
451 // 244 | 366
452 WaitTicks(387);
453 legic_prng_forward(4); // 460 / 100 = 4.6 iterations
454
455 frame_sendAsReader(cmd, cmd_sz);
456 frame_receiveAsReader(&current_frame, 12);
457
458 byte = BYTEx(current_frame.data, 0);
459 calcCrc = legic4Crc(LEGIC_READ, byte_index, byte, cmd_sz);
460 crc = BYTEx(current_frame.data, 1);
461
462 if( calcCrc != crc ) {
463 Dbprintf("!!! crc mismatch: expected %x but got %x !!!", calcCrc, crc);
464 return -1;
465 }
466 return byte;
467 }
468
469 /*
470 * - assemble a write_cmd_frame with crc and send it
471 * - wait until the tag sends back an ACK ('1' bit unencrypted)
472 * - forward the prng based on the timing
473 */
474 //int legic_write_byte(int byte, int addr, int addr_sz, int PrngCorrection) {
475 int legic_write_byte(uint8_t byte, uint16_t addr, uint8_t addr_sz) {
476
477 //do not write UID, CRC at offset 0-4.
478 if (addr <= 4) return 0;
479
480 // crc
481 crc_clear(&legic_crc);
482 crc_update(&legic_crc, 0, 1); /* CMD_WRITE */
483 crc_update(&legic_crc, addr, addr_sz);
484 crc_update(&legic_crc, byte, 8);
485 uint32_t crc = crc_finish(&legic_crc);
486
487 uint32_t crc2 = legic4Crc(LEGIC_WRITE, addr, byte, addr_sz+1);
488 if ( crc != crc2 )
489 Dbprintf("crc is missmatch");
490
491 // send write command
492 uint32_t cmd = ((crc <<(addr_sz+1+8)) //CRC
493 |(byte <<(addr_sz+1)) //Data
494 |(addr <<1) //Address
495 | LEGIC_WRITE); //CMD = Write
496
497 uint32_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd
498
499 legic_prng_forward(2); /* we wait anyways */
500
501 WaitUS(TAG_FRAME_WAIT);
502
503 frame_sendAsReader(cmd, cmd_sz);
504
505 // wllm-rbnt doesnt have these
506 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
507 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
508
509 // wait for ack
510 int t, old_level = 0, edges = 0;
511 int next_bit_at = 0;
512
513 WaitUS(TAG_FRAME_WAIT);
514
515 for( t = 0; t < 80; ++t) {
516 edges = 0;
517 next_bit_at += TAG_BIT_PERIOD;
518 while(timer->TC_CV < next_bit_at) {
519 int level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
520 if(level != old_level)
521 edges++;
522
523 old_level = level;
524 }
525 if(edges > 20 && edges < 60) { /* expected are 42 edges */
526 int t = timer->TC_CV;
527 int c = t / TAG_BIT_PERIOD;
528
529 ResetTimer(timer);
530 legic_prng_forward(c);
531 return 0;
532 }
533 }
534
535 ResetTimer(timer);
536 return -1;
537 }
538
539 int LegicRfReader(int offset, int bytes, int iv) {
540
541 uint16_t byte_index = 0;
542 uint8_t cmd_sz = 0, isOK = 1;
543 int card_sz = 0;
544
545 LegicCommonInit();
546
547 uint32_t tag_type = setup_phase_reader(iv);
548
549 switch_off_tag_rwd();
550
551 switch(tag_type) {
552 case 0x0d:
553 if ( MF_DBGLEVEL >= 2) DbpString("MIM22 card found, reading card");
554 cmd_sz = 6;
555 card_sz = 22;
556 break;
557 case 0x1d:
558 if ( MF_DBGLEVEL >= 2) DbpString("MIM256 card found, reading card");
559 cmd_sz = 9;
560 card_sz = 256;
561 break;
562 case 0x3d:
563 if ( MF_DBGLEVEL >= 2) DbpString("MIM1024 card found, reading card");
564 cmd_sz = 11;
565 card_sz = 1024;
566 break;
567 default:
568 if ( MF_DBGLEVEL >= 1) Dbprintf("Unknown card format: %x", tag_type);
569 isOK = 0;
570 goto OUT;
571 break;
572 }
573 if (bytes == -1)
574 bytes = card_sz;
575
576 if (bytes + offset >= card_sz)
577 bytes = card_sz - offset;
578
579 // Start setup and read bytes.
580 setup_phase_reader(iv);
581
582 LED_B_ON();
583 while (byte_index < bytes) {
584 int r = legic_read_byte(byte_index + offset, cmd_sz);
585
586 if (r == -1 || BUTTON_PRESS()) {
587 if ( MF_DBGLEVEL >= 3) DbpString("operation aborted");
588 isOK = 0;
589 goto OUT;
590 }
591 cardmem[++byte_index] = r;
592 WDT_HIT();
593 }
594
595 OUT:
596 WDT_HIT();
597 switch_off_tag_rwd();
598 LEDsoff();
599 uint8_t len = (bytes & 0x3FF);
600 cmd_send(CMD_ACK,isOK,len,0,cardmem,len);
601 return 0;
602 }
603
604 /*int _LegicRfWriter(int offset, int bytes, int addr_sz, uint8_t *BigBuf, int RoundBruteforceValue) {
605 int byte_index=0;
606
607 LED_B_ON();
608 setup_phase_reader(iv);
609 //legic_prng_forward(2);
610 while(byte_index < bytes) {
611 int r;
612
613 //check if the DCF should be changed
614 if ( (offset == 0x05) && (bytes == 0x02) ) {
615 //write DCF in reverse order (addr 0x06 before 0x05)
616 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
617 //legic_prng_forward(1);
618 if(r == 0) {
619 byte_index++;
620 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
621 }
622 //legic_prng_forward(1);
623 }
624 else {
625 r = legic_write_byte(BigBuf[byte_index+offset], byte_index+offset, addr_sz, RoundBruteforceValue);
626 }
627 if((r != 0) || BUTTON_PRESS()) {
628 Dbprintf("operation aborted @ 0x%03.3x", byte_index);
629 switch_off_tag_rwd();
630 LED_B_OFF();
631 LED_C_OFF();
632 return -1;
633 }
634
635 WDT_HIT();
636 byte_index++;
637 if(byte_index & 0x10) LED_C_ON(); else LED_C_OFF();
638 }
639 LED_B_OFF();
640 LED_C_OFF();
641 DbpString("write successful");
642 return 0;
643 }*/
644
645 void LegicRfWriter(int offset, int bytes, int iv) {
646
647 int byte_index = 0, addr_sz = 0;
648
649 LegicCommonInit();
650
651 if ( MF_DBGLEVEL >= 2) DbpString("setting up legic card");
652
653 uint32_t tag_type = setup_phase_reader(iv);
654
655 switch_off_tag_rwd();
656
657 switch(tag_type) {
658 case 0x0d:
659 if(offset+bytes > 22) {
660 Dbprintf("Error: can not write to 0x%03.3x on MIM22", offset + bytes);
661 return;
662 }
663 addr_sz = 5;
664 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM22 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset + bytes);
665 break;
666 case 0x1d:
667 if(offset+bytes > 0x100) {
668 Dbprintf("Error: can not write to 0x%03.3x on MIM256", offset + bytes);
669 return;
670 }
671 addr_sz = 8;
672 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM256 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset + bytes);
673 break;
674 case 0x3d:
675 if(offset+bytes > 0x400) {
676 Dbprintf("Error: can not write to 0x%03.3x on MIM1024", offset + bytes);
677 return;
678 }
679 addr_sz = 10;
680 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM1024 card found, writing 0x%03.3x - 0x%03.3x ...", offset, offset + bytes);
681 break;
682 default:
683 Dbprintf("No or unknown card found, aborting");
684 return;
685 }
686
687 LED_B_ON();
688 setup_phase_reader(iv);
689 int r = 0;
690 while(byte_index < bytes) {
691
692 //check if the DCF should be changed
693 if ( ((byte_index+offset) == 0x05) && (bytes >= 0x02) ) {
694 //write DCF in reverse order (addr 0x06 before 0x05)
695 r = legic_write_byte(cardmem[(0x06-byte_index)], (0x06-byte_index), addr_sz);
696
697 // write second byte on success...
698 if(r == 0) {
699 byte_index++;
700 r = legic_write_byte(cardmem[(0x06-byte_index)], (0x06-byte_index), addr_sz);
701 }
702 }
703 else {
704 r = legic_write_byte(cardmem[byte_index+offset], byte_index+offset, addr_sz);
705 }
706
707 if ((r != 0) || BUTTON_PRESS()) {
708 Dbprintf("operation aborted @ 0x%03.3x", byte_index);
709 switch_off_tag_rwd();
710 LEDsoff();
711 return;
712 }
713
714 WDT_HIT();
715 byte_index++;
716 }
717 LEDsoff();
718 if ( MF_DBGLEVEL >= 1) DbpString("write successful");
719 }
720
721 void LegicRfRawWriter(int address, int byte, int iv) {
722
723 int byte_index = 0, addr_sz = 0;
724
725 LegicCommonInit();
726
727 if ( MF_DBGLEVEL >= 2) DbpString("setting up legic card");
728
729 uint32_t tag_type = setup_phase_reader(iv);
730
731 switch_off_tag_rwd();
732
733 switch(tag_type) {
734 case 0x0d:
735 if(address > 22) {
736 Dbprintf("Error: can not write to 0x%03.3x on MIM22", address);
737 return;
738 }
739 addr_sz = 5;
740 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM22 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address, byte);
741 break;
742 case 0x1d:
743 if(address > 0x100) {
744 Dbprintf("Error: can not write to 0x%03.3x on MIM256", address);
745 return;
746 }
747 addr_sz = 8;
748 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM256 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address, byte);
749 break;
750 case 0x3d:
751 if(address > 0x400) {
752 Dbprintf("Error: can not write to 0x%03.3x on MIM1024", address);
753 return;
754 }
755 addr_sz = 10;
756 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM1024 card found, writing at addr 0x%03.3x - value 0x%03.3x ...", address, byte);
757 break;
758 default:
759 Dbprintf("No or unknown card found, aborting");
760 return;
761 }
762
763 Dbprintf("integer value: %d address: %d addr_sz: %d", byte, address, addr_sz);
764 LED_B_ON();
765
766 setup_phase_reader(iv);
767
768 int r = legic_write_byte(byte, address, addr_sz);
769
770 if((r != 0) || BUTTON_PRESS()) {
771 Dbprintf("operation aborted @ 0x%03.3x (%1d)", byte_index, r);
772 switch_off_tag_rwd();
773 LEDsoff();
774 return;
775 }
776
777 LEDsoff();
778 if ( MF_DBGLEVEL >= 1) DbpString("write successful");
779 }
780
781 void LegicRfInfo(void){
782
783 LegicCommonInit();
784 uint32_t tag_type = setup_phase_reader(0x55);
785 uint8_t cmd_sz = 0;
786 uint16_t card_sz = 0;
787
788 switch(tag_type) {
789 case 0x0d:
790 cmd_sz = 6;
791 card_sz = 22;
792 break;
793 case 0x1d:
794 cmd_sz = 9;
795 card_sz = 256;
796 break;
797 case 0x3d:
798 cmd_sz = 11;
799 card_sz = 1024;
800 break;
801 default:
802 cmd_send(CMD_ACK,0,0,0,0,0);
803 goto OUT;
804 }
805
806 // read UID bytes.
807 uint8_t uid[] = {0,0,0,0};
808 for ( uint8_t i = 0; i < sizeof(uid); ++i) {
809 int r = legic_read_byte(i, cmd_sz);
810 if ( r == -1 ) {
811 cmd_send(CMD_ACK,0,0,0,0,0);
812 goto OUT;
813 }
814 uid[i] = r & 0xFF;
815 }
816
817 cmd_send(CMD_ACK,1,card_sz,0,uid,sizeof(uid));
818 OUT:
819 switch_off_tag_rwd();
820 LEDsoff();
821
822 }
823
824 /* Handle (whether to respond) a frame in tag mode
825 * Only called when simulating a tag.
826 */
827 static void frame_handle_tag(struct legic_frame const * const f)
828 {
829 uint8_t *BigBuf = BigBuf_get_addr();
830
831 /* First Part of Handshake (IV) */
832 if(f->bits == 7) {
833
834 LED_C_ON();
835
836 // Reset prng timer
837 ResetTimer(prng_timer);
838
839 legic_prng_init(f->data);
840 frame_send_tag(0x3d, 6, 1); /* 0x3d^0x26 = 0x1B */
841 legic_state = STATE_IV;
842 legic_read_count = 0;
843 legic_prng_bc = 0;
844 legic_prng_iv = f->data;
845
846
847 ResetTimer(timer);
848 WaitUS(280);
849 return;
850 }
851
852 /* 0x19==??? */
853 if(legic_state == STATE_IV) {
854 int local_key = get_key_stream(3, 6);
855 int xored = 0x39 ^ local_key;
856 if((f->bits == 6) && (f->data == xored)) {
857 legic_state = STATE_CON;
858
859 ResetTimer(timer);
860 WaitUS(200);
861 return;
862
863 } else {
864 legic_state = STATE_DISCON;
865 LED_C_OFF();
866 Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored);
867 return;
868 }
869 }
870
871 /* Read */
872 if(f->bits == 11) {
873 if(legic_state == STATE_CON) {
874 int key = get_key_stream(2, 11); //legic_phase_drift, 11);
875 int addr = f->data ^ key; addr = addr >> 1;
876 int data = BigBuf[addr];
877 int hash = legic4Crc(LEGIC_READ, addr, data, 11) << 8;
878 BigBuf[OFFSET_LOG+legic_read_count] = (uint8_t)addr;
879 legic_read_count++;
880
881 //Dbprintf("Data:%03.3x, key:%03.3x, addr: %03.3x, read_c:%u", f->data, key, addr, read_c);
882 legic_prng_forward(legic_reqresp_drift);
883
884 frame_send_tag(hash | data, 12, 1);
885
886 ResetTimer(timer);
887 legic_prng_forward(2);
888 WaitUS(180);
889 return;
890 }
891 }
892
893 /* Write */
894 if(f->bits == 23) {
895 int key = get_key_stream(-1, 23); //legic_frame_drift, 23);
896 int addr = f->data ^ key; addr = addr >> 1; addr = addr & 0x3ff;
897 int data = f->data ^ key; data = data >> 11; data = data & 0xff;
898
899 /* write command */
900 legic_state = STATE_DISCON;
901 LED_C_OFF();
902 Dbprintf("write - addr: %x, data: %x", addr, data);
903 return;
904 }
905
906 if(legic_state != STATE_DISCON) {
907 Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count);
908 int i;
909 Dbprintf("IV: %03.3x", legic_prng_iv);
910 for(i = 0; i<legic_read_count; i++) {
911 Dbprintf("Read Nb: %u, Addr: %u", i, BigBuf[OFFSET_LOG+i]);
912 }
913
914 for(i = -1; i<legic_read_count; i++) {
915 uint32_t t;
916 t = BigBuf[OFFSET_LOG+256+i*4];
917 t |= BigBuf[OFFSET_LOG+256+i*4+1] << 8;
918 t |= BigBuf[OFFSET_LOG+256+i*4+2] <<16;
919 t |= BigBuf[OFFSET_LOG+256+i*4+3] <<24;
920
921 Dbprintf("Cycles: %u, Frame Length: %u, Time: %u",
922 BigBuf[OFFSET_LOG+128+i],
923 BigBuf[OFFSET_LOG+384+i],
924 t);
925 }
926 }
927 legic_state = STATE_DISCON;
928 legic_read_count = 0;
929 SpinDelay(10);
930 LED_C_OFF();
931 return;
932 }
933
934 /* Read bit by bit untill full frame is received
935 * Call to process frame end answer
936 */
937 static void emit(int bit) {
938
939 switch (bit) {
940 case 1:
941 frame_append_bit(&current_frame, 1);
942 break;
943 case 0:
944 frame_append_bit(&current_frame, 0);
945 break;
946 default:
947 if(current_frame.bits <= 4) {
948 frame_clean(&current_frame);
949 } else {
950 frame_handle_tag(&current_frame);
951 frame_clean(&current_frame);
952 }
953 WDT_HIT();
954 break;
955 }
956 }
957
958 void LegicRfSimulate(int phase, int frame, int reqresp)
959 {
960 /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
961 * modulation mode set to 212kHz subcarrier. We are getting the incoming raw
962 * envelope waveform on DIN and should send our response on DOUT.
963 *
964 * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
965 * measure the time between two rising edges on DIN, and no encoding on the
966 * subcarrier from card to reader, so we'll just shift out our verbatim data
967 * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
968 * seems to be 300us-ish.
969 */
970
971 legic_phase_drift = phase;
972 legic_frame_drift = frame;
973 legic_reqresp_drift = reqresp;
974
975 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
976 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
977 FpgaSetupSsc();
978 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
979
980 /* Bitbang the receiver */
981 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
982 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
983
984 //setup_timer();
985 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
986
987 int old_level = 0;
988 int active = 0;
989 legic_state = STATE_DISCON;
990
991 LED_B_ON();
992 DbpString("Starting Legic emulator, press button to end");
993
994 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
995 int level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
996 int time = timer->TC_CV;
997
998 if(level != old_level) {
999 if(level == 1) {
1000 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1001
1002 if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
1003 /* 1 bit */
1004 emit(1);
1005 active = 1;
1006 LED_A_ON();
1007 } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
1008 /* 0 bit */
1009 emit(0);
1010 active = 1;
1011 LED_A_ON();
1012 } else if (active) {
1013 /* invalid */
1014 emit(-1);
1015 active = 0;
1016 LED_A_OFF();
1017 }
1018 }
1019 }
1020
1021 /* Frame end */
1022 if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) {
1023 emit(-1);
1024 active = 0;
1025 LED_A_OFF();
1026 }
1027
1028 if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) {
1029 timer->TC_CCR = AT91C_TC_CLKDIS;
1030 }
1031
1032 old_level = level;
1033 WDT_HIT();
1034 }
1035 if ( MF_DBGLEVEL >= 1) DbpString("Stopped");
1036 LEDsoff();
1037 }
1038
1039 //-----------------------------------------------------------------------------
1040 // Code up a string of octets at layer 2 (including CRC, we don't generate
1041 // that here) so that they can be transmitted to the reader. Doesn't transmit
1042 // them yet, just leaves them ready to send in ToSend[].
1043 //-----------------------------------------------------------------------------
1044 // static void CodeLegicAsTag(const uint8_t *cmd, int len)
1045 // {
1046 // int i;
1047
1048 // ToSendReset();
1049
1050 // // Transmit a burst of ones, as the initial thing that lets the
1051 // // reader get phase sync. This (TR1) must be > 80/fs, per spec,
1052 // // but tag that I've tried (a Paypass) exceeds that by a fair bit,
1053 // // so I will too.
1054 // for(i = 0; i < 20; i++) {
1055 // ToSendStuffBit(1);
1056 // ToSendStuffBit(1);
1057 // ToSendStuffBit(1);
1058 // ToSendStuffBit(1);
1059 // }
1060
1061 // // Send SOF.
1062 // for(i = 0; i < 10; i++) {
1063 // ToSendStuffBit(0);
1064 // ToSendStuffBit(0);
1065 // ToSendStuffBit(0);
1066 // ToSendStuffBit(0);
1067 // }
1068 // for(i = 0; i < 2; i++) {
1069 // ToSendStuffBit(1);
1070 // ToSendStuffBit(1);
1071 // ToSendStuffBit(1);
1072 // ToSendStuffBit(1);
1073 // }
1074
1075 // for(i = 0; i < len; i++) {
1076 // int j;
1077 // uint8_t b = cmd[i];
1078
1079 // // Start bit
1080 // ToSendStuffBit(0);
1081 // ToSendStuffBit(0);
1082 // ToSendStuffBit(0);
1083 // ToSendStuffBit(0);
1084
1085 // // Data bits
1086 // for(j = 0; j < 8; j++) {
1087 // if(b & 1) {
1088 // ToSendStuffBit(1);
1089 // ToSendStuffBit(1);
1090 // ToSendStuffBit(1);
1091 // ToSendStuffBit(1);
1092 // } else {
1093 // ToSendStuffBit(0);
1094 // ToSendStuffBit(0);
1095 // ToSendStuffBit(0);
1096 // ToSendStuffBit(0);
1097 // }
1098 // b >>= 1;
1099 // }
1100
1101 // // Stop bit
1102 // ToSendStuffBit(1);
1103 // ToSendStuffBit(1);
1104 // ToSendStuffBit(1);
1105 // ToSendStuffBit(1);
1106 // }
1107
1108 // // Send EOF.
1109 // for(i = 0; i < 10; i++) {
1110 // ToSendStuffBit(0);
1111 // ToSendStuffBit(0);
1112 // ToSendStuffBit(0);
1113 // ToSendStuffBit(0);
1114 // }
1115 // for(i = 0; i < 2; i++) {
1116 // ToSendStuffBit(1);
1117 // ToSendStuffBit(1);
1118 // ToSendStuffBit(1);
1119 // ToSendStuffBit(1);
1120 // }
1121
1122 // // Convert from last byte pos to length
1123 // ToSendMax++;
1124 // }
1125
1126 //-----------------------------------------------------------------------------
1127 // The software UART that receives commands from the reader, and its state
1128 // variables.
1129 //-----------------------------------------------------------------------------
1130 /*
1131 static struct {
1132 enum {
1133 STATE_UNSYNCD,
1134 STATE_GOT_FALLING_EDGE_OF_SOF,
1135 STATE_AWAITING_START_BIT,
1136 STATE_RECEIVING_DATA
1137 } state;
1138 uint16_t shiftReg;
1139 int bitCnt;
1140 int byteCnt;
1141 int byteCntMax;
1142 int posCnt;
1143 uint8_t *output;
1144 } Uart;
1145 */
1146 /* Receive & handle a bit coming from the reader.
1147 *
1148 * This function is called 4 times per bit (every 2 subcarrier cycles).
1149 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1150 *
1151 * LED handling:
1152 * LED A -> ON once we have received the SOF and are expecting the rest.
1153 * LED A -> OFF once we have received EOF or are in error state or unsynced
1154 *
1155 * Returns: true if we received a EOF
1156 * false if we are still waiting for some more
1157 */
1158 // static RAMFUNC int HandleLegicUartBit(uint8_t bit)
1159 // {
1160 // switch(Uart.state) {
1161 // case STATE_UNSYNCD:
1162 // if(!bit) {
1163 // // we went low, so this could be the beginning of an SOF
1164 // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
1165 // Uart.posCnt = 0;
1166 // Uart.bitCnt = 0;
1167 // }
1168 // break;
1169
1170 // case STATE_GOT_FALLING_EDGE_OF_SOF:
1171 // Uart.posCnt++;
1172 // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
1173 // if(bit) {
1174 // if(Uart.bitCnt > 9) {
1175 // // we've seen enough consecutive
1176 // // zeros that it's a valid SOF
1177 // Uart.posCnt = 0;
1178 // Uart.byteCnt = 0;
1179 // Uart.state = STATE_AWAITING_START_BIT;
1180 // LED_A_ON(); // Indicate we got a valid SOF
1181 // } else {
1182 // // didn't stay down long enough
1183 // // before going high, error
1184 // Uart.state = STATE_UNSYNCD;
1185 // }
1186 // } else {
1187 // // do nothing, keep waiting
1188 // }
1189 // Uart.bitCnt++;
1190 // }
1191 // if(Uart.posCnt >= 4) Uart.posCnt = 0;
1192 // if(Uart.bitCnt > 12) {
1193 // // Give up if we see too many zeros without
1194 // // a one, too.
1195 // LED_A_OFF();
1196 // Uart.state = STATE_UNSYNCD;
1197 // }
1198 // break;
1199
1200 // case STATE_AWAITING_START_BIT:
1201 // Uart.posCnt++;
1202 // if(bit) {
1203 // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
1204 // // stayed high for too long between
1205 // // characters, error
1206 // Uart.state = STATE_UNSYNCD;
1207 // }
1208 // } else {
1209 // // falling edge, this starts the data byte
1210 // Uart.posCnt = 0;
1211 // Uart.bitCnt = 0;
1212 // Uart.shiftReg = 0;
1213 // Uart.state = STATE_RECEIVING_DATA;
1214 // }
1215 // break;
1216
1217 // case STATE_RECEIVING_DATA:
1218 // Uart.posCnt++;
1219 // if(Uart.posCnt == 2) {
1220 // // time to sample a bit
1221 // Uart.shiftReg >>= 1;
1222 // if(bit) {
1223 // Uart.shiftReg |= 0x200;
1224 // }
1225 // Uart.bitCnt++;
1226 // }
1227 // if(Uart.posCnt >= 4) {
1228 // Uart.posCnt = 0;
1229 // }
1230 // if(Uart.bitCnt == 10) {
1231 // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
1232 // {
1233 // // this is a data byte, with correct
1234 // // start and stop bits
1235 // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
1236 // Uart.byteCnt++;
1237
1238 // if(Uart.byteCnt >= Uart.byteCntMax) {
1239 // // Buffer overflowed, give up
1240 // LED_A_OFF();
1241 // Uart.state = STATE_UNSYNCD;
1242 // } else {
1243 // // so get the next byte now
1244 // Uart.posCnt = 0;
1245 // Uart.state = STATE_AWAITING_START_BIT;
1246 // }
1247 // } else if (Uart.shiftReg == 0x000) {
1248 // // this is an EOF byte
1249 // LED_A_OFF(); // Finished receiving
1250 // Uart.state = STATE_UNSYNCD;
1251 // if (Uart.byteCnt != 0) {
1252 // return TRUE;
1253 // }
1254 // } else {
1255 // // this is an error
1256 // LED_A_OFF();
1257 // Uart.state = STATE_UNSYNCD;
1258 // }
1259 // }
1260 // break;
1261
1262 // default:
1263 // LED_A_OFF();
1264 // Uart.state = STATE_UNSYNCD;
1265 // break;
1266 // }
1267
1268 // return FALSE;
1269 // }
1270 /*
1271
1272 static void UartReset() {
1273 Uart.byteCntMax = 3;
1274 Uart.state = STATE_UNSYNCD;
1275 Uart.byteCnt = 0;
1276 Uart.bitCnt = 0;
1277 Uart.posCnt = 0;
1278 memset(Uart.output, 0x00, 3);
1279 }
1280 */
1281 // static void UartInit(uint8_t *data) {
1282 // Uart.output = data;
1283 // UartReset();
1284 // }
1285
1286 //=============================================================================
1287 // An LEGIC reader. We take layer two commands, code them
1288 // appropriately, and then send them to the tag. We then listen for the
1289 // tag's response, which we leave in the buffer to be demodulated on the
1290 // PC side.
1291 //=============================================================================
1292 /*
1293 static struct {
1294 enum {
1295 DEMOD_UNSYNCD,
1296 DEMOD_PHASE_REF_TRAINING,
1297 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
1298 DEMOD_GOT_FALLING_EDGE_OF_SOF,
1299 DEMOD_AWAITING_START_BIT,
1300 DEMOD_RECEIVING_DATA
1301 } state;
1302 int bitCount;
1303 int posCount;
1304 int thisBit;
1305 uint16_t shiftReg;
1306 uint8_t *output;
1307 int len;
1308 int sumI;
1309 int sumQ;
1310 } Demod;
1311 */
1312 /*
1313 * Handles reception of a bit from the tag
1314 *
1315 * This function is called 2 times per bit (every 4 subcarrier cycles).
1316 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1317 *
1318 * LED handling:
1319 * LED C -> ON once we have received the SOF and are expecting the rest.
1320 * LED C -> OFF once we have received EOF or are unsynced
1321 *
1322 * Returns: true if we received a EOF
1323 * false if we are still waiting for some more
1324 *
1325 */
1326
1327 /*
1328 static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq)
1329 {
1330 int v = 0;
1331 int ai = ABS(ci);
1332 int aq = ABS(cq);
1333 int halfci = (ai >> 1);
1334 int halfcq = (aq >> 1);
1335
1336 switch(Demod.state) {
1337 case DEMOD_UNSYNCD:
1338
1339 CHECK_FOR_SUBCARRIER()
1340
1341 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
1342 Demod.state = DEMOD_PHASE_REF_TRAINING;
1343 Demod.sumI = ci;
1344 Demod.sumQ = cq;
1345 Demod.posCount = 1;
1346 }
1347 break;
1348
1349 case DEMOD_PHASE_REF_TRAINING:
1350 if(Demod.posCount < 8) {
1351
1352 CHECK_FOR_SUBCARRIER()
1353
1354 if (v > SUBCARRIER_DETECT_THRESHOLD) {
1355 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
1356 // note: synchronization time > 80 1/fs
1357 Demod.sumI += ci;
1358 Demod.sumQ += cq;
1359 ++Demod.posCount;
1360 } else {
1361 // subcarrier lost
1362 Demod.state = DEMOD_UNSYNCD;
1363 }
1364 } else {
1365 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
1366 }
1367 break;
1368
1369 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
1370
1371 MAKE_SOFT_DECISION()
1372
1373 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
1374 // logic '0' detected
1375 if (v <= 0) {
1376
1377 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
1378
1379 // start of SOF sequence
1380 Demod.posCount = 0;
1381 } else {
1382 // maximum length of TR1 = 200 1/fs
1383 if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
1384 }
1385 ++Demod.posCount;
1386 break;
1387
1388 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
1389 ++Demod.posCount;
1390
1391 MAKE_SOFT_DECISION()
1392
1393 if(v > 0) {
1394 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
1395 if(Demod.posCount < 10*2) {
1396 Demod.state = DEMOD_UNSYNCD;
1397 } else {
1398 LED_C_ON(); // Got SOF
1399 Demod.state = DEMOD_AWAITING_START_BIT;
1400 Demod.posCount = 0;
1401 Demod.len = 0;
1402 }
1403 } else {
1404 // low phase of SOF too long (> 12 etu)
1405 if(Demod.posCount > 13*2) {
1406 Demod.state = DEMOD_UNSYNCD;
1407 LED_C_OFF();
1408 }
1409 }
1410 break;
1411
1412 case DEMOD_AWAITING_START_BIT:
1413 ++Demod.posCount;
1414
1415 MAKE_SOFT_DECISION()
1416
1417 if(v > 0) {
1418 // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
1419 if(Demod.posCount > 3*2) {
1420 Demod.state = DEMOD_UNSYNCD;
1421 LED_C_OFF();
1422 }
1423 } else {
1424 // start bit detected
1425 Demod.bitCount = 0;
1426 Demod.posCount = 1; // this was the first half
1427 Demod.thisBit = v;
1428 Demod.shiftReg = 0;
1429 Demod.state = DEMOD_RECEIVING_DATA;
1430 }
1431 break;
1432
1433 case DEMOD_RECEIVING_DATA:
1434
1435 MAKE_SOFT_DECISION()
1436
1437 if(Demod.posCount == 0) {
1438 // first half of bit
1439 Demod.thisBit = v;
1440 Demod.posCount = 1;
1441 } else {
1442 // second half of bit
1443 Demod.thisBit += v;
1444 Demod.shiftReg >>= 1;
1445 // logic '1'
1446 if(Demod.thisBit > 0)
1447 Demod.shiftReg |= 0x200;
1448
1449 ++Demod.bitCount;
1450
1451 if(Demod.bitCount == 10) {
1452
1453 uint16_t s = Demod.shiftReg;
1454
1455 if((s & 0x200) && !(s & 0x001)) {
1456 // stop bit == '1', start bit == '0'
1457 uint8_t b = (s >> 1);
1458 Demod.output[Demod.len] = b;
1459 ++Demod.len;
1460 Demod.state = DEMOD_AWAITING_START_BIT;
1461 } else {
1462 Demod.state = DEMOD_UNSYNCD;
1463 LED_C_OFF();
1464
1465 if(s == 0x000) {
1466 // This is EOF (start, stop and all data bits == '0'
1467 return TRUE;
1468 }
1469 }
1470 }
1471 Demod.posCount = 0;
1472 }
1473 break;
1474
1475 default:
1476 Demod.state = DEMOD_UNSYNCD;
1477 LED_C_OFF();
1478 break;
1479 }
1480 return FALSE;
1481 }
1482 */
1483 /*
1484 // Clear out the state of the "UART" that receives from the tag.
1485 static void DemodReset() {
1486 Demod.len = 0;
1487 Demod.state = DEMOD_UNSYNCD;
1488 Demod.posCount = 0;
1489 Demod.sumI = 0;
1490 Demod.sumQ = 0;
1491 Demod.bitCount = 0;
1492 Demod.thisBit = 0;
1493 Demod.shiftReg = 0;
1494 memset(Demod.output, 0x00, 3);
1495 }
1496
1497 static void DemodInit(uint8_t *data) {
1498 Demod.output = data;
1499 DemodReset();
1500 }
1501 */
1502
1503 /*
1504 * Demodulate the samples we received from the tag, also log to tracebuffer
1505 * quiet: set to 'TRUE' to disable debug output
1506 */
1507
1508 /*
1509 #define LEGIC_DMA_BUFFER_SIZE 256
1510
1511 static void GetSamplesForLegicDemod(int n, bool quiet)
1512 {
1513 int max = 0;
1514 bool gotFrame = FALSE;
1515 int lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1516 int ci, cq, samples = 0;
1517
1518 BigBuf_free();
1519
1520 // And put the FPGA in the appropriate mode
1521 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ);
1522
1523 // The response (tag -> reader) that we're receiving.
1524 // Set up the demodulator for tag -> reader responses.
1525 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1526
1527 // The DMA buffer, used to stream samples from the FPGA
1528 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE);
1529 int8_t *upTo = dmaBuf;
1530
1531 // Setup and start DMA.
1532 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){
1533 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1534 return;
1535 }
1536
1537 // Signal field is ON with the appropriate LED:
1538 LED_D_ON();
1539 for(;;) {
1540 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
1541 if(behindBy > max) max = behindBy;
1542
1543 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) {
1544 ci = upTo[0];
1545 cq = upTo[1];
1546 upTo += 2;
1547 if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) {
1548 upTo = dmaBuf;
1549 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
1550 AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE;
1551 }
1552 lastRxCounter -= 2;
1553 if(lastRxCounter <= 0)
1554 lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1555
1556 samples += 2;
1557
1558 gotFrame = HandleLegicSamplesDemod(ci , cq );
1559 if ( gotFrame )
1560 break;
1561 }
1562
1563 if(samples > n || gotFrame)
1564 break;
1565 }
1566
1567 FpgaDisableSscDma();
1568
1569 if (!quiet && Demod.len == 0) {
1570 Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
1571 max,
1572 samples,
1573 gotFrame,
1574 Demod.len,
1575 Demod.sumI,
1576 Demod.sumQ
1577 );
1578 }
1579
1580 //Tracing
1581 if (Demod.len > 0) {
1582 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1583 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
1584 }
1585 }
1586
1587 */
1588
1589 //-----------------------------------------------------------------------------
1590 // Transmit the command (to the tag) that was placed in ToSend[].
1591 //-----------------------------------------------------------------------------
1592 /*
1593 static void TransmitForLegic(void)
1594 {
1595 int c;
1596
1597 FpgaSetupSsc();
1598
1599 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
1600 AT91C_BASE_SSC->SSC_THR = 0xff;
1601
1602 // Signal field is ON with the appropriate Red LED
1603 LED_D_ON();
1604
1605 // Signal we are transmitting with the Green LED
1606 LED_B_ON();
1607 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1608
1609 for(c = 0; c < 10;) {
1610 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1611 AT91C_BASE_SSC->SSC_THR = 0xff;
1612 c++;
1613 }
1614 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1615 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1616 (void)r;
1617 }
1618 WDT_HIT();
1619 }
1620
1621 c = 0;
1622 for(;;) {
1623 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1624 AT91C_BASE_SSC->SSC_THR = ToSend[c];
1625 legic_prng_forward(1); // forward the lfsr
1626 c++;
1627 if(c >= ToSendMax) {
1628 break;
1629 }
1630 }
1631 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1632 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1633 (void)r;
1634 }
1635 WDT_HIT();
1636 }
1637 LED_B_OFF();
1638 }
1639 */
1640
1641 //-----------------------------------------------------------------------------
1642 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1643 // so that it is ready to transmit to the tag using TransmitForLegic().
1644 //-----------------------------------------------------------------------------
1645 /*
1646 static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1647 {
1648 int i, j;
1649 uint8_t b;
1650
1651 ToSendReset();
1652
1653 // Send SOF
1654 for(i = 0; i < 7; i++)
1655 ToSendStuffBit(1);
1656
1657
1658 for(i = 0; i < cmdlen; i++) {
1659 // Start bit
1660 ToSendStuffBit(0);
1661
1662 // Data bits
1663 b = cmd[i];
1664 for(j = 0; j < bits; j++) {
1665 if(b & 1) {
1666 ToSendStuffBit(1);
1667 } else {
1668 ToSendStuffBit(0);
1669 }
1670 b >>= 1;
1671 }
1672 }
1673
1674 // Convert from last character reference to length
1675 ++ToSendMax;
1676 }
1677 */
1678 /**
1679 Convenience function to encode, transmit and trace Legic comms
1680 **/
1681 /*
1682 static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1683 {
1684 CodeLegicBitsAsReader(cmd, cmdlen, bits);
1685 TransmitForLegic();
1686 if (tracing) {
1687 uint8_t parity[1] = {0x00};
1688 LogTrace(cmd, cmdlen, 0, 0, parity, TRUE);
1689 }
1690 }
1691
1692 */
1693 // Set up LEGIC communication
1694 /*
1695 void ice_legic_setup() {
1696
1697 // standard things.
1698 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1699 BigBuf_free(); BigBuf_Clear_ext(false);
1700 clear_trace();
1701 set_tracing(TRUE);
1702 DemodReset();
1703 UartReset();
1704
1705 // Set up the synchronous serial port
1706 FpgaSetupSsc();
1707
1708 // connect Demodulated Signal to ADC:
1709 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1710
1711 // Signal field is on with the appropriate LED
1712 LED_D_ON();
1713 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1714 SpinDelay(20);
1715 // Start the timer
1716 //StartCountSspClk();
1717
1718 // initalize CRC
1719 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
1720
1721 // initalize prng
1722 legic_prng_init(0);
1723 }
1724 */
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