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FIX: the underlaying bug on deviceside code. The SSPCLOCK wasn't reset to zero somet...
[proxmark3-svn] / armsrc / legicrf.c
1 //-----------------------------------------------------------------------------
2 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // LEGIC RF simulation code
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "string.h"
15
16 #include "legicrf.h"
17 #include "legic_prng.h"
18 #include "crc.h"
19
20 static struct legic_frame {
21 int bits;
22 uint32_t data;
23 } current_frame;
24
25 static enum {
26 STATE_DISCON,
27 STATE_IV,
28 STATE_CON,
29 } legic_state;
30
31 static crc_t legic_crc;
32 static int legic_read_count;
33 static uint32_t legic_prng_bc;
34 static uint32_t legic_prng_iv;
35
36 static int legic_phase_drift;
37 static int legic_frame_drift;
38 static int legic_reqresp_drift;
39
40 AT91PS_TC timer;
41 AT91PS_TC prng_timer;
42
43 static void setup_timer(void)
44 {
45 /* Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
46 * this it won't be terribly accurate but should be good enough.
47 */
48 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
49 timer = AT91C_BASE_TC1;
50 timer->TC_CCR = AT91C_TC_CLKDIS;
51 timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
52 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
53
54 /*
55 * Set up Timer 2 to use for measuring time between frames in
56 * tag simulation mode. Runs 4x faster as Timer 1
57 */
58 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);
59 prng_timer = AT91C_BASE_TC2;
60 prng_timer->TC_CCR = AT91C_TC_CLKDIS;
61 prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
62 prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
63 }
64
65 /* At TIMER_CLOCK3 (MCK/32) */
66 #define RWD_TIME_1 150 /* RWD_TIME_PAUSE off, 80us on = 100us */
67 #define RWD_TIME_0 90 /* RWD_TIME_PAUSE off, 40us on = 60us */
68 #define RWD_TIME_PAUSE 30 /* 20us */
69 #define RWD_TIME_FUZZ 20 /* rather generous 13us, since the peak detector + hysteresis fuzz quite a bit */
70 #define TAG_TIME_BIT 150 /* 100us for every bit */
71 #define TAG_TIME_WAIT 490 /* time from RWD frame end to tag frame start, experimentally determined */
72
73 #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
74 #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
75
76 #define SESSION_IV 0x55
77 #define OFFSET_LOG 1024
78
79 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
80
81 /* Generate Keystream */
82 static uint32_t get_key_stream(int skip, int count)
83 {
84 uint32_t key=0; int i;
85
86 /* Use int to enlarge timer tc to 32bit */
87 legic_prng_bc += prng_timer->TC_CV;
88 prng_timer->TC_CCR = AT91C_TC_SWTRG;
89
90 /* If skip == -1, forward prng time based */
91 if(skip == -1) {
92 i = (legic_prng_bc+SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */
93 i -= legic_prng_count(); /* substract cycles of finished frames */
94 i -= count; /* substract current frame length, rewidn to bedinning */
95 legic_prng_forward(i);
96 } else {
97 legic_prng_forward(skip);
98 }
99
100 /* Write Time Data into LOG */
101 uint8_t *BigBuf = BigBuf_get_addr();
102 i = (count == 6) ? -1 : legic_read_count;
103
104 BigBuf[OFFSET_LOG+128+i] = legic_prng_count();
105 BigBuf[OFFSET_LOG+256+i*4] = (legic_prng_bc >> 0) & 0xff;
106 BigBuf[OFFSET_LOG+256+i*4+1] = (legic_prng_bc >> 8) & 0xff;
107 BigBuf[OFFSET_LOG+256+i*4+2] = (legic_prng_bc >>16) & 0xff;
108 BigBuf[OFFSET_LOG+256+i*4+3] = (legic_prng_bc >>24) & 0xff;
109 BigBuf[OFFSET_LOG+384+i] = count;
110
111 /* Generate KeyStream */
112 for(i=0; i<count; i++) {
113 key |= legic_prng_get_bit() << i;
114 legic_prng_forward(1);
115 }
116 return key;
117 }
118
119 /* Send a frame in tag mode, the FPGA must have been set up by
120 * LegicRfSimulate
121 */
122 static void frame_send_tag(uint16_t response, int bits, int crypt)
123 {
124 /* Bitbang the response */
125 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
126 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
127 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
128
129 /* Use time to crypt frame */
130 if(crypt) {
131 legic_prng_forward(2); /* TAG_TIME_WAIT -> shift by 2 */
132 int i; int key = 0;
133 for(i=0; i<bits; i++) {
134 key |= legic_prng_get_bit() << i;
135 legic_prng_forward(1);
136 }
137 //Dbprintf("key = 0x%x", key);
138 response = response ^ key;
139 }
140
141 /* Wait for the frame start */
142 while(timer->TC_CV < (TAG_TIME_WAIT - 30)) ;
143
144 int i;
145 for(i=0; i<bits; i++) {
146 int nextbit = timer->TC_CV + TAG_TIME_BIT;
147 int bit = response & 1;
148 response = response >> 1;
149 if(bit)
150 AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
151 else
152 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
153
154 while(timer->TC_CV < nextbit) ;
155 }
156 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
157 }
158
159 /* Send a frame in reader mode, the FPGA must have been set up by
160 * LegicRfReader
161 */
162 static void frame_send_rwd(uint32_t data, int bits)
163 {
164 /* Start clock */
165 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
166 while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
167
168 int i;
169 for(i=0; i<bits; i++) {
170 int starttime = timer->TC_CV;
171 int pause_end = starttime + RWD_TIME_PAUSE, bit_end;
172 int bit = data & 1;
173 data = data >> 1;
174
175 if(bit ^ legic_prng_get_bit())
176 bit_end = starttime + RWD_TIME_1;
177 else
178 bit_end = starttime + RWD_TIME_0;
179
180
181 /* RWD_TIME_PAUSE time off, then some time on, so that the complete bit time is
182 * RWD_TIME_x, where x is the bit to be transmitted */
183 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
184 while(timer->TC_CV < pause_end) ;
185 AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
186 legic_prng_forward(1); /* bit duration is longest. use this time to forward the lfsr */
187
188 while(timer->TC_CV < bit_end);
189 }
190
191 /* One final pause to mark the end of the frame */
192 int pause_end = timer->TC_CV + RWD_TIME_PAUSE;
193 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
194 while(timer->TC_CV < pause_end) ;
195 AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
196
197
198 /* Reset the timer, to measure time until the start of the tag frame */
199 timer->TC_CCR = AT91C_TC_SWTRG;
200 while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
201 }
202
203 /* Receive a frame from the card in reader emulation mode, the FPGA and
204 * timer must have been set up by LegicRfReader and frame_send_rwd.
205 *
206 * The LEGIC RF protocol from card to reader does not include explicit
207 * frame start/stop information or length information. The reader must
208 * know beforehand how many bits it wants to receive. (Notably: a card
209 * sending a stream of 0-bits is indistinguishable from no card present.)
210 *
211 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
212 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
213 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
214 * for edges. Count the edges in each bit interval. If they are approximately
215 * 0 this was a 0-bit, if they are approximately equal to the number of edges
216 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
217 * timer that's still running from frame_send_rwd in order to get a synchronization
218 * with the frame that we just sent.
219 *
220 * FIXME: Because we're relying on the hysteresis to just do the right thing
221 * the range is severely reduced (and you'll probably also need a good antenna).
222 * So this should be fixed some time in the future for a proper receiver.
223 */
224 static void frame_receive_rwd(struct legic_frame * const f, int bits, int crypt)
225 {
226 uint32_t the_bit = 1; /* Use a bitmask to save on shifts */
227 uint32_t data=0;
228 int i, old_level=0, edges=0;
229 int next_bit_at = TAG_TIME_WAIT;
230
231 if(bits > 32) {
232 bits = 32;
233 }
234
235 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
236 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
237
238 /* we have some time now, precompute the cipher
239 * since we cannot compute it on the fly while reading */
240 legic_prng_forward(2);
241
242 if(crypt) {
243 for(i=0; i<bits; i++) {
244 data |= legic_prng_get_bit() << i;
245 legic_prng_forward(1);
246 }
247 }
248
249 while(timer->TC_CV < next_bit_at) ;
250
251 next_bit_at += TAG_TIME_BIT;
252
253 for(i=0; i<bits; i++) {
254 edges = 0;
255 while(timer->TC_CV < next_bit_at) {
256 int level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
257 if(level != old_level)
258 edges++;
259 old_level = level;
260 }
261 next_bit_at += TAG_TIME_BIT;
262
263 if(edges > 20 && edges < 60) { /* expected are 42 edges */
264 data ^= the_bit;
265 }
266 the_bit <<= 1;
267 }
268
269 f->data = data;
270 f->bits = bits;
271
272 /* Reset the timer, to synchronize the next frame */
273 timer->TC_CCR = AT91C_TC_SWTRG;
274 while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
275 }
276
277 static void frame_append_bit(struct legic_frame * const f, int bit)
278 {
279 if (f->bits >= 31)
280 return; /* Overflow, won't happen */
281
282 f->data |= (bit << f->bits);
283 f->bits++;
284 }
285
286 static void frame_clean(struct legic_frame * const f)
287 {
288 f->data = 0;
289 f->bits = 0;
290 }
291
292 static uint32_t perform_setup_phase_rwd(int iv)
293 {
294
295 /* Switch on carrier and let the tag charge for 1ms */
296 AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
297 SpinDelay(1);
298
299 legic_prng_init(0); /* no keystream yet */
300 frame_send_rwd(iv, 7);
301 legic_prng_init(iv);
302
303 frame_clean(&current_frame);
304 frame_receive_rwd(&current_frame, 6, 1);
305 legic_prng_forward(1); /* we wait anyways */
306 while(timer->TC_CV < 387) ; /* ~ 258us */
307 frame_send_rwd(0x19, 6);
308
309 return current_frame.data;
310 }
311
312 static void LegicCommonInit(void) {
313 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
314 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
315 FpgaSetupSsc();
316 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
317
318 /* Bitbang the transmitter */
319 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
320 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
321 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
322
323 setup_timer();
324
325 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
326 }
327
328 /* Switch off carrier, make sure tag is reset */
329 static void switch_off_tag_rwd(void)
330 {
331 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
332 SpinDelay(10);
333 WDT_HIT();
334 }
335 /* calculate crc for a legic command */
336 static int LegicCRC(int byte_index, int value, int cmd_sz) {
337 crc_clear(&legic_crc);
338 crc_update(&legic_crc, 1, 1); /* CMD_READ */
339 crc_update(&legic_crc, byte_index, cmd_sz-1);
340 crc_update(&legic_crc, value, 8);
341 return crc_finish(&legic_crc);
342 }
343
344 int legic_read_byte(int byte_index, int cmd_sz) {
345 int byte;
346
347 legic_prng_forward(4); /* we wait anyways */
348 while(timer->TC_CV < 387) ; /* ~ 258us + 100us*delay */
349
350 frame_send_rwd(1 | (byte_index << 1), cmd_sz);
351 frame_clean(&current_frame);
352
353 frame_receive_rwd(&current_frame, 12, 1);
354
355 byte = current_frame.data & 0xff;
356
357 if( LegicCRC(byte_index, byte, cmd_sz) != (current_frame.data >> 8) ) {
358 Dbprintf("!!! crc mismatch: expected %x but got %x !!!",
359 LegicCRC(byte_index, current_frame.data & 0xff, cmd_sz),
360 current_frame.data >> 8);
361 return -1;
362 }
363
364 return byte;
365 }
366
367 /* legic_write_byte() is not included, however it's trivial to implement
368 * and here are some hints on what remains to be done:
369 *
370 * * assemble a write_cmd_frame with crc and send it
371 * * wait until the tag sends back an ACK ('1' bit unencrypted)
372 * * forward the prng based on the timing
373 */
374 //int legic_write_byte(int byte, int addr, int addr_sz, int PrngCorrection) {
375 int legic_write_byte(int byte, int addr, int addr_sz) {
376 //do not write UID, CRC
377 if(addr <= 0x04) {
378 return 0;
379 }
380 //== send write command ==============================
381 crc_clear(&legic_crc);
382 crc_update(&legic_crc, 0, 1); /* CMD_WRITE */
383 crc_update(&legic_crc, addr, addr_sz);
384 crc_update(&legic_crc, byte, 8);
385
386 uint32_t crc = crc_finish(&legic_crc);
387 uint32_t cmd = ((crc <<(addr_sz+1+8)) //CRC
388 |(byte <<(addr_sz+1)) //Data
389 |(addr <<1) //Address
390 |(0x00 <<0)); //CMD = W
391 uint32_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd
392
393 legic_prng_forward(4); /* we wait anyways */
394 while(timer->TC_CV < 387) ; /* ~ 258us */
395 frame_send_rwd(cmd, cmd_sz);
396
397 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
398 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
399
400 //== wait for ack ====================================
401 int t, old_level=0, edges=0;
402 int next_bit_at =0;
403 while(timer->TC_CV < 387) ; /* ~ 258us */
404 for(t=0; t<80; t++) {
405 edges = 0;
406 next_bit_at += TAG_TIME_BIT;
407 while(timer->TC_CV < next_bit_at) {
408 int level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
409 if(level != old_level) {
410 edges++;
411 }
412 old_level = level;
413 }
414 if(edges > 20 && edges < 60) { /* expected are 42 edges */
415 int t = timer->TC_CV;
416 int c = t/TAG_TIME_BIT;
417 timer->TC_CCR = AT91C_TC_SWTRG;
418 while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
419 legic_prng_forward(c-1);
420 return 0;
421 }
422 }
423 timer->TC_CCR = AT91C_TC_SWTRG;
424 while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
425 return -1;
426 }
427
428 int LegicRfReader(int offset, int bytes) {
429
430 // ice_legic_setup();
431 // ice_legic_select_card();
432 // return 0;
433
434 int byte_index=0, cmd_sz=0, card_sz=0;
435
436 LegicCommonInit();
437
438 uint8_t *BigBuf = BigBuf_get_addr();
439 memset(BigBuf, 0, 1024);
440
441 DbpString("setting up legic card");
442 uint32_t tag_type = perform_setup_phase_rwd(SESSION_IV);
443 switch_off_tag_rwd(); //we lose to mutch time with dprintf
444 switch(tag_type) {
445 case 0x0d:
446 DbpString("MIM22 card found, reading card ...");
447 cmd_sz = 6;
448 card_sz = 22;
449 break;
450 case 0x1d:
451 DbpString("MIM256 card found, reading card ...");
452 cmd_sz = 9;
453 card_sz = 256;
454 break;
455 case 0x3d:
456 DbpString("MIM1024 card found, reading card ...");
457 cmd_sz = 11;
458 card_sz = 1024;
459 break;
460 default:
461 Dbprintf("Unknown card format: %x",tag_type);
462 return -1;
463 }
464 if(bytes == -1)
465 bytes = card_sz;
466
467 if(bytes+offset >= card_sz)
468 bytes = card_sz-offset;
469
470 perform_setup_phase_rwd(SESSION_IV);
471
472 LED_B_ON();
473 while(byte_index < bytes) {
474 int r = legic_read_byte(byte_index+offset, cmd_sz);
475 if(r == -1 ||BUTTON_PRESS()) {
476 DbpString("operation aborted");
477 switch_off_tag_rwd();
478 LED_B_OFF();
479 LED_C_OFF();
480 return -1;
481 }
482 BigBuf[byte_index] = r;
483 WDT_HIT();
484 byte_index++;
485 if (byte_index & 0x10) LED_C_ON(); else LED_C_OFF();
486 }
487 LED_B_OFF();
488 LED_C_OFF();
489 switch_off_tag_rwd();
490 Dbprintf("Card read, use 'hf legic decode' or");
491 Dbprintf("'data hexsamples %d' to view results", (bytes+7) & ~7);
492 return 0;
493 }
494
495 /*int _LegicRfWriter(int bytes, int offset, int addr_sz, uint8_t *BigBuf, int RoundBruteforceValue) {
496 int byte_index=0;
497
498 LED_B_ON();
499 perform_setup_phase_rwd(SESSION_IV);
500 //legic_prng_forward(2);
501 while(byte_index < bytes) {
502 int r;
503
504 //check if the DCF should be changed
505 if ( (offset == 0x05) && (bytes == 0x02) ) {
506 //write DCF in reverse order (addr 0x06 before 0x05)
507 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
508 //legic_prng_forward(1);
509 if(r == 0) {
510 byte_index++;
511 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
512 }
513 //legic_prng_forward(1);
514 }
515 else {
516 r = legic_write_byte(BigBuf[byte_index+offset], byte_index+offset, addr_sz, RoundBruteforceValue);
517 }
518 if((r != 0) || BUTTON_PRESS()) {
519 Dbprintf("operation aborted @ 0x%03.3x", byte_index);
520 switch_off_tag_rwd();
521 LED_B_OFF();
522 LED_C_OFF();
523 return -1;
524 }
525
526 WDT_HIT();
527 byte_index++;
528 if(byte_index & 0x10) LED_C_ON(); else LED_C_OFF();
529 }
530 LED_B_OFF();
531 LED_C_OFF();
532 DbpString("write successful");
533 return 0;
534 }*/
535
536 void LegicRfWriter(int bytes, int offset) {
537 int byte_index=0, addr_sz=0;
538 uint8_t *BigBuf = BigBuf_get_addr();
539
540 LegicCommonInit();
541
542 DbpString("setting up legic card");
543 uint32_t tag_type = perform_setup_phase_rwd(SESSION_IV);
544 switch_off_tag_rwd();
545 switch(tag_type) {
546 case 0x0d:
547 if(offset+bytes > 22) {
548 Dbprintf("Error: can not write to 0x%03.3x on MIM22", offset+bytes);
549 return;
550 }
551 addr_sz = 5;
552 Dbprintf("MIM22 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset+bytes);
553 break;
554 case 0x1d:
555 if(offset+bytes > 0x100) {
556 Dbprintf("Error: can not write to 0x%03.3x on MIM256", offset+bytes);
557 return;
558 }
559 addr_sz = 8;
560 Dbprintf("MIM256 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset+bytes);
561 break;
562 case 0x3d:
563 if(offset+bytes > 0x400) {
564 Dbprintf("Error: can not write to 0x%03.3x on MIM1024", offset+bytes);
565 return;
566 }
567 addr_sz = 10;
568 Dbprintf("MIM1024 card found, writing 0x%03.3x - 0x%03.3x ...", offset, offset+bytes);
569 break;
570 default:
571 Dbprintf("No or unknown card found, aborting");
572 return;
573 }
574
575 #if 1
576 LED_B_ON();
577 perform_setup_phase_rwd(SESSION_IV);
578
579 while(byte_index < bytes) {
580 int r;
581
582 //check if the DCF should be changed
583 if ( ((byte_index+offset) == 0x05) && (bytes >= 0x02) ) {
584 //write DCF in reverse order (addr 0x06 before 0x05)
585 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz);
586
587 // write second byte on success...
588 if(r == 0) {
589 byte_index++;
590 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz);
591 }
592 }
593 else {
594 r = legic_write_byte(BigBuf[byte_index+offset], byte_index+offset, addr_sz);
595 }
596 if((r != 0) || BUTTON_PRESS()) {
597 Dbprintf("operation aborted @ 0x%03.3x", byte_index);
598 switch_off_tag_rwd();
599 LED_B_OFF();
600 LED_C_OFF();
601 return;
602 }
603
604 WDT_HIT();
605 byte_index++;
606 if(byte_index & 0x10) LED_C_ON(); else LED_C_OFF();
607 }
608 LED_B_OFF();
609 LED_C_OFF();
610 DbpString("write successful");
611 #else
612 for(byte_index = -2; byte_index < 200; byte_index++)
613 {
614 Dbprintf("+ Try RndValue %d...", byte_index);
615 if(_LegicRfWriter(bytes, offset, addr_sz, BigBuf, byte_index) == 0)
616 break;
617 }
618 #endif
619
620 }
621
622 void LegicRfRawWriter(int offset, int byte) {
623 int byte_index=0, addr_sz=0;
624
625 LegicCommonInit();
626
627 DbpString("setting up legic card");
628 uint32_t tag_type = perform_setup_phase_rwd(SESSION_IV);
629 switch_off_tag_rwd();
630 switch(tag_type) {
631 case 0x0d:
632 if(offset > 22) {
633 Dbprintf("Error: can not write to 0x%03.3x on MIM22", offset);
634 return;
635 }
636 addr_sz = 5;
637 Dbprintf("MIM22 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", offset, byte);
638 break;
639 case 0x1d:
640 if(offset > 0x100) {
641 Dbprintf("Error: can not write to 0x%03.3x on MIM256", offset);
642 return;
643 }
644 addr_sz = 8;
645 Dbprintf("MIM256 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", offset, byte);
646 break;
647 case 0x3d:
648 if(offset > 0x400) {
649 Dbprintf("Error: can not write to 0x%03.3x on MIM1024", offset);
650 return;
651 }
652 addr_sz = 10;
653 Dbprintf("MIM1024 card found, writing at addr 0x%03.3x - value 0x%03.3x ...", offset, byte);
654 break;
655 default:
656 Dbprintf("No or unknown card found, aborting");
657 return;
658 }
659 Dbprintf("integer value: %d offset: %d addr_sz: %d", byte, offset, addr_sz);
660 LED_B_ON();
661 perform_setup_phase_rwd(SESSION_IV);
662 //legic_prng_forward(2);
663
664 int r = legic_write_byte(byte, offset, addr_sz);
665
666 if((r != 0) || BUTTON_PRESS()) {
667 Dbprintf("operation aborted @ 0x%03.3x (%1d)", byte_index, r);
668 switch_off_tag_rwd();
669 LED_B_OFF();
670 LED_C_OFF();
671 return;
672 }
673
674 LED_B_OFF();
675 LED_C_OFF();
676 DbpString("write successful");
677 }
678
679 int timestamp;
680
681 /* Handle (whether to respond) a frame in tag mode */
682 static void frame_handle_tag(struct legic_frame const * const f)
683 {
684 uint8_t *BigBuf = BigBuf_get_addr();
685
686 /* First Part of Handshake (IV) */
687 if(f->bits == 7) {
688 if(f->data == SESSION_IV) {
689 LED_C_ON();
690 prng_timer->TC_CCR = AT91C_TC_SWTRG;
691 legic_prng_init(f->data);
692 frame_send_tag(0x3d, 6, 1); /* 0x3d^0x26 = 0x1b */
693 legic_state = STATE_IV;
694 legic_read_count = 0;
695 legic_prng_bc = 0;
696 legic_prng_iv = f->data;
697
698 /* TIMEOUT */
699 timer->TC_CCR = AT91C_TC_SWTRG;
700 while(timer->TC_CV > 1);
701 while(timer->TC_CV < 280);
702 return;
703 } else if((prng_timer->TC_CV % 50) > 40) {
704 legic_prng_init(f->data);
705 frame_send_tag(0x3d, 6, 1);
706 SpinDelay(20);
707 return;
708 }
709 }
710
711 /* 0x19==??? */
712 if(legic_state == STATE_IV) {
713 if((f->bits == 6) && (f->data == (0x19 ^ get_key_stream(1, 6)))) {
714 legic_state = STATE_CON;
715
716 /* TIMEOUT */
717 timer->TC_CCR = AT91C_TC_SWTRG;
718 while(timer->TC_CV > 1);
719 while(timer->TC_CV < 200);
720 return;
721 } else {
722 legic_state = STATE_DISCON;
723 LED_C_OFF();
724 Dbprintf("0x19 - Frame: %03.3x", f->data);
725 return;
726 }
727 }
728
729 /* Read */
730 if(f->bits == 11) {
731 if(legic_state == STATE_CON) {
732 int key = get_key_stream(-1, 11); //legic_phase_drift, 11);
733 int addr = f->data ^ key; addr = addr >> 1;
734 int data = BigBuf[addr];
735 int hash = LegicCRC(addr, data, 11) << 8;
736 BigBuf[OFFSET_LOG+legic_read_count] = (uint8_t)addr;
737 legic_read_count++;
738
739 //Dbprintf("Data:%03.3x, key:%03.3x, addr: %03.3x, read_c:%u", f->data, key, addr, read_c);
740 legic_prng_forward(legic_reqresp_drift);
741
742 frame_send_tag(hash | data, 12, 1);
743
744 /* SHORT TIMEOUT */
745 timer->TC_CCR = AT91C_TC_SWTRG;
746 while(timer->TC_CV > 1);
747 legic_prng_forward(legic_frame_drift);
748 while(timer->TC_CV < 180);
749 return;
750 }
751 }
752
753 /* Write */
754 if(f->bits == 23) {
755 int key = get_key_stream(-1, 23); //legic_frame_drift, 23);
756 int addr = f->data ^ key; addr = addr >> 1; addr = addr & 0x3ff;
757 int data = f->data ^ key; data = data >> 11; data = data & 0xff;
758
759 /* write command */
760 legic_state = STATE_DISCON;
761 LED_C_OFF();
762 Dbprintf("write - addr: %x, data: %x", addr, data);
763 return;
764 }
765
766 if(legic_state != STATE_DISCON) {
767 Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count);
768 int i;
769 Dbprintf("IV: %03.3x", legic_prng_iv);
770 for(i = 0; i<legic_read_count; i++) {
771 Dbprintf("Read Nb: %u, Addr: %u", i, BigBuf[OFFSET_LOG+i]);
772 }
773
774 for(i = -1; i<legic_read_count; i++) {
775 uint32_t t;
776 t = BigBuf[OFFSET_LOG+256+i*4];
777 t |= BigBuf[OFFSET_LOG+256+i*4+1] << 8;
778 t |= BigBuf[OFFSET_LOG+256+i*4+2] <<16;
779 t |= BigBuf[OFFSET_LOG+256+i*4+3] <<24;
780
781 Dbprintf("Cycles: %u, Frame Length: %u, Time: %u",
782 BigBuf[OFFSET_LOG+128+i],
783 BigBuf[OFFSET_LOG+384+i],
784 t);
785 }
786 }
787 legic_state = STATE_DISCON;
788 legic_read_count = 0;
789 SpinDelay(10);
790 LED_C_OFF();
791 return;
792 }
793
794 /* Read bit by bit untill full frame is received
795 * Call to process frame end answer
796 */
797 static void emit(int bit)
798 {
799 if(bit == -1) {
800 if(current_frame.bits <= 4) {
801 frame_clean(&current_frame);
802 } else {
803 frame_handle_tag(&current_frame);
804 frame_clean(&current_frame);
805 }
806 WDT_HIT();
807 } else if(bit == 0) {
808 frame_append_bit(&current_frame, 0);
809 } else if(bit == 1) {
810 frame_append_bit(&current_frame, 1);
811 }
812 }
813
814 void LegicRfSimulate(int phase, int frame, int reqresp)
815 {
816 /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
817 * modulation mode set to 212kHz subcarrier. We are getting the incoming raw
818 * envelope waveform on DIN and should send our response on DOUT.
819 *
820 * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
821 * measure the time between two rising edges on DIN, and no encoding on the
822 * subcarrier from card to reader, so we'll just shift out our verbatim data
823 * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
824 * seems to be 300us-ish.
825 */
826
827 if(phase < 0) {
828 int i;
829 for(i=0; i<=reqresp; i++) {
830 legic_prng_init(SESSION_IV);
831 Dbprintf("i=%u, key 0x%3.3x", i, get_key_stream(i, frame));
832 }
833 return;
834 }
835
836 legic_phase_drift = phase;
837 legic_frame_drift = frame;
838 legic_reqresp_drift = reqresp;
839
840 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
841 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
842 FpgaSetupSsc();
843 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
844
845 /* Bitbang the receiver */
846 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
847 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
848
849 setup_timer();
850 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
851
852 int old_level = 0;
853 int active = 0;
854 legic_state = STATE_DISCON;
855
856 LED_B_ON();
857 DbpString("Starting Legic emulator, press button to end");
858 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
859 int level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
860 int time = timer->TC_CV;
861
862 if(level != old_level) {
863 if(level == 1) {
864 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
865 if(FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
866 /* 1 bit */
867 emit(1);
868 active = 1;
869 LED_A_ON();
870 } else if(FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
871 /* 0 bit */
872 emit(0);
873 active = 1;
874 LED_A_ON();
875 } else if(active) {
876 /* invalid */
877 emit(-1);
878 active = 0;
879 LED_A_OFF();
880 }
881 }
882 }
883
884 if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) {
885 /* Frame end */
886 emit(-1);
887 active = 0;
888 LED_A_OFF();
889 }
890
891 if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) {
892 timer->TC_CCR = AT91C_TC_CLKDIS;
893 }
894
895 old_level = level;
896 WDT_HIT();
897 }
898 DbpString("Stopped");
899 LED_B_OFF();
900 LED_A_OFF();
901 LED_C_OFF();
902 }
903
904
905 //-----------------------------------------------------------------------------
906 //-----------------------------------------------------------------------------
907
908
909 //-----------------------------------------------------------------------------
910 // Code up a string of octets at layer 2 (including CRC, we don't generate
911 // that here) so that they can be transmitted to the reader. Doesn't transmit
912 // them yet, just leaves them ready to send in ToSend[].
913 //-----------------------------------------------------------------------------
914 // static void CodeLegicAsTag(const uint8_t *cmd, int len)
915 // {
916 // int i;
917
918 // ToSendReset();
919
920 // // Transmit a burst of ones, as the initial thing that lets the
921 // // reader get phase sync. This (TR1) must be > 80/fs, per spec,
922 // // but tag that I've tried (a Paypass) exceeds that by a fair bit,
923 // // so I will too.
924 // for(i = 0; i < 20; i++) {
925 // ToSendStuffBit(1);
926 // ToSendStuffBit(1);
927 // ToSendStuffBit(1);
928 // ToSendStuffBit(1);
929 // }
930
931 // // Send SOF.
932 // for(i = 0; i < 10; i++) {
933 // ToSendStuffBit(0);
934 // ToSendStuffBit(0);
935 // ToSendStuffBit(0);
936 // ToSendStuffBit(0);
937 // }
938 // for(i = 0; i < 2; i++) {
939 // ToSendStuffBit(1);
940 // ToSendStuffBit(1);
941 // ToSendStuffBit(1);
942 // ToSendStuffBit(1);
943 // }
944
945 // for(i = 0; i < len; i++) {
946 // int j;
947 // uint8_t b = cmd[i];
948
949 // // Start bit
950 // ToSendStuffBit(0);
951 // ToSendStuffBit(0);
952 // ToSendStuffBit(0);
953 // ToSendStuffBit(0);
954
955 // // Data bits
956 // for(j = 0; j < 8; j++) {
957 // if(b & 1) {
958 // ToSendStuffBit(1);
959 // ToSendStuffBit(1);
960 // ToSendStuffBit(1);
961 // ToSendStuffBit(1);
962 // } else {
963 // ToSendStuffBit(0);
964 // ToSendStuffBit(0);
965 // ToSendStuffBit(0);
966 // ToSendStuffBit(0);
967 // }
968 // b >>= 1;
969 // }
970
971 // // Stop bit
972 // ToSendStuffBit(1);
973 // ToSendStuffBit(1);
974 // ToSendStuffBit(1);
975 // ToSendStuffBit(1);
976 // }
977
978 // // Send EOF.
979 // for(i = 0; i < 10; i++) {
980 // ToSendStuffBit(0);
981 // ToSendStuffBit(0);
982 // ToSendStuffBit(0);
983 // ToSendStuffBit(0);
984 // }
985 // for(i = 0; i < 2; i++) {
986 // ToSendStuffBit(1);
987 // ToSendStuffBit(1);
988 // ToSendStuffBit(1);
989 // ToSendStuffBit(1);
990 // }
991
992 // // Convert from last byte pos to length
993 // ToSendMax++;
994 // }
995
996 //-----------------------------------------------------------------------------
997 // The software UART that receives commands from the reader, and its state
998 // variables.
999 //-----------------------------------------------------------------------------
1000 static struct {
1001 enum {
1002 STATE_UNSYNCD,
1003 STATE_GOT_FALLING_EDGE_OF_SOF,
1004 STATE_AWAITING_START_BIT,
1005 STATE_RECEIVING_DATA
1006 } state;
1007 uint16_t shiftReg;
1008 int bitCnt;
1009 int byteCnt;
1010 int byteCntMax;
1011 int posCnt;
1012 uint8_t *output;
1013 } Uart;
1014
1015 /* Receive & handle a bit coming from the reader.
1016 *
1017 * This function is called 4 times per bit (every 2 subcarrier cycles).
1018 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1019 *
1020 * LED handling:
1021 * LED A -> ON once we have received the SOF and are expecting the rest.
1022 * LED A -> OFF once we have received EOF or are in error state or unsynced
1023 *
1024 * Returns: true if we received a EOF
1025 * false if we are still waiting for some more
1026 */
1027 // static RAMFUNC int HandleLegicUartBit(uint8_t bit)
1028 // {
1029 // switch(Uart.state) {
1030 // case STATE_UNSYNCD:
1031 // if(!bit) {
1032 // // we went low, so this could be the beginning of an SOF
1033 // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
1034 // Uart.posCnt = 0;
1035 // Uart.bitCnt = 0;
1036 // }
1037 // break;
1038
1039 // case STATE_GOT_FALLING_EDGE_OF_SOF:
1040 // Uart.posCnt++;
1041 // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
1042 // if(bit) {
1043 // if(Uart.bitCnt > 9) {
1044 // // we've seen enough consecutive
1045 // // zeros that it's a valid SOF
1046 // Uart.posCnt = 0;
1047 // Uart.byteCnt = 0;
1048 // Uart.state = STATE_AWAITING_START_BIT;
1049 // LED_A_ON(); // Indicate we got a valid SOF
1050 // } else {
1051 // // didn't stay down long enough
1052 // // before going high, error
1053 // Uart.state = STATE_UNSYNCD;
1054 // }
1055 // } else {
1056 // // do nothing, keep waiting
1057 // }
1058 // Uart.bitCnt++;
1059 // }
1060 // if(Uart.posCnt >= 4) Uart.posCnt = 0;
1061 // if(Uart.bitCnt > 12) {
1062 // // Give up if we see too many zeros without
1063 // // a one, too.
1064 // LED_A_OFF();
1065 // Uart.state = STATE_UNSYNCD;
1066 // }
1067 // break;
1068
1069 // case STATE_AWAITING_START_BIT:
1070 // Uart.posCnt++;
1071 // if(bit) {
1072 // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
1073 // // stayed high for too long between
1074 // // characters, error
1075 // Uart.state = STATE_UNSYNCD;
1076 // }
1077 // } else {
1078 // // falling edge, this starts the data byte
1079 // Uart.posCnt = 0;
1080 // Uart.bitCnt = 0;
1081 // Uart.shiftReg = 0;
1082 // Uart.state = STATE_RECEIVING_DATA;
1083 // }
1084 // break;
1085
1086 // case STATE_RECEIVING_DATA:
1087 // Uart.posCnt++;
1088 // if(Uart.posCnt == 2) {
1089 // // time to sample a bit
1090 // Uart.shiftReg >>= 1;
1091 // if(bit) {
1092 // Uart.shiftReg |= 0x200;
1093 // }
1094 // Uart.bitCnt++;
1095 // }
1096 // if(Uart.posCnt >= 4) {
1097 // Uart.posCnt = 0;
1098 // }
1099 // if(Uart.bitCnt == 10) {
1100 // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
1101 // {
1102 // // this is a data byte, with correct
1103 // // start and stop bits
1104 // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
1105 // Uart.byteCnt++;
1106
1107 // if(Uart.byteCnt >= Uart.byteCntMax) {
1108 // // Buffer overflowed, give up
1109 // LED_A_OFF();
1110 // Uart.state = STATE_UNSYNCD;
1111 // } else {
1112 // // so get the next byte now
1113 // Uart.posCnt = 0;
1114 // Uart.state = STATE_AWAITING_START_BIT;
1115 // }
1116 // } else if (Uart.shiftReg == 0x000) {
1117 // // this is an EOF byte
1118 // LED_A_OFF(); // Finished receiving
1119 // Uart.state = STATE_UNSYNCD;
1120 // if (Uart.byteCnt != 0) {
1121 // return TRUE;
1122 // }
1123 // } else {
1124 // // this is an error
1125 // LED_A_OFF();
1126 // Uart.state = STATE_UNSYNCD;
1127 // }
1128 // }
1129 // break;
1130
1131 // default:
1132 // LED_A_OFF();
1133 // Uart.state = STATE_UNSYNCD;
1134 // break;
1135 // }
1136
1137 // return FALSE;
1138 // }
1139
1140
1141 static void UartReset()
1142 {
1143 Uart.byteCntMax = MAX_FRAME_SIZE;
1144 Uart.state = STATE_UNSYNCD;
1145 Uart.byteCnt = 0;
1146 Uart.bitCnt = 0;
1147 Uart.posCnt = 0;
1148 memset(Uart.output, 0x00, MAX_FRAME_SIZE);
1149 }
1150
1151 // static void UartInit(uint8_t *data)
1152 // {
1153 // Uart.output = data;
1154 // UartReset();
1155 // }
1156
1157 //=============================================================================
1158 // An LEGIC reader. We take layer two commands, code them
1159 // appropriately, and then send them to the tag. We then listen for the
1160 // tag's response, which we leave in the buffer to be demodulated on the
1161 // PC side.
1162 //=============================================================================
1163
1164 static struct {
1165 enum {
1166 DEMOD_UNSYNCD,
1167 DEMOD_PHASE_REF_TRAINING,
1168 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
1169 DEMOD_GOT_FALLING_EDGE_OF_SOF,
1170 DEMOD_AWAITING_START_BIT,
1171 DEMOD_RECEIVING_DATA
1172 } state;
1173 int bitCount;
1174 int posCount;
1175 int thisBit;
1176 uint16_t shiftReg;
1177 uint8_t *output;
1178 int len;
1179 int sumI;
1180 int sumQ;
1181 } Demod;
1182
1183 /*
1184 * Handles reception of a bit from the tag
1185 *
1186 * This function is called 2 times per bit (every 4 subcarrier cycles).
1187 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1188 *
1189 * LED handling:
1190 * LED C -> ON once we have received the SOF and are expecting the rest.
1191 * LED C -> OFF once we have received EOF or are unsynced
1192 *
1193 * Returns: true if we received a EOF
1194 * false if we are still waiting for some more
1195 *
1196 */
1197
1198 #ifndef SUBCARRIER_DETECT_THRESHOLD
1199 # define SUBCARRIER_DETECT_THRESHOLD 8
1200 #endif
1201
1202 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
1203 #ifndef CHECK_FOR_SUBCARRIER
1204 # define CHECK_FOR_SUBCARRIER() { v = MAX(ai, aq) + MIN(halfci, halfcq); }
1205 #endif
1206
1207 // The soft decision on the bit uses an estimate of just the
1208 // quadrant of the reference angle, not the exact angle.
1209 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
1210 #define MAKE_SOFT_DECISION() { \
1211 if(Demod.sumI > 0) \
1212 v = ci; \
1213 else \
1214 v = -ci; \
1215 \
1216 if(Demod.sumQ > 0) \
1217 v += cq; \
1218 else \
1219 v -= cq; \
1220 \
1221 }
1222
1223 static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq)
1224 {
1225 int v = 0;
1226 int ai = ABS(ci);
1227 int aq = ABS(cq);
1228 int halfci = (ai >> 1);
1229 int halfcq = (aq >> 1);
1230
1231 switch(Demod.state) {
1232 case DEMOD_UNSYNCD:
1233
1234 CHECK_FOR_SUBCARRIER()
1235
1236 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
1237 Demod.state = DEMOD_PHASE_REF_TRAINING;
1238 Demod.sumI = ci;
1239 Demod.sumQ = cq;
1240 Demod.posCount = 1;
1241 }
1242 break;
1243
1244 case DEMOD_PHASE_REF_TRAINING:
1245 if(Demod.posCount < 8) {
1246
1247 CHECK_FOR_SUBCARRIER()
1248
1249 if (v > SUBCARRIER_DETECT_THRESHOLD) {
1250 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
1251 // note: synchronization time > 80 1/fs
1252 Demod.sumI += ci;
1253 Demod.sumQ += cq;
1254 ++Demod.posCount;
1255 } else {
1256 // subcarrier lost
1257 Demod.state = DEMOD_UNSYNCD;
1258 }
1259 } else {
1260 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
1261 }
1262 break;
1263
1264 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
1265
1266 MAKE_SOFT_DECISION()
1267
1268 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
1269 // logic '0' detected
1270 if (v <= 0) {
1271
1272 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
1273
1274 // start of SOF sequence
1275 Demod.posCount = 0;
1276 } else {
1277 // maximum length of TR1 = 200 1/fs
1278 if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
1279 }
1280 ++Demod.posCount;
1281 break;
1282
1283 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
1284 ++Demod.posCount;
1285
1286 MAKE_SOFT_DECISION()
1287
1288 if(v > 0) {
1289 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
1290 if(Demod.posCount < 10*2) {
1291 Demod.state = DEMOD_UNSYNCD;
1292 } else {
1293 LED_C_ON(); // Got SOF
1294 Demod.state = DEMOD_AWAITING_START_BIT;
1295 Demod.posCount = 0;
1296 Demod.len = 0;
1297 }
1298 } else {
1299 // low phase of SOF too long (> 12 etu)
1300 if(Demod.posCount > 13*2) {
1301 Demod.state = DEMOD_UNSYNCD;
1302 LED_C_OFF();
1303 }
1304 }
1305 break;
1306
1307 case DEMOD_AWAITING_START_BIT:
1308 ++Demod.posCount;
1309
1310 MAKE_SOFT_DECISION()
1311
1312 if(v > 0) {
1313 // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
1314 if(Demod.posCount > 3*2) {
1315 Demod.state = DEMOD_UNSYNCD;
1316 LED_C_OFF();
1317 }
1318 } else {
1319 // start bit detected
1320 Demod.bitCount = 0;
1321 Demod.posCount = 1; // this was the first half
1322 Demod.thisBit = v;
1323 Demod.shiftReg = 0;
1324 Demod.state = DEMOD_RECEIVING_DATA;
1325 }
1326 break;
1327
1328 case DEMOD_RECEIVING_DATA:
1329
1330 MAKE_SOFT_DECISION()
1331
1332 if(Demod.posCount == 0) {
1333 // first half of bit
1334 Demod.thisBit = v;
1335 Demod.posCount = 1;
1336 } else {
1337 // second half of bit
1338 Demod.thisBit += v;
1339 Demod.shiftReg >>= 1;
1340 // logic '1'
1341 if(Demod.thisBit > 0)
1342 Demod.shiftReg |= 0x200;
1343
1344 ++Demod.bitCount;
1345
1346 if(Demod.bitCount == 10) {
1347
1348 uint16_t s = Demod.shiftReg;
1349
1350 if((s & 0x200) && !(s & 0x001)) {
1351 // stop bit == '1', start bit == '0'
1352 uint8_t b = (s >> 1);
1353 Demod.output[Demod.len] = b;
1354 ++Demod.len;
1355 Demod.state = DEMOD_AWAITING_START_BIT;
1356 } else {
1357 Demod.state = DEMOD_UNSYNCD;
1358 LED_C_OFF();
1359
1360 if(s == 0x000) {
1361 // This is EOF (start, stop and all data bits == '0'
1362 return TRUE;
1363 }
1364 }
1365 }
1366 Demod.posCount = 0;
1367 }
1368 break;
1369
1370 default:
1371 Demod.state = DEMOD_UNSYNCD;
1372 LED_C_OFF();
1373 break;
1374 }
1375 return FALSE;
1376 }
1377
1378 // Clear out the state of the "UART" that receives from the tag.
1379 static void DemodReset() {
1380 Demod.len = 0;
1381 Demod.state = DEMOD_UNSYNCD;
1382 Demod.posCount = 0;
1383 Demod.sumI = 0;
1384 Demod.sumQ = 0;
1385 Demod.bitCount = 0;
1386 Demod.thisBit = 0;
1387 Demod.shiftReg = 0;
1388 memset(Demod.output, 0x00, MAX_FRAME_SIZE);
1389 }
1390
1391 static void DemodInit(uint8_t *data) {
1392 Demod.output = data;
1393 DemodReset();
1394 }
1395
1396 /*
1397 * Demodulate the samples we received from the tag, also log to tracebuffer
1398 * quiet: set to 'TRUE' to disable debug output
1399 */
1400 #define LEGIC_DMA_BUFFER_SIZE 256
1401 static void GetSamplesForLegicDemod(int n, bool quiet)
1402 {
1403 int max = 0;
1404 bool gotFrame = FALSE;
1405 int lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1406 int ci, cq, samples = 0;
1407
1408 BigBuf_free();
1409
1410 // And put the FPGA in the appropriate mode
1411 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ);
1412
1413 // The response (tag -> reader) that we're receiving.
1414 // Set up the demodulator for tag -> reader responses.
1415 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1416
1417 // The DMA buffer, used to stream samples from the FPGA
1418 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE);
1419 int8_t *upTo = dmaBuf;
1420
1421 // Setup and start DMA.
1422 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){
1423 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1424 return;
1425 }
1426
1427 // Signal field is ON with the appropriate LED:
1428 LED_D_ON();
1429 for(;;) {
1430 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
1431 if(behindBy > max) max = behindBy;
1432
1433 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) {
1434 ci = upTo[0];
1435 cq = upTo[1];
1436 upTo += 2;
1437 if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) {
1438 upTo = dmaBuf;
1439 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
1440 AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE;
1441 }
1442 lastRxCounter -= 2;
1443 if(lastRxCounter <= 0)
1444 lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1445
1446 samples += 2;
1447
1448 gotFrame = HandleLegicSamplesDemod(ci , cq );
1449 if ( gotFrame )
1450 break;
1451 }
1452
1453 if(samples > n || gotFrame)
1454 break;
1455 }
1456
1457 FpgaDisableSscDma();
1458
1459 if (!quiet && Demod.len == 0) {
1460 Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
1461 max,
1462 samples,
1463 gotFrame,
1464 Demod.len,
1465 Demod.sumI,
1466 Demod.sumQ
1467 );
1468 }
1469
1470 //Tracing
1471 if (Demod.len > 0) {
1472 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1473 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
1474 }
1475 }
1476 //-----------------------------------------------------------------------------
1477 // Transmit the command (to the tag) that was placed in ToSend[].
1478 //-----------------------------------------------------------------------------
1479 static void TransmitForLegic(void)
1480 {
1481 int c;
1482
1483 FpgaSetupSsc();
1484
1485 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
1486 AT91C_BASE_SSC->SSC_THR = 0xff;
1487
1488 // Signal field is ON with the appropriate Red LED
1489 LED_D_ON();
1490
1491 // Signal we are transmitting with the Green LED
1492 LED_B_ON();
1493 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1494
1495 for(c = 0; c < 10;) {
1496 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1497 AT91C_BASE_SSC->SSC_THR = 0xff;
1498 c++;
1499 }
1500 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1501 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1502 (void)r;
1503 }
1504 WDT_HIT();
1505 }
1506
1507 c = 0;
1508 for(;;) {
1509 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1510 AT91C_BASE_SSC->SSC_THR = ToSend[c];
1511 legic_prng_forward(1); // forward the lfsr
1512 c++;
1513 if(c >= ToSendMax) {
1514 break;
1515 }
1516 }
1517 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1518 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1519 (void)r;
1520 }
1521 WDT_HIT();
1522 }
1523 LED_B_OFF();
1524 }
1525
1526
1527 //-----------------------------------------------------------------------------
1528 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1529 // so that it is ready to transmit to the tag using TransmitForLegic().
1530 //-----------------------------------------------------------------------------
1531 static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1532 {
1533 int i, j;
1534 uint8_t b;
1535
1536 ToSendReset();
1537
1538 // Send SOF
1539 for(i = 0; i < 7; i++)
1540 ToSendStuffBit(1);
1541
1542
1543 for(i = 0; i < cmdlen; i++) {
1544 // Start bit
1545 ToSendStuffBit(0);
1546
1547 // Data bits
1548 b = cmd[i];
1549 for(j = 0; j < bits; j++) {
1550 if(b & 1) {
1551 ToSendStuffBit(1);
1552 } else {
1553 ToSendStuffBit(0);
1554 }
1555 b >>= 1;
1556 }
1557 }
1558
1559 // Convert from last character reference to length
1560 ++ToSendMax;
1561 }
1562
1563 /**
1564 Convenience function to encode, transmit and trace Legic comms
1565 **/
1566 static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1567 {
1568 CodeLegicBitsAsReader(cmd, cmdlen, bits);
1569 TransmitForLegic();
1570 if (tracing) {
1571 uint8_t parity[1] = {0x00};
1572 LogTrace(cmd, cmdlen, 0, 0, parity, TRUE);
1573 }
1574 }
1575
1576 int ice_legic_select_card()
1577 {
1578 //int cmd_size=0, card_size=0;
1579 uint8_t wakeup[] = { 0x7F };
1580 uint8_t getid[] = {0x19};
1581
1582 legic_prng_init(SESSION_IV);
1583
1584 // first, wake up the tag, 7bits
1585 CodeAndTransmitLegicAsReader(wakeup, sizeof(wakeup), 7);
1586
1587 GetSamplesForLegicDemod(1000, TRUE);
1588
1589 // frame_clean(&current_frame);
1590 //frame_receive_rwd(&current_frame, 6, 1);
1591
1592 legic_prng_forward(1); /* we wait anyways */
1593
1594 //while(timer->TC_CV < 387) ; /* ~ 258us */
1595 //frame_send_rwd(0x19, 6);
1596 CodeAndTransmitLegicAsReader(getid, sizeof(getid), 8);
1597 GetSamplesForLegicDemod(1000, TRUE);
1598
1599 //if (Demod.len < 14) return 2;
1600 Dbprintf("CARD TYPE: %02x LEN: %d", Demod.output[0], Demod.len);
1601
1602 switch(Demod.output[0]) {
1603 case 0x1d:
1604 DbpString("MIM 256 card found");
1605 // cmd_size = 9;
1606 // card_size = 256;
1607 break;
1608 case 0x3d:
1609 DbpString("MIM 1024 card found");
1610 // cmd_size = 11;
1611 // card_size = 1024;
1612 break;
1613 default:
1614 return -1;
1615 }
1616
1617 // if(bytes == -1)
1618 // bytes = card_size;
1619
1620 // if(bytes + offset >= card_size)
1621 // bytes = card_size - offset;
1622
1623 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1624 set_tracing(FALSE);
1625 return 1;
1626 }
1627
1628 // Set up LEGIC communication
1629 void ice_legic_setup() {
1630
1631 // standard things.
1632 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1633 BigBuf_free(); BigBuf_Clear_ext(false);
1634 clear_trace();
1635 set_tracing(TRUE);
1636 DemodReset();
1637 UartReset();
1638
1639 // Set up the synchronous serial port
1640 FpgaSetupSsc();
1641
1642 // connect Demodulated Signal to ADC:
1643 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1644
1645 // Signal field is on with the appropriate LED
1646 LED_D_ON();
1647 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1648 SpinDelay(200);
1649 // Start the timer
1650 //StartCountSspClk();
1651
1652 // initalize CRC
1653 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
1654
1655 // initalize prng
1656 legic_prng_init(0);
1657 }
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