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CHG: experimenting with 'lf sim' It does send a signal now but...
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "protocols.h"
20 #include "usb_cdc.h" // for usb_poll_validate_length
21
22 #ifndef SHORT_COIL
23 # define SHORT_COIL() LOW(GPIO_SSC_DOUT)
24 #endif
25 #ifndef OPEN_COIL
26 # define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
27 #endif
28
29 /**
30 * Function to do a modulation and then get samples.
31 * @param delay_off
32 * @param periods 0xFFFF0000 is period_0, 0x0000FFFF is period_1
33 * @param useHighFreg
34 * @param command
35 */
36 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint32_t useHighFreq, uint8_t *command)
37 {
38 /* Make sure the tag is reset */
39 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
40 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
41 SpinDelay(200);
42
43 uint16_t period_0 = periods >> 16;
44 uint16_t period_1 = periods & 0xFFFF;
45
46 // 95 == 125 KHz 88 == 124.8 KHz
47 int divisor_used = (useHighFreq) ? 88 : 95;
48 sample_config sc = { 0,0,1, divisor_used, 0};
49 setSamplingConfig(&sc);
50
51 //clear read buffer
52 BigBuf_Clear_keep_EM();
53
54 LFSetupFPGAForADC(sc.divisor, 1);
55
56 // And a little more time for the tag to fully power up
57 SpinDelay(50);
58
59 // now modulate the reader field
60 while(*command != '\0' && *command != ' ') {
61 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
62 LED_D_OFF();
63 WaitUS(delay_off);
64 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
65
66 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
67 LED_D_ON();
68 if(*(command++) == '0')
69 WaitUS(period_0);
70 else
71 WaitUS(period_1);
72 }
73 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
74 LED_D_OFF();
75 WaitUS(delay_off);
76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
77 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
78
79 // now do the read
80 DoAcquisition_config(false);
81 }
82
83 /* blank r/w tag data stream
84 ...0000000000000000 01111111
85 1010101010101010101010101010101010101010101010101010101010101010
86 0011010010100001
87 01111111
88 101010101010101[0]000...
89
90 [5555fe852c5555555555555555fe0000]
91 */
92 void ReadTItag(void)
93 {
94 StartTicks();
95 // some hardcoded initial params
96 // when we read a TI tag we sample the zerocross line at 2Mhz
97 // TI tags modulate a 1 as 16 cycles of 123.2Khz
98 // TI tags modulate a 0 as 16 cycles of 134.2Khz
99 #define FSAMPLE 2000000
100 #define FREQLO 123200
101 #define FREQHI 134200
102
103 signed char *dest = (signed char *)BigBuf_get_addr();
104 uint16_t n = BigBuf_max_traceLen();
105 // 128 bit shift register [shift3:shift2:shift1:shift0]
106 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
107
108 int i, cycles=0, samples=0;
109 // how many sample points fit in 16 cycles of each frequency
110 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
111 // when to tell if we're close enough to one freq or another
112 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
113
114 // TI tags charge at 134.2Khz
115 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
116 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
117
118 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
119 // connects to SSP_DIN and the SSP_DOUT logic level controls
120 // whether we're modulating the antenna (high)
121 // or listening to the antenna (low)
122 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
123
124 // get TI tag data into the buffer
125 AcquireTiType();
126
127 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
128
129 for (i=0; i<n-1; i++) {
130 // count cycles by looking for lo to hi zero crossings
131 if ( (dest[i]<0) && (dest[i+1]>0) ) {
132 cycles++;
133 // after 16 cycles, measure the frequency
134 if (cycles>15) {
135 cycles=0;
136 samples=i-samples; // number of samples in these 16 cycles
137
138 // TI bits are coming to us lsb first so shift them
139 // right through our 128 bit right shift register
140 shift0 = (shift0>>1) | (shift1 << 31);
141 shift1 = (shift1>>1) | (shift2 << 31);
142 shift2 = (shift2>>1) | (shift3 << 31);
143 shift3 >>= 1;
144
145 // check if the cycles fall close to the number
146 // expected for either the low or high frequency
147 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
148 // low frequency represents a 1
149 shift3 |= (1<<31);
150 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
151 // high frequency represents a 0
152 } else {
153 // probably detected a gay waveform or noise
154 // use this as gaydar or discard shift register and start again
155 shift3 = shift2 = shift1 = shift0 = 0;
156 }
157 samples = i;
158
159 // for each bit we receive, test if we've detected a valid tag
160
161 // if we see 17 zeroes followed by 6 ones, we might have a tag
162 // remember the bits are backwards
163 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
164 // if start and end bytes match, we have a tag so break out of the loop
165 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
166 cycles = 0xF0B; //use this as a flag (ugly but whatever)
167 break;
168 }
169 }
170 }
171 }
172 }
173
174 // if flag is set we have a tag
175 if (cycles!=0xF0B) {
176 DbpString("Info: No valid tag detected.");
177 } else {
178 // put 64 bit data into shift1 and shift0
179 shift0 = (shift0>>24) | (shift1 << 8);
180 shift1 = (shift1>>24) | (shift2 << 8);
181
182 // align 16 bit crc into lower half of shift2
183 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
184
185 // if r/w tag, check ident match
186 if (shift3 & (1<<15) ) {
187 DbpString("Info: TI tag is rewriteable");
188 // only 15 bits compare, last bit of ident is not valid
189 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
190 DbpString("Error: Ident mismatch!");
191 } else {
192 DbpString("Info: TI tag ident is valid");
193 }
194 } else {
195 DbpString("Info: TI tag is readonly");
196 }
197
198 // WARNING the order of the bytes in which we calc crc below needs checking
199 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
200 // bytes in reverse or something
201 // calculate CRC
202 uint32_t crc=0;
203
204 crc = update_crc16(crc, (shift0)&0xff);
205 crc = update_crc16(crc, (shift0>>8)&0xff);
206 crc = update_crc16(crc, (shift0>>16)&0xff);
207 crc = update_crc16(crc, (shift0>>24)&0xff);
208 crc = update_crc16(crc, (shift1)&0xff);
209 crc = update_crc16(crc, (shift1>>8)&0xff);
210 crc = update_crc16(crc, (shift1>>16)&0xff);
211 crc = update_crc16(crc, (shift1>>24)&0xff);
212
213 Dbprintf("Info: Tag data: %x%08x, crc=%x", (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
214 if (crc != (shift2&0xffff)) {
215 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
216 } else {
217 DbpString("Info: CRC is good");
218 }
219 }
220 StopTicks();
221 }
222
223 void WriteTIbyte(uint8_t b)
224 {
225 int i = 0;
226
227 // modulate 8 bits out to the antenna
228 for (i=0; i<8; i++)
229 {
230 if ( b & ( 1 << i ) ) {
231 // stop modulating antenna 1ms
232 LOW(GPIO_SSC_DOUT);
233 WaitUS(1000);
234 // modulate antenna 1ms
235 HIGH(GPIO_SSC_DOUT);
236 WaitUS(1000);
237 } else {
238 // stop modulating antenna 1ms
239 LOW(GPIO_SSC_DOUT);
240 WaitUS(300);
241 // modulate antenna 1m
242 HIGH(GPIO_SSC_DOUT);
243 WaitUS(1700);
244 }
245 }
246 }
247
248 void AcquireTiType(void)
249 {
250 int i, j, n;
251 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
252 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
253 #define TIBUFLEN 1250
254
255 // clear buffer
256 uint32_t *buf = (uint32_t *)BigBuf_get_addr();
257
258 //clear buffer now so it does not interfere with timing later
259 BigBuf_Clear_ext(false);
260
261 // Set up the synchronous serial port
262 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
263 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
264
265 // steal this pin from the SSP and use it to control the modulation
266 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
267 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
268
269 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
270 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
271
272 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
273 // 48/2 = 24 MHz clock must be divided by 12
274 AT91C_BASE_SSC->SSC_CMR = 12;
275
276 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
277 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
278 AT91C_BASE_SSC->SSC_TCMR = 0;
279 AT91C_BASE_SSC->SSC_TFMR = 0;
280 // iceman, FpgaSetupSsc() ?? the code above? can it be replaced?
281 LED_D_ON();
282
283 // modulate antenna
284 HIGH(GPIO_SSC_DOUT);
285
286 // Charge TI tag for 50ms.
287 WaitMS(50);
288
289 // stop modulating antenna and listen
290 LOW(GPIO_SSC_DOUT);
291
292 LED_D_OFF();
293
294 i = 0;
295 for(;;) {
296 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
297 buf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
298 i++; if(i >= TIBUFLEN) break;
299 }
300 WDT_HIT();
301 }
302
303 // return stolen pin to SSP
304 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
305 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
306
307 char *dest = (char *)BigBuf_get_addr();
308 n = TIBUFLEN * 32;
309
310 // unpack buffer
311 for (i = TIBUFLEN-1; i >= 0; i--) {
312 for (j = 0; j < 32; j++) {
313 if(buf[i] & (1 << j)) {
314 dest[--n] = 1;
315 } else {
316 dest[--n] = -1;
317 }
318 }
319 }
320 }
321
322 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
323 // if crc provided, it will be written with the data verbatim (even if bogus)
324 // if not provided a valid crc will be computed from the data and written.
325 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
326 {
327 StartTicks();
328 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
329 if(crc == 0) {
330 crc = update_crc16(crc, (idlo)&0xff);
331 crc = update_crc16(crc, (idlo>>8)&0xff);
332 crc = update_crc16(crc, (idlo>>16)&0xff);
333 crc = update_crc16(crc, (idlo>>24)&0xff);
334 crc = update_crc16(crc, (idhi)&0xff);
335 crc = update_crc16(crc, (idhi>>8)&0xff);
336 crc = update_crc16(crc, (idhi>>16)&0xff);
337 crc = update_crc16(crc, (idhi>>24)&0xff);
338 }
339 Dbprintf("Writing to tag: %x%08x, crc=%x", (unsigned int) idhi, (unsigned int) idlo, crc);
340
341 // TI tags charge at 134.2Khz
342 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
343 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
344 // connects to SSP_DIN and the SSP_DOUT logic level controls
345 // whether we're modulating the antenna (high)
346 // or listening to the antenna (low)
347 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
348 LED_A_ON();
349
350 // steal this pin from the SSP and use it to control the modulation
351 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
352 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
353
354 // writing algorithm:
355 // a high bit consists of a field off for 1ms and field on for 1ms
356 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
357 // initiate a charge time of 50ms (field on) then immediately start writing bits
358 // start by writing 0xBB (keyword) and 0xEB (password)
359 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
360 // finally end with 0x0300 (write frame)
361 // all data is sent lsb first
362 // finish with 15ms programming time
363
364 // modulate antenna
365 HIGH(GPIO_SSC_DOUT);
366 WaitMS(50); // charge time
367
368 WriteTIbyte(0xbb); // keyword
369 WriteTIbyte(0xeb); // password
370 WriteTIbyte( (idlo )&0xff );
371 WriteTIbyte( (idlo>>8 )&0xff );
372 WriteTIbyte( (idlo>>16)&0xff );
373 WriteTIbyte( (idlo>>24)&0xff );
374 WriteTIbyte( (idhi )&0xff );
375 WriteTIbyte( (idhi>>8 )&0xff );
376 WriteTIbyte( (idhi>>16)&0xff );
377 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
378 WriteTIbyte( (crc )&0xff ); // crc lo
379 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
380 WriteTIbyte(0x00); // write frame lo
381 WriteTIbyte(0x03); // write frame hi
382 HIGH(GPIO_SSC_DOUT);
383 WaitMS(50); // programming time
384
385 LED_A_OFF();
386
387 // get TI tag data into the buffer
388 AcquireTiType();
389
390 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
391 DbpString("Now use `lf ti read` to check");
392 StopTicks();
393 }
394
395 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
396 {
397 int i = 0;
398 uint8_t *buf = BigBuf_get_addr();
399
400 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
401 //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
402
403 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
404 //AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
405 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
406 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
407
408 StartTicks();
409
410 for(;;) {
411 WDT_HIT();
412
413 if (ledcontrol) LED_D_ON();
414
415 // wait until SSC_CLK goes HIGH
416 // used as a simple detection of a reader field?
417 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
418 WDT_HIT();
419 if ( usb_poll_validate_length() || BUTTON_PRESS() )
420 goto OUT;
421 }
422
423 if(buf[i])
424 OPEN_COIL();
425 else
426 SHORT_COIL();
427
428 if (ledcontrol) LED_D_OFF();
429
430 //wait until SSC_CLK goes LOW
431 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
432 WDT_HIT();
433 if ( usb_poll_validate_length() || BUTTON_PRESS() )
434 goto OUT;
435 }
436
437 i++;
438 if(i == period) {
439 i = 0;
440 if (gap) {
441 WDT_HIT();
442 SHORT_COIL();
443 WaitUS(gap);
444 }
445 }
446 }
447 OUT:
448 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
449 StopTicks();
450 LED_D_OFF();
451 DbpString("Simulation stopped");
452 return;
453 }
454
455 #define DEBUG_FRAME_CONTENTS 1
456 void SimulateTagLowFrequencyBidir(int divisor, int t0)
457 {
458 }
459
460 // compose fc/8 fc/10 waveform (FSK2)
461 static void fc(int c, int *n)
462 {
463 uint8_t *dest = BigBuf_get_addr();
464 int idx;
465
466 // for when we want an fc8 pattern every 4 logical bits
467 if(c==0) {
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=1;
471 dest[((*n)++)]=1;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 dest[((*n)++)]=0;
475 dest[((*n)++)]=0;
476 }
477
478 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
479 if(c==8) {
480 for (idx=0; idx<6; idx++) {
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 }
490 }
491
492 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
493 if(c==10) {
494 for (idx=0; idx<5; idx++) {
495 dest[((*n)++)]=1;
496 dest[((*n)++)]=1;
497 dest[((*n)++)]=1;
498 dest[((*n)++)]=1;
499 dest[((*n)++)]=1;
500 dest[((*n)++)]=0;
501 dest[((*n)++)]=0;
502 dest[((*n)++)]=0;
503 dest[((*n)++)]=0;
504 dest[((*n)++)]=0;
505 }
506 }
507 }
508 // compose fc/X fc/Y waveform (FSKx)
509 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
510 {
511 uint8_t *dest = BigBuf_get_addr();
512 uint8_t halfFC = fc/2;
513 uint8_t wavesPerClock = clock/fc;
514 uint8_t mod = clock % fc; //modifier
515 uint8_t modAdj = fc/mod; //how often to apply modifier
516 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
517 // loop through clock - step field clock
518 for (uint8_t idx=0; idx < wavesPerClock; idx++){
519 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
520 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
521 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
522 *n += fc;
523 }
524 if (mod>0) (*modCnt)++;
525 if ((mod>0) && modAdjOk){ //fsk2
526 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
527 memset(dest+(*n), 0, fc-halfFC);
528 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
529 *n += fc;
530 }
531 }
532 if (mod>0 && !modAdjOk){ //fsk1
533 memset(dest+(*n), 0, mod-(mod/2));
534 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
535 *n += mod;
536 }
537 }
538
539 // prepare a waveform pattern in the buffer based on the ID given then
540 // simulate a HID tag until the button is pressed
541 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
542 {
543 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
544 set_tracing(FALSE);
545
546 int n = 0, i = 0;
547 /*
548 HID tag bitstream format
549 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
550 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
551 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
552 A fc8 is inserted before every 4 bits
553 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
554 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
555 */
556
557 if (hi > 0xFFF) {
558 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
559 return;
560 }
561 fc(0,&n);
562 // special start of frame marker containing invalid bit sequences
563 fc(8, &n); fc(8, &n); // invalid
564 fc(8, &n); fc(10, &n); // logical 0
565 fc(10, &n); fc(10, &n); // invalid
566 fc(8, &n); fc(10, &n); // logical 0
567
568 WDT_HIT();
569 // manchester encode bits 43 to 32
570 for (i=11; i>=0; i--) {
571 if ((i%4)==3) fc(0,&n);
572 if ((hi>>i)&1) {
573 fc(10, &n); fc(8, &n); // low-high transition
574 } else {
575 fc(8, &n); fc(10, &n); // high-low transition
576 }
577 }
578
579 WDT_HIT();
580 // manchester encode bits 31 to 0
581 for (i=31; i>=0; i--) {
582 if ((i%4)==3) fc(0,&n);
583 if ((lo>>i)&1) {
584 fc(10, &n); fc(8, &n); // low-high transition
585 } else {
586 fc(8, &n); fc(10, &n); // high-low transition
587 }
588 }
589 WDT_HIT();
590
591 if (ledcontrol) LED_A_ON();
592 SimulateTagLowFrequency(n, 0, ledcontrol);
593 if (ledcontrol) LED_A_OFF();
594 }
595
596 // prepare a waveform pattern in the buffer based on the ID given then
597 // simulate a FSK tag until the button is pressed
598 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
599 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
600 {
601 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
602
603 // free eventually allocated BigBuf memory
604 BigBuf_free(); BigBuf_Clear_ext(false);
605 clear_trace();
606 set_tracing(FALSE);
607
608 int ledcontrol = 1, n = 0, i = 0;
609 uint8_t fcHigh = arg1 >> 8;
610 uint8_t fcLow = arg1 & 0xFF;
611 uint16_t modCnt = 0;
612 uint8_t clk = arg2 & 0xFF;
613 uint8_t invert = (arg2 >> 8) & 1;
614
615 for (i=0; i<size; i++){
616
617 if (BitStream[i] == invert)
618 fcAll(fcLow, &n, clk, &modCnt);
619 else
620 fcAll(fcHigh, &n, clk, &modCnt);
621 }
622 WDT_HIT();
623
624 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d", fcHigh, fcLow, clk, invert, n);
625
626 if (ledcontrol) LED_A_ON();
627 SimulateTagLowFrequency(n, 0, ledcontrol);
628 if (ledcontrol) LED_A_OFF();
629 }
630
631 // compose ask waveform for one bit(ASK)
632 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
633 {
634 uint8_t *dest = BigBuf_get_addr();
635 uint8_t halfClk = clock/2;
636 // c = current bit 1 or 0
637 if (manchester==1){
638 memset(dest+(*n), c, halfClk);
639 memset(dest+(*n) + halfClk, c^1, halfClk);
640 } else {
641 memset(dest+(*n), c, clock);
642 }
643 *n += clock;
644 }
645
646 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
647 {
648 uint8_t *dest = BigBuf_get_addr();
649 uint8_t halfClk = clock/2;
650 if (c){
651 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
652 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
653 } else {
654 memset(dest+(*n), c ^ *phase, clock);
655 *phase ^= 1;
656 }
657 *n += clock;
658 }
659
660 static void stAskSimBit(int *n, uint8_t clock) {
661 uint8_t *dest = BigBuf_get_addr();
662 uint8_t halfClk = clock/2;
663 //ST = .5 high .5 low 1.5 high .5 low 1 high
664 memset(dest+(*n), 1, halfClk);
665 memset(dest+(*n) + halfClk, 0, halfClk);
666 memset(dest+(*n) + clock, 1, clock + halfClk);
667 memset(dest+(*n) + clock*2 + halfClk, 0, halfClk);
668 memset(dest+(*n) + clock*3, 1, clock);
669 *n += clock*4;
670 }
671
672 // args clock, ask/man or askraw, invert, transmission separator
673 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
674 {
675 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
676 set_tracing(FALSE);
677
678 int ledcontrol = 1, n = 0, i = 0;
679 uint8_t clk = (arg1 >> 8) & 0xFF;
680 uint8_t encoding = arg1 & 0xFF;
681 uint8_t separator = arg2 & 1;
682 uint8_t invert = (arg2 >> 8) & 1;
683
684 if (encoding == 2){ //biphase
685 uint8_t phase = 0;
686 for (i=0; i<size; i++){
687 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
688 }
689 if (phase == 1) { //run a second set inverted to keep phase in check
690 for (i=0; i<size; i++){
691 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
692 }
693 }
694 } else { // ask/manchester || ask/raw
695 for (i=0; i<size; i++){
696 askSimBit(BitStream[i]^invert, &n, clk, encoding);
697 }
698 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
699 for (i=0; i<size; i++){
700 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
701 }
702 }
703 }
704 if (separator==1 && encoding == 1)
705 stAskSimBit(&n, clk);
706 else if (separator==1)
707 Dbprintf("sorry but separator option not yet available");
708
709 WDT_HIT();
710
711 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
712
713 if (ledcontrol) LED_A_ON();
714 SimulateTagLowFrequency(n, 0, ledcontrol);
715 if (ledcontrol) LED_A_OFF();
716 }
717
718 //carrier can be 2,4 or 8
719 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
720 {
721 uint8_t *dest = BigBuf_get_addr();
722 uint8_t halfWave = waveLen/2;
723 //uint8_t idx;
724 int i = 0;
725 if (phaseChg){
726 // write phase change
727 memset(dest+(*n), *curPhase^1, halfWave);
728 memset(dest+(*n) + halfWave, *curPhase, halfWave);
729 *n += waveLen;
730 *curPhase ^= 1;
731 i += waveLen;
732 }
733 //write each normal clock wave for the clock duration
734 for (; i < clk; i+=waveLen){
735 memset(dest+(*n), *curPhase, halfWave);
736 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
737 *n += waveLen;
738 }
739 }
740
741 // args clock, carrier, invert,
742 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
743 {
744 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
745 set_tracing(FALSE);
746
747 int ledcontrol = 1, n = 0, i = 0;
748 uint8_t clk = arg1 >> 8;
749 uint8_t carrier = arg1 & 0xFF;
750 uint8_t invert = arg2 & 0xFF;
751 uint8_t curPhase = 0;
752 for (i=0; i<size; i++){
753 if (BitStream[i] == curPhase){
754 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
755 } else {
756 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
757 }
758 }
759
760 WDT_HIT();
761
762 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
763
764 if (ledcontrol) LED_A_ON();
765 SimulateTagLowFrequency(n, 0, ledcontrol);
766 if (ledcontrol) LED_A_OFF();
767 }
768
769 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
770 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
771 {
772 uint8_t *dest = BigBuf_get_addr();
773 size_t size = 0;
774 uint32_t hi2=0, hi=0, lo=0;
775 int idx=0;
776 // Configure to go in 125Khz listen mode
777 LFSetupFPGAForADC(95, true);
778
779 //clear read buffer
780 BigBuf_Clear_keep_EM();
781
782 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
783
784 WDT_HIT();
785 if (ledcontrol) LED_A_ON();
786
787 DoAcquisition_default(-1,true);
788 // FSK demodulator
789 size = 50*128*2; //big enough to catch 2 sequences of largest format
790 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
791
792 if (idx>0 && lo>0 && (size==96 || size==192)){
793 // go over previously decoded manchester data and decode into usable tag ID
794 if (hi2 != 0){ //extra large HID tags 88/192 bits
795 Dbprintf("TAG ID: %x%08x%08x (%d)",
796 (unsigned int) hi2,
797 (unsigned int) hi,
798 (unsigned int) lo,
799 (unsigned int) (lo>>1) & 0xFFFF
800 );
801 } else { //standard HID tags 44/96 bits
802 uint8_t bitlen = 0;
803 uint32_t fc = 0;
804 uint32_t cardnum = 0;
805
806 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
807 uint32_t lo2=0;
808 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
809 uint8_t idx3 = 1;
810 while(lo2 > 1){ //find last bit set to 1 (format len bit)
811 lo2=lo2 >> 1;
812 idx3++;
813 }
814 bitlen = idx3+19;
815 fc =0;
816 cardnum=0;
817 if(bitlen == 26){
818 cardnum = (lo>>1)&0xFFFF;
819 fc = (lo>>17)&0xFF;
820 }
821 if(bitlen == 37){
822 cardnum = (lo>>1)&0x7FFFF;
823 fc = ((hi&0xF)<<12)|(lo>>20);
824 }
825 if(bitlen == 34){
826 cardnum = (lo>>1)&0xFFFF;
827 fc= ((hi&1)<<15)|(lo>>17);
828 }
829 if(bitlen == 35){
830 cardnum = (lo>>1)&0xFFFFF;
831 fc = ((hi&1)<<11)|(lo>>21);
832 }
833 }
834 else { //if bit 38 is not set then 37 bit format is used
835 bitlen= 37;
836 fc =0;
837 cardnum=0;
838 if(bitlen==37){
839 cardnum = (lo>>1)&0x7FFFF;
840 fc = ((hi&0xF)<<12)|(lo>>20);
841 }
842 }
843 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
844 (unsigned int) hi,
845 (unsigned int) lo,
846 (unsigned int) (lo>>1) & 0xFFFF,
847 (unsigned int) bitlen,
848 (unsigned int) fc,
849 (unsigned int) cardnum);
850 }
851 if (findone){
852 if (ledcontrol) LED_A_OFF();
853 *high = hi;
854 *low = lo;
855 return;
856 }
857 // reset
858 }
859 hi2 = hi = lo = idx = 0;
860 WDT_HIT();
861 }
862 DbpString("Stopped");
863 if (ledcontrol) LED_A_OFF();
864 }
865
866 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
867 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
868 {
869 uint8_t *dest = BigBuf_get_addr();
870 size_t size;
871 int idx=0;
872 //clear read buffer
873 BigBuf_Clear_keep_EM();
874 // Configure to go in 125Khz listen mode
875 LFSetupFPGAForADC(95, true);
876
877 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
878
879 WDT_HIT();
880 if (ledcontrol) LED_A_ON();
881
882 DoAcquisition_default(-1,true);
883 // FSK demodulator
884 size = 50*128*2; //big enough to catch 2 sequences of largest format
885 idx = AWIDdemodFSK(dest, &size);
886
887 if (idx<=0 || size!=96) continue;
888 // Index map
889 // 0 10 20 30 40 50 60
890 // | | | | | | |
891 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
892 // -----------------------------------------------------------------------------
893 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
894 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
895 // |---26 bit---| |-----117----||-------------142-------------|
896 // b = format bit len, o = odd parity of last 3 bits
897 // f = facility code, c = card number
898 // w = wiegand parity
899 // (26 bit format shown)
900
901 //get raw ID before removing parities
902 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
903 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
904 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
905
906 size = removeParity(dest, idx+8, 4, 1, 88);
907 if (size != 66) continue;
908
909 // Index map
910 // 0 10 20 30 40 50 60
911 // | | | | | | |
912 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
913 // -----------------------------------------------------------------------------
914 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
915 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
916 // |26 bit| |-117--| |-----142------|
917 //
918 // 00110010 0 0000011111010000000000000001000100101000100001111 0 00000000
919 // bbbbbbbb w ffffffffffffffffccccccccccccccccccccccccccccccccc w xxxxxxxx
920 // |50 bit| |----4000------||-----------2248975-------------|
921 //
922 // b = format bit len, o = odd parity of last 3 bits
923 // f = facility code, c = card number
924 // w = wiegand parity
925
926 uint32_t fc = 0;
927 uint32_t cardnum = 0;
928 uint32_t code1 = 0;
929 uint32_t code2 = 0;
930 uint8_t fmtLen = bytebits_to_byte(dest,8);
931 switch(fmtLen) {
932 case 26:
933 fc = bytebits_to_byte(dest + 9, 8);
934 cardnum = bytebits_to_byte(dest + 17, 16);
935 code1 = bytebits_to_byte(dest + 8,fmtLen);
936 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
937 break;
938 case 50:
939 fc = bytebits_to_byte(dest + 9, 16);
940 cardnum = bytebits_to_byte(dest + 25, 32);
941 code1 = bytebits_to_byte(dest + 8, (fmtLen-32) );
942 code2 = bytebits_to_byte(dest + 8 + (fmtLen-32), 32);
943 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, code2, rawHi2, rawHi, rawLo);
944 break;
945 default:
946 if (fmtLen > 32 ) {
947 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
948 code1 = bytebits_to_byte(dest+8,fmtLen-32);
949 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
950 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
951 } else {
952 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
953 code1 = bytebits_to_byte(dest+8,fmtLen);
954 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
955 }
956 break;
957 }
958 if (findone){
959 if (ledcontrol) LED_A_OFF();
960 return;
961 }
962 idx = 0;
963 WDT_HIT();
964 }
965 DbpString("Stopped");
966 if (ledcontrol) LED_A_OFF();
967 }
968
969 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
970 {
971 uint8_t *dest = BigBuf_get_addr();
972
973 size_t size=0, idx=0;
974 int clk=0, invert=0, errCnt=0, maxErr=20;
975 uint32_t hi=0;
976 uint64_t lo=0;
977 //clear read buffer
978 BigBuf_Clear_keep_EM();
979 // Configure to go in 125Khz listen mode
980 LFSetupFPGAForADC(95, true);
981
982 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
983
984 WDT_HIT();
985 if (ledcontrol) LED_A_ON();
986
987 DoAcquisition_default(-1,true);
988 size = BigBuf_max_traceLen();
989 //askdemod and manchester decode
990 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
991 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
992 WDT_HIT();
993
994 if (errCnt<0) continue;
995
996 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
997 if (errCnt){
998 if (size>64){
999 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
1000 hi,
1001 (uint32_t)(lo>>32),
1002 (uint32_t)lo,
1003 (uint32_t)(lo&0xFFFF),
1004 (uint32_t)((lo>>16LL) & 0xFF),
1005 (uint32_t)(lo & 0xFFFFFF));
1006 } else {
1007 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
1008 (uint32_t)(lo>>32),
1009 (uint32_t)lo,
1010 (uint32_t)(lo&0xFFFF),
1011 (uint32_t)((lo>>16LL) & 0xFF),
1012 (uint32_t)(lo & 0xFFFFFF));
1013 }
1014
1015 if (findone){
1016 if (ledcontrol) LED_A_OFF();
1017 *high=lo>>32;
1018 *low=lo & 0xFFFFFFFF;
1019 return;
1020 }
1021 }
1022 WDT_HIT();
1023 hi = lo = size = idx = 0;
1024 clk = invert = errCnt = 0;
1025 }
1026 DbpString("Stopped");
1027 if (ledcontrol) LED_A_OFF();
1028 }
1029
1030 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
1031 {
1032 uint8_t *dest = BigBuf_get_addr();
1033 int idx=0;
1034 uint32_t code=0, code2=0;
1035 uint8_t version=0;
1036 uint8_t facilitycode=0;
1037 uint16_t number=0;
1038 uint8_t crc = 0;
1039 uint16_t calccrc = 0;
1040
1041 //clear read buffer
1042 BigBuf_Clear_keep_EM();
1043
1044 // Configure to go in 125Khz listen mode
1045 LFSetupFPGAForADC(95, true);
1046
1047 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
1048 WDT_HIT();
1049 if (ledcontrol) LED_A_ON();
1050 DoAcquisition_default(-1,true);
1051 //fskdemod and get start index
1052 WDT_HIT();
1053 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
1054 if (idx<0) continue;
1055 //valid tag found
1056
1057 //Index map
1058 //0 10 20 30 40 50 60
1059 //| | | | | | |
1060 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1061 //-----------------------------------------------------------------------------
1062 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
1063 //
1064 //Checksum:
1065 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
1066 //preamble F0 E0 01 03 B6 75
1067 // How to calc checksum,
1068 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
1069 // F0 + E0 + 01 + 03 + B6 = 28A
1070 // 28A & FF = 8A
1071 // FF - 8A = 75
1072 // Checksum: 0x75
1073 //XSF(version)facility:codeone+codetwo
1074 //Handle the data
1075 if(findone){ //only print binary if we are doing one
1076 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1077 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1078 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1079 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1080 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1081 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1082 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1083 }
1084 code = bytebits_to_byte(dest+idx,32);
1085 code2 = bytebits_to_byte(dest+idx+32,32);
1086 version = bytebits_to_byte(dest+idx+27,8); //14,4
1087 facilitycode = bytebits_to_byte(dest+idx+18,8);
1088 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1089
1090 crc = bytebits_to_byte(dest+idx+54,8);
1091 for (uint8_t i=1; i<6; ++i)
1092 calccrc += bytebits_to_byte(dest+idx+9*i,8);
1093 calccrc &= 0xff;
1094 calccrc = 0xff - calccrc;
1095
1096 char *crcStr = (crc == calccrc) ? "ok":"!crc";
1097
1098 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
1099 // if we're only looking for one tag
1100 if (findone){
1101 if (ledcontrol) LED_A_OFF();
1102 *high=code;
1103 *low=code2;
1104 return;
1105 }
1106 code=code2=0;
1107 version=facilitycode=0;
1108 number=0;
1109 idx=0;
1110
1111 WDT_HIT();
1112 }
1113 DbpString("Stopped");
1114 if (ledcontrol) LED_A_OFF();
1115 }
1116
1117 /*------------------------------
1118 * T5555/T5557/T5567/T5577 routines
1119 *------------------------------
1120 * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
1121 *
1122 * Relevant communication times in microsecond
1123 * To compensate antenna falling times shorten the write times
1124 * and enlarge the gap ones.
1125 * Q5 tags seems to have issues when these values changes.
1126 */
1127
1128 #define START_GAP 50*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (15fc)
1129 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (10fc)
1130 #define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (24fc)
1131 #define WRITE_1 54*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (56fc) 432 for T55x7; 448 for E5550
1132 #define READ_GAP 15*8
1133
1134 // VALUES TAKEN FROM EM4x function: SendForward
1135 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1136 // WRITE_GAP = 128; (16*8)
1137 // WRITE_1 = 256 32*8; (32*8)
1138
1139 // These timings work for 4469/4269/4305 (with the 55*8 above)
1140 // WRITE_0 = 23*8 , 9*8
1141
1142 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1143 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1144 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1145 // T0 = TIMER_CLOCK1 / 125000 = 192
1146 // 1 Cycle = 8 microseconds(us) == 1 field clock
1147
1148 // new timer:
1149 // = 1us = 1.5ticks
1150 // 1fc = 8us = 12ticks
1151 void TurnReadLFOn(uint32_t delay) {
1152 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1153
1154 // measure antenna strength.
1155 //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
1156
1157 // Give it a bit of time for the resonant antenna to settle.
1158 WaitUS(delay);
1159 }
1160
1161 // Write one bit to card
1162 void T55xxWriteBit(int bit) {
1163 if (!bit)
1164 TurnReadLFOn(WRITE_0);
1165 else
1166 TurnReadLFOn(WRITE_1);
1167 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1168 WaitUS(WRITE_GAP);
1169 }
1170
1171 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
1172 void T55xxResetRead(void) {
1173 LED_A_ON();
1174 //clear buffer now so it does not interfere with timing later
1175 BigBuf_Clear_keep_EM();
1176
1177 // Set up FPGA, 125kHz
1178 LFSetupFPGAForADC(95, true);
1179
1180 // Trigger T55x7 in mode.
1181 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1182 WaitUS(START_GAP);
1183
1184 // reset tag - op code 00
1185 T55xxWriteBit(0);
1186 T55xxWriteBit(0);
1187
1188 // Turn field on to read the response
1189 TurnReadLFOn(READ_GAP);
1190
1191 // Acquisition
1192 doT55x7Acquisition(BigBuf_max_traceLen());
1193
1194 // Turn the field off
1195 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1196 cmd_send(CMD_ACK,0,0,0,0,0);
1197 LED_A_OFF();
1198 }
1199
1200 // Write one card block in page 0, no lock
1201 void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1202 LED_A_ON();
1203 bool PwdMode = arg & 0x1;
1204 uint8_t Page = (arg & 0x2)>>1;
1205 uint32_t i = 0;
1206
1207 // Set up FPGA, 125kHz
1208 LFSetupFPGAForADC(95, true);
1209
1210 // Trigger T55x7 in mode.
1211 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1212 WaitUS(START_GAP);
1213
1214 // Opcode 10
1215 T55xxWriteBit(1);
1216 T55xxWriteBit(Page); //Page 0
1217 if (PwdMode){
1218 // Send Pwd
1219 for (i = 0x80000000; i != 0; i >>= 1)
1220 T55xxWriteBit(Pwd & i);
1221 }
1222 // Send Lock bit
1223 T55xxWriteBit(0);
1224
1225 // Send Data
1226 for (i = 0x80000000; i != 0; i >>= 1)
1227 T55xxWriteBit(Data & i);
1228
1229 // Send Block number
1230 for (i = 0x04; i != 0; i >>= 1)
1231 T55xxWriteBit(Block & i);
1232
1233 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1234 // so wait a little more)
1235 TurnReadLFOn(20 * 1000);
1236
1237 //could attempt to do a read to confirm write took
1238 // as the tag should repeat back the new block
1239 // until it is reset, but to confirm it we would
1240 // need to know the current block 0 config mode
1241
1242 // turn field off
1243 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1244 LED_A_OFF();
1245 }
1246
1247 // Write one card block in page 0, no lock
1248 void T55xxWriteBlock(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1249 T55xxWriteBlockExt(Data, Block, Pwd, arg);
1250 cmd_send(CMD_ACK,0,0,0,0,0);
1251 }
1252
1253 // Read one card block in page [page]
1254 void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
1255 LED_A_ON();
1256 bool PwdMode = arg0 & 0x1;
1257 uint8_t Page = (arg0 & 0x2) >> 1;
1258 uint32_t i = 0;
1259 bool RegReadMode = (Block == 0xFF);
1260
1261 //clear buffer now so it does not interfere with timing later
1262 BigBuf_Clear_keep_EM();
1263
1264 //make sure block is at max 7
1265 Block &= 0x7;
1266
1267 // Set up FPGA, 125kHz to power up the tag
1268 LFSetupFPGAForADC(95, true);
1269 SpinDelay(3);
1270
1271 // Trigger T55x7 Direct Access Mode with start gap
1272 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1273 WaitUS(START_GAP);
1274
1275 // Opcode 1[page]
1276 T55xxWriteBit(1);
1277 T55xxWriteBit(Page); //Page 0
1278
1279 if (PwdMode){
1280 // Send Pwd
1281 for (i = 0x80000000; i != 0; i >>= 1)
1282 T55xxWriteBit(Pwd & i);
1283 }
1284 // Send a zero bit separation
1285 T55xxWriteBit(0);
1286
1287 // Send Block number (if direct access mode)
1288 if (!RegReadMode)
1289 for (i = 0x04; i != 0; i >>= 1)
1290 T55xxWriteBit(Block & i);
1291
1292 // Turn field on to read the response
1293 TurnReadLFOn(READ_GAP);
1294
1295 // Acquisition
1296 doT55x7Acquisition(12000);
1297
1298 // Turn the field off
1299 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1300 cmd_send(CMD_ACK,0,0,0,0,0);
1301 LED_A_OFF();
1302 }
1303
1304 void T55xxWakeUp(uint32_t Pwd){
1305 LED_B_ON();
1306 uint32_t i = 0;
1307
1308 // Set up FPGA, 125kHz
1309 LFSetupFPGAForADC(95, true);
1310
1311 // Trigger T55x7 Direct Access Mode
1312 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1313 WaitUS(START_GAP);
1314
1315 // Opcode 10
1316 T55xxWriteBit(1);
1317 T55xxWriteBit(0); //Page 0
1318
1319 // Send Pwd
1320 for (i = 0x80000000; i != 0; i >>= 1)
1321 T55xxWriteBit(Pwd & i);
1322
1323 // Turn and leave field on to let the begin repeating transmission
1324 TurnReadLFOn(20*1000);
1325 }
1326
1327 /*-------------- Cloning routines -----------*/
1328 void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1329 // write last block first and config block last (if included)
1330 for (uint8_t i = numblocks+startblock; i > startblock; i--)
1331 T55xxWriteBlockExt(blockdata[i-1], i-1, 0, 0);
1332 }
1333
1334 // Copy HID id to card and setup block 0 config
1335 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
1336 uint32_t data[] = {0,0,0,0,0,0,0};
1337 uint8_t last_block = 0;
1338
1339 if (longFMT){
1340 // Ensure no more than 84 bits supplied
1341 if (hi2 > 0xFFFFF) {
1342 DbpString("Tags can only have 84 bits.");
1343 return;
1344 }
1345 // Build the 6 data blocks for supplied 84bit ID
1346 last_block = 6;
1347 // load preamble (1D) & long format identifier (9E manchester encoded)
1348 data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
1349 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1350 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1351 data[3] = manchesterEncode2Bytes(hi >> 16);
1352 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1353 data[5] = manchesterEncode2Bytes(lo >> 16);
1354 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
1355 } else {
1356 // Ensure no more than 44 bits supplied
1357 if (hi > 0xFFF) {
1358 DbpString("Tags can only have 44 bits.");
1359 return;
1360 }
1361 // Build the 3 data blocks for supplied 44bit ID
1362 last_block = 3;
1363 // load preamble
1364 data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
1365 data[2] = manchesterEncode2Bytes(lo >> 16);
1366 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
1367 }
1368 // load chip config block
1369 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
1370
1371 //TODO add selection of chip for Q5 or T55x7
1372 // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
1373
1374 LED_D_ON();
1375 // Program the data blocks for supplied ID
1376 // and the block 0 for HID format
1377 WriteT55xx(data, 0, last_block+1);
1378
1379 LED_D_OFF();
1380
1381 DbpString("DONE!");
1382 }
1383
1384 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
1385 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1386 //TODO add selection of chip for Q5 or T55x7
1387 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1388 // data[0] = (64 << T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
1389
1390 LED_D_ON();
1391 // Program the data blocks for supplied ID
1392 // and the block 0 config
1393 WriteT55xx(data, 0, 3);
1394 LED_D_OFF();
1395 DbpString("DONE!");
1396 }
1397
1398 // Clone Indala 64-bit tag by UID to T55x7
1399 void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1400 //Program the 2 data blocks for supplied 64bit UID
1401 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1402 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1403 //TODO add selection of chip for Q5 or T55x7
1404 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
1405
1406 WriteT55xx(data, 0, 3);
1407 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1408 // T5567WriteBlock(0x603E1042,0);
1409 DbpString("DONE!");
1410 }
1411 // Clone Indala 224-bit tag by UID to T55x7
1412 void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
1413 //Program the 7 data blocks for supplied 224bit UID
1414 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1415 // and the block 0 for Indala224 format
1416 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1417 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
1418 //TODO add selection of chip for Q5 or T55x7
1419 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
1420 WriteT55xx(data, 0, 8);
1421 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1422 // T5567WriteBlock(0x603E10E2,0);
1423 DbpString("DONE!");
1424 }
1425 // clone viking tag to T55xx
1426 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
1427 uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
1428 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1429 if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
1430 // Program the data blocks for supplied ID and the block 0 config
1431 WriteT55xx(data, 0, 3);
1432 LED_D_OFF();
1433 cmd_send(CMD_ACK,0,0,0,0,0);
1434 }
1435
1436 // Define 9bit header for EM410x tags
1437 #define EM410X_HEADER 0x1FF
1438 #define EM410X_ID_LENGTH 40
1439
1440 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
1441 int i, id_bit;
1442 uint64_t id = EM410X_HEADER;
1443 uint64_t rev_id = 0; // reversed ID
1444 int c_parity[4]; // column parity
1445 int r_parity = 0; // row parity
1446 uint32_t clock = 0;
1447
1448 // Reverse ID bits given as parameter (for simpler operations)
1449 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1450 if (i < 32) {
1451 rev_id = (rev_id << 1) | (id_lo & 1);
1452 id_lo >>= 1;
1453 } else {
1454 rev_id = (rev_id << 1) | (id_hi & 1);
1455 id_hi >>= 1;
1456 }
1457 }
1458
1459 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1460 id_bit = rev_id & 1;
1461
1462 if (i % 4 == 0) {
1463 // Don't write row parity bit at start of parsing
1464 if (i)
1465 id = (id << 1) | r_parity;
1466 // Start counting parity for new row
1467 r_parity = id_bit;
1468 } else {
1469 // Count row parity
1470 r_parity ^= id_bit;
1471 }
1472
1473 // First elements in column?
1474 if (i < 4)
1475 // Fill out first elements
1476 c_parity[i] = id_bit;
1477 else
1478 // Count column parity
1479 c_parity[i % 4] ^= id_bit;
1480
1481 // Insert ID bit
1482 id = (id << 1) | id_bit;
1483 rev_id >>= 1;
1484 }
1485
1486 // Insert parity bit of last row
1487 id = (id << 1) | r_parity;
1488
1489 // Fill out column parity at the end of tag
1490 for (i = 0; i < 4; ++i)
1491 id = (id << 1) | c_parity[i];
1492
1493 // Add stop bit
1494 id <<= 1;
1495
1496 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1497 LED_D_ON();
1498
1499 // Write EM410x ID
1500 uint32_t data[] = {0, (uint32_t)(id>>32), (uint32_t)(id & 0xFFFFFFFF)};
1501
1502 clock = (card & 0xFF00) >> 8;
1503 clock = (clock == 0) ? 64 : clock;
1504 Dbprintf("Clock rate: %d", clock);
1505 if (card & 0xFF) { //t55x7
1506 clock = GetT55xxClockBit(clock);
1507 if (clock == 0) {
1508 Dbprintf("Invalid clock rate: %d", clock);
1509 return;
1510 }
1511 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
1512 } else { //t5555 (Q5)
1513 clock = (clock-2)>>1; //n = (RF-2)/2
1514 data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
1515 }
1516
1517 WriteT55xx(data, 0, 3);
1518
1519 LED_D_OFF();
1520 Dbprintf("Tag %s written with 0x%08x%08x\n",
1521 card ? "T55x7":"T5555",
1522 (uint32_t)(id >> 32),
1523 (uint32_t)id);
1524 }
1525
1526 //-----------------------------------
1527 // EM4469 / EM4305 routines
1528 //-----------------------------------
1529 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1530 #define FWD_CMD_WRITE 0xA
1531 #define FWD_CMD_READ 0x9
1532 #define FWD_CMD_DISABLE 0x5
1533
1534 uint8_t forwardLink_data[64]; //array of forwarded bits
1535 uint8_t * forward_ptr; //ptr for forward message preparation
1536 uint8_t fwd_bit_sz; //forwardlink bit counter
1537 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1538
1539 //====================================================================
1540 // prepares command bits
1541 // see EM4469 spec
1542 //====================================================================
1543 //--------------------------------------------------------------------
1544 // VALUES TAKEN FROM EM4x function: SendForward
1545 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1546 // WRITE_GAP = 128; (16*8)
1547 // WRITE_1 = 256 32*8; (32*8)
1548
1549 // These timings work for 4469/4269/4305 (with the 55*8 above)
1550 // WRITE_0 = 23*8 , 9*8
1551
1552 uint8_t Prepare_Cmd( uint8_t cmd ) {
1553
1554 *forward_ptr++ = 0; //start bit
1555 *forward_ptr++ = 0; //second pause for 4050 code
1556
1557 *forward_ptr++ = cmd;
1558 cmd >>= 1;
1559 *forward_ptr++ = cmd;
1560 cmd >>= 1;
1561 *forward_ptr++ = cmd;
1562 cmd >>= 1;
1563 *forward_ptr++ = cmd;
1564
1565 return 6; //return number of emited bits
1566 }
1567
1568 //====================================================================
1569 // prepares address bits
1570 // see EM4469 spec
1571 //====================================================================
1572 uint8_t Prepare_Addr( uint8_t addr ) {
1573
1574 register uint8_t line_parity;
1575
1576 uint8_t i;
1577 line_parity = 0;
1578 for(i=0;i<6;i++) {
1579 *forward_ptr++ = addr;
1580 line_parity ^= addr;
1581 addr >>= 1;
1582 }
1583
1584 *forward_ptr++ = (line_parity & 1);
1585
1586 return 7; //return number of emited bits
1587 }
1588
1589 //====================================================================
1590 // prepares data bits intreleaved with parity bits
1591 // see EM4469 spec
1592 //====================================================================
1593 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1594
1595 register uint8_t line_parity;
1596 register uint8_t column_parity;
1597 register uint8_t i, j;
1598 register uint16_t data;
1599
1600 data = data_low;
1601 column_parity = 0;
1602
1603 for(i=0; i<4; i++) {
1604 line_parity = 0;
1605 for(j=0; j<8; j++) {
1606 line_parity ^= data;
1607 column_parity ^= (data & 1) << j;
1608 *forward_ptr++ = data;
1609 data >>= 1;
1610 }
1611 *forward_ptr++ = line_parity;
1612 if(i == 1)
1613 data = data_hi;
1614 }
1615
1616 for(j=0; j<8; j++) {
1617 *forward_ptr++ = column_parity;
1618 column_parity >>= 1;
1619 }
1620 *forward_ptr = 0;
1621
1622 return 45; //return number of emited bits
1623 }
1624
1625 //====================================================================
1626 // Forward Link send function
1627 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1628 // fwd_bit_count set with number of bits to be sent
1629 //====================================================================
1630 void SendForward(uint8_t fwd_bit_count) {
1631
1632 fwd_write_ptr = forwardLink_data;
1633 fwd_bit_sz = fwd_bit_count;
1634
1635 LED_D_ON();
1636
1637 // Set up FPGA, 125kHz
1638 LFSetupFPGAForADC(95, true);
1639
1640 // force 1st mod pulse (start gap must be longer for 4305)
1641 fwd_bit_sz--; //prepare next bit modulation
1642 fwd_write_ptr++;
1643 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1644 WaitUS(55*8); //55 cycles off (8us each)for 4305 // ICEMAN: problem with (us) clock is 21.3us increments
1645 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1646 WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1647
1648 // now start writting
1649 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1650 if(((*fwd_write_ptr++) & 1) == 1)
1651 WaitUS(32*8); //32 cycles at 125Khz (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1652 else {
1653 //These timings work for 4469/4269/4305 (with the 55*8 above)
1654 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1655 WaitUS(16*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1656 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1657 WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1658 }
1659 }
1660 }
1661
1662 void EM4xLogin(uint32_t Password) {
1663
1664 uint8_t fwd_bit_count;
1665 forward_ptr = forwardLink_data;
1666 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1667 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1668 SendForward(fwd_bit_count);
1669
1670 //Wait for command to complete
1671 WaitMS(20);
1672 }
1673
1674 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1675
1676 uint8_t fwd_bit_count;
1677 uint8_t *dest = BigBuf_get_addr();
1678 uint16_t bufsize = BigBuf_max_traceLen(); // ICEMAN: this tries to fill up all tracelog space
1679 uint32_t i = 0;
1680
1681 // Clear destination buffer before sending the command
1682 BigBuf_Clear_ext(false);
1683
1684 //If password mode do login
1685 if (PwdMode == 1) EM4xLogin(Pwd);
1686
1687 forward_ptr = forwardLink_data;
1688 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1689 fwd_bit_count += Prepare_Addr( Address );
1690
1691 SendForward(fwd_bit_count);
1692
1693 // Now do the acquisition
1694 // ICEMAN, change to the one in lfsampling.c
1695 i = 0;
1696 for(;;) {
1697 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1698 AT91C_BASE_SSC->SSC_THR = 0x43;
1699 }
1700 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1701 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1702 ++i;
1703 if (i >= bufsize) break;
1704 }
1705 }
1706
1707 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1708 cmd_send(CMD_ACK,0,0,0,0,0);
1709 LED_D_OFF();
1710 }
1711
1712 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1713
1714 uint8_t fwd_bit_count;
1715
1716 //If password mode do login
1717 if (PwdMode == 1) EM4xLogin(Pwd);
1718
1719 forward_ptr = forwardLink_data;
1720 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1721 fwd_bit_count += Prepare_Addr( Address );
1722 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1723
1724 SendForward(fwd_bit_count);
1725
1726 //Wait for write to complete
1727 WaitMS(20);
1728 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1729 LED_D_OFF();
1730 }
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