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bugfixes iso14443a (hf 14a commands)
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17
18
19 /**
20 * Does the sample acquisition. If threshold is specified, the actual sampling
21 * is not commenced until the threshold has been reached.
22 * @param trigger_threshold - the threshold
23 * @param silent - is true, now outputs are made. If false, dbprints the status
24 */
25 void DoAcquisition125k_internal(int trigger_threshold,bool silent)
26 {
27 uint8_t *dest = (uint8_t *)BigBuf;
28 int n = sizeof(BigBuf);
29 int i;
30
31 memset(dest, 0, n);
32 i = 0;
33 for(;;) {
34 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
35 AT91C_BASE_SSC->SSC_THR = 0x43;
36 LED_D_ON();
37 }
38 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
39 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
40 LED_D_OFF();
41 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
42 continue;
43 else
44 trigger_threshold = -1;
45 if (++i >= n) break;
46 }
47 }
48 if(!silent)
49 {
50 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
51 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
52
53 }
54 }
55 /**
56 * Perform sample aquisition.
57 */
58 void DoAcquisition125k(int trigger_threshold)
59 {
60 DoAcquisition125k_internal(trigger_threshold, false);
61 }
62
63 /**
64 * Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
65 * if not already loaded, sets divisor and starts up the antenna.
66 * @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
67 * 0 or 95 ==> 125 KHz
68 *
69 **/
70 void LFSetupFPGAForADC(int divisor, bool lf_field)
71 {
72 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
73 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
74 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
75 else if (divisor == 0)
76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
77 else
78 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
79
80 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
81
82 // Connect the A/D to the peak-detected low-frequency path.
83 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
84 // Give it a bit of time for the resonant antenna to settle.
85 SpinDelay(50);
86 // Now set up the SSC to get the ADC samples that are now streaming at us.
87 FpgaSetupSsc();
88 }
89 /**
90 * Initializes the FPGA, and acquires the samples.
91 **/
92 void AcquireRawAdcSamples125k(int divisor)
93 {
94 LFSetupFPGAForADC(divisor, true);
95 // Now call the acquisition routine
96 DoAcquisition125k_internal(-1,false);
97 }
98 /**
99 * Initializes the FPGA for snoop-mode, and acquires the samples.
100 **/
101
102 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
103 {
104 LFSetupFPGAForADC(divisor, false);
105 DoAcquisition125k(trigger_threshold);
106 }
107
108 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
109 {
110
111 /* Make sure the tag is reset */
112 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
113 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
114 SpinDelay(2500);
115
116
117 int divisor_used = 95; // 125 KHz
118 // see if 'h' was specified
119
120 if (command[strlen((char *) command) - 1] == 'h')
121 divisor_used = 88; // 134.8 KHz
122
123
124 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
125 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
126 // Give it a bit of time for the resonant antenna to settle.
127 SpinDelay(50);
128
129 // And a little more time for the tag to fully power up
130 SpinDelay(2000);
131
132 // Now set up the SSC to get the ADC samples that are now streaming at us.
133 FpgaSetupSsc();
134
135 // now modulate the reader field
136 while(*command != '\0' && *command != ' ') {
137 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
138 LED_D_OFF();
139 SpinDelayUs(delay_off);
140 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
141
142 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
143 LED_D_ON();
144 if(*(command++) == '0')
145 SpinDelayUs(period_0);
146 else
147 SpinDelayUs(period_1);
148 }
149 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
150 LED_D_OFF();
151 SpinDelayUs(delay_off);
152 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
153
154 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
155
156 // now do the read
157 DoAcquisition125k(-1);
158 }
159
160 /* blank r/w tag data stream
161 ...0000000000000000 01111111
162 1010101010101010101010101010101010101010101010101010101010101010
163 0011010010100001
164 01111111
165 101010101010101[0]000...
166
167 [5555fe852c5555555555555555fe0000]
168 */
169 void ReadTItag(void)
170 {
171 // some hardcoded initial params
172 // when we read a TI tag we sample the zerocross line at 2Mhz
173 // TI tags modulate a 1 as 16 cycles of 123.2Khz
174 // TI tags modulate a 0 as 16 cycles of 134.2Khz
175 #define FSAMPLE 2000000
176 #define FREQLO 123200
177 #define FREQHI 134200
178
179 signed char *dest = (signed char *)BigBuf;
180 int n = sizeof(BigBuf);
181 // int *dest = GraphBuffer;
182 // int n = GraphTraceLen;
183
184 // 128 bit shift register [shift3:shift2:shift1:shift0]
185 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
186
187 int i, cycles=0, samples=0;
188 // how many sample points fit in 16 cycles of each frequency
189 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
190 // when to tell if we're close enough to one freq or another
191 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
192
193 // TI tags charge at 134.2Khz
194 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
195 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
196
197 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
198 // connects to SSP_DIN and the SSP_DOUT logic level controls
199 // whether we're modulating the antenna (high)
200 // or listening to the antenna (low)
201 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
202
203 // get TI tag data into the buffer
204 AcquireTiType();
205
206 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
207
208 for (i=0; i<n-1; i++) {
209 // count cycles by looking for lo to hi zero crossings
210 if ( (dest[i]<0) && (dest[i+1]>0) ) {
211 cycles++;
212 // after 16 cycles, measure the frequency
213 if (cycles>15) {
214 cycles=0;
215 samples=i-samples; // number of samples in these 16 cycles
216
217 // TI bits are coming to us lsb first so shift them
218 // right through our 128 bit right shift register
219 shift0 = (shift0>>1) | (shift1 << 31);
220 shift1 = (shift1>>1) | (shift2 << 31);
221 shift2 = (shift2>>1) | (shift3 << 31);
222 shift3 >>= 1;
223
224 // check if the cycles fall close to the number
225 // expected for either the low or high frequency
226 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
227 // low frequency represents a 1
228 shift3 |= (1<<31);
229 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
230 // high frequency represents a 0
231 } else {
232 // probably detected a gay waveform or noise
233 // use this as gaydar or discard shift register and start again
234 shift3 = shift2 = shift1 = shift0 = 0;
235 }
236 samples = i;
237
238 // for each bit we receive, test if we've detected a valid tag
239
240 // if we see 17 zeroes followed by 6 ones, we might have a tag
241 // remember the bits are backwards
242 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
243 // if start and end bytes match, we have a tag so break out of the loop
244 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
245 cycles = 0xF0B; //use this as a flag (ugly but whatever)
246 break;
247 }
248 }
249 }
250 }
251 }
252
253 // if flag is set we have a tag
254 if (cycles!=0xF0B) {
255 DbpString("Info: No valid tag detected.");
256 } else {
257 // put 64 bit data into shift1 and shift0
258 shift0 = (shift0>>24) | (shift1 << 8);
259 shift1 = (shift1>>24) | (shift2 << 8);
260
261 // align 16 bit crc into lower half of shift2
262 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
263
264 // if r/w tag, check ident match
265 if ( shift3&(1<<15) ) {
266 DbpString("Info: TI tag is rewriteable");
267 // only 15 bits compare, last bit of ident is not valid
268 if ( ((shift3>>16)^shift0)&0x7fff ) {
269 DbpString("Error: Ident mismatch!");
270 } else {
271 DbpString("Info: TI tag ident is valid");
272 }
273 } else {
274 DbpString("Info: TI tag is readonly");
275 }
276
277 // WARNING the order of the bytes in which we calc crc below needs checking
278 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
279 // bytes in reverse or something
280 // calculate CRC
281 uint32_t crc=0;
282
283 crc = update_crc16(crc, (shift0)&0xff);
284 crc = update_crc16(crc, (shift0>>8)&0xff);
285 crc = update_crc16(crc, (shift0>>16)&0xff);
286 crc = update_crc16(crc, (shift0>>24)&0xff);
287 crc = update_crc16(crc, (shift1)&0xff);
288 crc = update_crc16(crc, (shift1>>8)&0xff);
289 crc = update_crc16(crc, (shift1>>16)&0xff);
290 crc = update_crc16(crc, (shift1>>24)&0xff);
291
292 Dbprintf("Info: Tag data: %x%08x, crc=%x",
293 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
294 if (crc != (shift2&0xffff)) {
295 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
296 } else {
297 DbpString("Info: CRC is good");
298 }
299 }
300 }
301
302 void WriteTIbyte(uint8_t b)
303 {
304 int i = 0;
305
306 // modulate 8 bits out to the antenna
307 for (i=0; i<8; i++)
308 {
309 if (b&(1<<i)) {
310 // stop modulating antenna
311 LOW(GPIO_SSC_DOUT);
312 SpinDelayUs(1000);
313 // modulate antenna
314 HIGH(GPIO_SSC_DOUT);
315 SpinDelayUs(1000);
316 } else {
317 // stop modulating antenna
318 LOW(GPIO_SSC_DOUT);
319 SpinDelayUs(300);
320 // modulate antenna
321 HIGH(GPIO_SSC_DOUT);
322 SpinDelayUs(1700);
323 }
324 }
325 }
326
327 void AcquireTiType(void)
328 {
329 int i, j, n;
330 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
331 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
332 #define TIBUFLEN 1250
333
334 // clear buffer
335 memset(BigBuf,0,sizeof(BigBuf));
336
337 // Set up the synchronous serial port
338 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
339 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
340
341 // steal this pin from the SSP and use it to control the modulation
342 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
343 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
344
345 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
346 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
347
348 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
349 // 48/2 = 24 MHz clock must be divided by 12
350 AT91C_BASE_SSC->SSC_CMR = 12;
351
352 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
353 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
354 AT91C_BASE_SSC->SSC_TCMR = 0;
355 AT91C_BASE_SSC->SSC_TFMR = 0;
356
357 LED_D_ON();
358
359 // modulate antenna
360 HIGH(GPIO_SSC_DOUT);
361
362 // Charge TI tag for 50ms.
363 SpinDelay(50);
364
365 // stop modulating antenna and listen
366 LOW(GPIO_SSC_DOUT);
367
368 LED_D_OFF();
369
370 i = 0;
371 for(;;) {
372 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
373 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
374 i++; if(i >= TIBUFLEN) break;
375 }
376 WDT_HIT();
377 }
378
379 // return stolen pin to SSP
380 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
381 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
382
383 char *dest = (char *)BigBuf;
384 n = TIBUFLEN*32;
385 // unpack buffer
386 for (i=TIBUFLEN-1; i>=0; i--) {
387 for (j=0; j<32; j++) {
388 if(BigBuf[i] & (1 << j)) {
389 dest[--n] = 1;
390 } else {
391 dest[--n] = -1;
392 }
393 }
394 }
395 }
396
397 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
398 // if crc provided, it will be written with the data verbatim (even if bogus)
399 // if not provided a valid crc will be computed from the data and written.
400 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
401 {
402 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
403 if(crc == 0) {
404 crc = update_crc16(crc, (idlo)&0xff);
405 crc = update_crc16(crc, (idlo>>8)&0xff);
406 crc = update_crc16(crc, (idlo>>16)&0xff);
407 crc = update_crc16(crc, (idlo>>24)&0xff);
408 crc = update_crc16(crc, (idhi)&0xff);
409 crc = update_crc16(crc, (idhi>>8)&0xff);
410 crc = update_crc16(crc, (idhi>>16)&0xff);
411 crc = update_crc16(crc, (idhi>>24)&0xff);
412 }
413 Dbprintf("Writing to tag: %x%08x, crc=%x",
414 (unsigned int) idhi, (unsigned int) idlo, crc);
415
416 // TI tags charge at 134.2Khz
417 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
418 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
419 // connects to SSP_DIN and the SSP_DOUT logic level controls
420 // whether we're modulating the antenna (high)
421 // or listening to the antenna (low)
422 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
423 LED_A_ON();
424
425 // steal this pin from the SSP and use it to control the modulation
426 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
427 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
428
429 // writing algorithm:
430 // a high bit consists of a field off for 1ms and field on for 1ms
431 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
432 // initiate a charge time of 50ms (field on) then immediately start writing bits
433 // start by writing 0xBB (keyword) and 0xEB (password)
434 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
435 // finally end with 0x0300 (write frame)
436 // all data is sent lsb firts
437 // finish with 15ms programming time
438
439 // modulate antenna
440 HIGH(GPIO_SSC_DOUT);
441 SpinDelay(50); // charge time
442
443 WriteTIbyte(0xbb); // keyword
444 WriteTIbyte(0xeb); // password
445 WriteTIbyte( (idlo )&0xff );
446 WriteTIbyte( (idlo>>8 )&0xff );
447 WriteTIbyte( (idlo>>16)&0xff );
448 WriteTIbyte( (idlo>>24)&0xff );
449 WriteTIbyte( (idhi )&0xff );
450 WriteTIbyte( (idhi>>8 )&0xff );
451 WriteTIbyte( (idhi>>16)&0xff );
452 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
453 WriteTIbyte( (crc )&0xff ); // crc lo
454 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
455 WriteTIbyte(0x00); // write frame lo
456 WriteTIbyte(0x03); // write frame hi
457 HIGH(GPIO_SSC_DOUT);
458 SpinDelay(50); // programming time
459
460 LED_A_OFF();
461
462 // get TI tag data into the buffer
463 AcquireTiType();
464
465 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
466 DbpString("Now use tiread to check");
467 }
468
469 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
470 {
471 int i;
472 uint8_t *tab = (uint8_t *)BigBuf;
473
474 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
475 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
476
477 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
478
479 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
480 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
481
482 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
483 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
484
485 i = 0;
486 for(;;) {
487 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
488 if(BUTTON_PRESS()) {
489 DbpString("Stopped");
490 return;
491 }
492 WDT_HIT();
493 }
494
495 if (ledcontrol)
496 LED_D_ON();
497
498 if(tab[i])
499 OPEN_COIL();
500 else
501 SHORT_COIL();
502
503 if (ledcontrol)
504 LED_D_OFF();
505
506 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
507 if(BUTTON_PRESS()) {
508 DbpString("Stopped");
509 return;
510 }
511 WDT_HIT();
512 }
513
514 i++;
515 if(i == period) {
516 i = 0;
517 if (gap) {
518 SHORT_COIL();
519 SpinDelayUs(gap);
520 }
521 }
522 }
523 }
524
525 #define DEBUG_FRAME_CONTENTS 1
526 void SimulateTagLowFrequencyBidir(int divisor, int t0)
527 {
528 }
529
530 // compose fc/8 fc/10 waveform
531 static void fc(int c, int *n) {
532 uint8_t *dest = (uint8_t *)BigBuf;
533 int idx;
534
535 // for when we want an fc8 pattern every 4 logical bits
536 if(c==0) {
537 dest[((*n)++)]=1;
538 dest[((*n)++)]=1;
539 dest[((*n)++)]=0;
540 dest[((*n)++)]=0;
541 dest[((*n)++)]=0;
542 dest[((*n)++)]=0;
543 dest[((*n)++)]=0;
544 dest[((*n)++)]=0;
545 }
546 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
547 if(c==8) {
548 for (idx=0; idx<6; idx++) {
549 dest[((*n)++)]=1;
550 dest[((*n)++)]=1;
551 dest[((*n)++)]=0;
552 dest[((*n)++)]=0;
553 dest[((*n)++)]=0;
554 dest[((*n)++)]=0;
555 dest[((*n)++)]=0;
556 dest[((*n)++)]=0;
557 }
558 }
559
560 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
561 if(c==10) {
562 for (idx=0; idx<5; idx++) {
563 dest[((*n)++)]=1;
564 dest[((*n)++)]=1;
565 dest[((*n)++)]=1;
566 dest[((*n)++)]=0;
567 dest[((*n)++)]=0;
568 dest[((*n)++)]=0;
569 dest[((*n)++)]=0;
570 dest[((*n)++)]=0;
571 dest[((*n)++)]=0;
572 dest[((*n)++)]=0;
573 }
574 }
575 }
576
577 // prepare a waveform pattern in the buffer based on the ID given then
578 // simulate a HID tag until the button is pressed
579 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
580 {
581 int n=0, i=0;
582 /*
583 HID tag bitstream format
584 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
585 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
586 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
587 A fc8 is inserted before every 4 bits
588 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
589 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
590 */
591
592 if (hi>0xFFF) {
593 DbpString("Tags can only have 44 bits.");
594 return;
595 }
596 fc(0,&n);
597 // special start of frame marker containing invalid bit sequences
598 fc(8, &n); fc(8, &n); // invalid
599 fc(8, &n); fc(10, &n); // logical 0
600 fc(10, &n); fc(10, &n); // invalid
601 fc(8, &n); fc(10, &n); // logical 0
602
603 WDT_HIT();
604 // manchester encode bits 43 to 32
605 for (i=11; i>=0; i--) {
606 if ((i%4)==3) fc(0,&n);
607 if ((hi>>i)&1) {
608 fc(10, &n); fc(8, &n); // low-high transition
609 } else {
610 fc(8, &n); fc(10, &n); // high-low transition
611 }
612 }
613
614 WDT_HIT();
615 // manchester encode bits 31 to 0
616 for (i=31; i>=0; i--) {
617 if ((i%4)==3) fc(0,&n);
618 if ((lo>>i)&1) {
619 fc(10, &n); fc(8, &n); // low-high transition
620 } else {
621 fc(8, &n); fc(10, &n); // high-low transition
622 }
623 }
624
625 if (ledcontrol)
626 LED_A_ON();
627 SimulateTagLowFrequency(n, 0, ledcontrol);
628
629 if (ledcontrol)
630 LED_A_OFF();
631 }
632
633 size_t fsk_demod(uint8_t * dest, size_t size)
634 {
635 uint32_t last_transition = 0;
636 uint32_t idx = 1;
637
638 // we don't care about actual value, only if it's more or less than a
639 // threshold essentially we capture zero crossings for later analysis
640 uint8_t threshold_value = 127;
641
642 // sync to first lo-hi transition, and threshold
643
644 //Need to threshold first sample
645 if(dest[0] < threshold_value) dest[0] = 0;
646 else dest[0] = 1;
647
648 size_t numBits = 0;
649 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
650 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
651 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
652 for(idx = 1; idx < size; idx++) {
653 // threshold current value
654 if (dest[idx] < threshold_value) dest[idx] = 0;
655 else dest[idx] = 1;
656
657 // Check for 0->1 transition
658 if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition
659
660 if (idx-last_transition < 9) {
661 dest[numBits]=1;
662 } else {
663 dest[numBits]=0;
664 }
665 last_transition = idx;
666 numBits++;
667 }
668 }
669 return numBits; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0
670 }
671
672
673 size_t aggregate_bits(uint8_t *dest,size_t size, uint8_t h2l_crossing_value,uint8_t l2h_crossing_value, uint8_t maxConsequtiveBits )
674 {
675 uint8_t lastval=dest[0];
676 uint32_t idx=0;
677 size_t numBits=0;
678 uint32_t n=1;
679
680 for( idx=1; idx < size; idx++) {
681
682 if (dest[idx]==lastval) {
683 n++;
684 continue;
685 }
686 //if lastval was 1, we have a 1->0 crossing
687 if ( dest[idx-1] ) {
688 n=(n+1) / h2l_crossing_value;
689 } else {// 0->1 crossing
690 n=(n+1) / l2h_crossing_value;
691 }
692 if (n == 0) n = 1;
693
694 if(n < maxConsequtiveBits)
695 {
696 memset(dest+numBits, dest[idx-1] , n);
697 numBits += n;
698 }
699 n=0;
700 lastval=dest[idx];
701 }//end for
702
703 return numBits;
704
705 }
706 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
707 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
708 {
709 uint8_t *dest = (uint8_t *)BigBuf;
710
711 size_t size=0,idx=0; //, found=0;
712 uint32_t hi2=0, hi=0, lo=0;
713
714 // Configure to go in 125Khz listen mode
715 LFSetupFPGAForADC(95, true);
716
717 while(!BUTTON_PRESS()) {
718
719 WDT_HIT();
720 if (ledcontrol) LED_A_ON();
721
722 DoAcquisition125k_internal(-1,true);
723 size = sizeof(BigBuf);
724
725 // FSK demodulator
726 size = fsk_demod(dest, size);
727
728 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
729 // 1->0 : fc/8 in sets of 6
730 // 0->1 : fc/10 in sets of 5
731 size = aggregate_bits(dest,size, 6,5,5);
732
733 WDT_HIT();
734
735 // final loop, go over previously decoded manchester data and decode into usable tag ID
736 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
737 uint8_t frame_marker_mask[] = {1,1,1,0,0,0};
738 int numshifts = 0;
739 idx = 0;
740 while( idx + sizeof(frame_marker_mask) < size) {
741 // search for a start of frame marker
742 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
743 { // frame marker found
744 idx+=sizeof(frame_marker_mask);
745
746 while(dest[idx] != dest[idx+1] && idx < size-2)
747 {
748 // Keep going until next frame marker (or error)
749 // Shift in a bit. Start by shifting high registers
750 hi2 = (hi2<<1)|(hi>>31);
751 hi = (hi<<1)|(lo>>31);
752 //Then, shift in a 0 or one into low
753 if (dest[idx] && !dest[idx+1]) // 1 0
754 lo=(lo<<1)|0;
755 else // 0 1
756 lo=(lo<<1)|
757 1;
758 numshifts ++;
759 idx += 2;
760 }
761 //Dbprintf("Num shifts: %d ", numshifts);
762 // Hopefully, we read a tag and hit upon the next frame marker
763 if(idx + sizeof(frame_marker_mask) < size)
764 {
765 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
766 {
767 if (hi2 != 0){
768 Dbprintf("TAG ID: %x%08x%08x (%d)",
769 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
770 }
771 else {
772 Dbprintf("TAG ID: %x%08x (%d)",
773 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
774 }
775 }
776
777 }
778
779 // reset
780 hi2 = hi = lo = 0;
781 numshifts = 0;
782 }else
783 {
784 idx++;
785 }
786 }
787 WDT_HIT();
788
789 }
790 DbpString("Stopped");
791 if (ledcontrol) LED_A_OFF();
792 }
793
794 uint32_t bytebits_to_byte(uint8_t* src, int numbits)
795 {
796 uint32_t num = 0;
797 for(int i = 0 ; i < numbits ; i++)
798 {
799 num = (num << 1) | (*src);
800 src++;
801 }
802 return num;
803 }
804
805
806 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
807 {
808 uint8_t *dest = (uint8_t *)BigBuf;
809
810 size_t size=0, idx=0;
811 uint32_t code=0, code2=0;
812
813 // Configure to go in 125Khz listen mode
814 LFSetupFPGAForADC(95, true);
815
816 while(!BUTTON_PRESS()) {
817
818
819 WDT_HIT();
820 if (ledcontrol) LED_A_ON();
821
822 DoAcquisition125k_internal(-1,true);
823 size = sizeof(BigBuf);
824
825 // FSK demodulator
826 size = fsk_demod(dest, size);
827
828 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
829 // 1->0 : fc/8 in sets of 7
830 // 0->1 : fc/10 in sets of 6
831 size = aggregate_bits(dest, size, 7,6,13);
832
833 WDT_HIT();
834
835 //Handle the data
836 uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
837 for( idx=0; idx < size - 64; idx++) {
838
839 if ( memcmp(dest + idx, mask, sizeof(mask)) ) continue;
840
841 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7]);
842 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+8], dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15]);
843 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+16],dest[idx+17],dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23]);
844 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+24],dest[idx+25],dest[idx+26],dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31]);
845 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35],dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39]);
846 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44],dest[idx+45],dest[idx+46],dest[idx+47]);
847 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53],dest[idx+54],dest[idx+55]);
848 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
849
850 code = bytebits_to_byte(dest+idx,32);
851 code2 = bytebits_to_byte(dest+idx+32,32);
852
853 short version = bytebits_to_byte(dest+idx+14,4);
854 char unknown = bytebits_to_byte(dest+idx+19,8) ;
855 uint16_t number = bytebits_to_byte(dest+idx+36,9);
856
857 Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,unknown,number,code,code2);
858 if (ledcontrol) LED_D_OFF();
859
860 // if we're only looking for one tag
861 if (findone){
862 LED_A_OFF();
863 return;
864 }
865 }
866 WDT_HIT();
867 }
868 DbpString("Stopped");
869 if (ledcontrol) LED_A_OFF();
870 }
871
872 /*------------------------------
873 * T5555/T5557/T5567 routines
874 *------------------------------
875 */
876
877 /* T55x7 configuration register definitions */
878 #define T55x7_POR_DELAY 0x00000001
879 #define T55x7_ST_TERMINATOR 0x00000008
880 #define T55x7_PWD 0x00000010
881 #define T55x7_MAXBLOCK_SHIFT 5
882 #define T55x7_AOR 0x00000200
883 #define T55x7_PSKCF_RF_2 0
884 #define T55x7_PSKCF_RF_4 0x00000400
885 #define T55x7_PSKCF_RF_8 0x00000800
886 #define T55x7_MODULATION_DIRECT 0
887 #define T55x7_MODULATION_PSK1 0x00001000
888 #define T55x7_MODULATION_PSK2 0x00002000
889 #define T55x7_MODULATION_PSK3 0x00003000
890 #define T55x7_MODULATION_FSK1 0x00004000
891 #define T55x7_MODULATION_FSK2 0x00005000
892 #define T55x7_MODULATION_FSK1a 0x00006000
893 #define T55x7_MODULATION_FSK2a 0x00007000
894 #define T55x7_MODULATION_MANCHESTER 0x00008000
895 #define T55x7_MODULATION_BIPHASE 0x00010000
896 #define T55x7_BITRATE_RF_8 0
897 #define T55x7_BITRATE_RF_16 0x00040000
898 #define T55x7_BITRATE_RF_32 0x00080000
899 #define T55x7_BITRATE_RF_40 0x000C0000
900 #define T55x7_BITRATE_RF_50 0x00100000
901 #define T55x7_BITRATE_RF_64 0x00140000
902 #define T55x7_BITRATE_RF_100 0x00180000
903 #define T55x7_BITRATE_RF_128 0x001C0000
904
905 /* T5555 (Q5) configuration register definitions */
906 #define T5555_ST_TERMINATOR 0x00000001
907 #define T5555_MAXBLOCK_SHIFT 0x00000001
908 #define T5555_MODULATION_MANCHESTER 0
909 #define T5555_MODULATION_PSK1 0x00000010
910 #define T5555_MODULATION_PSK2 0x00000020
911 #define T5555_MODULATION_PSK3 0x00000030
912 #define T5555_MODULATION_FSK1 0x00000040
913 #define T5555_MODULATION_FSK2 0x00000050
914 #define T5555_MODULATION_BIPHASE 0x00000060
915 #define T5555_MODULATION_DIRECT 0x00000070
916 #define T5555_INVERT_OUTPUT 0x00000080
917 #define T5555_PSK_RF_2 0
918 #define T5555_PSK_RF_4 0x00000100
919 #define T5555_PSK_RF_8 0x00000200
920 #define T5555_USE_PWD 0x00000400
921 #define T5555_USE_AOR 0x00000800
922 #define T5555_BITRATE_SHIFT 12
923 #define T5555_FAST_WRITE 0x00004000
924 #define T5555_PAGE_SELECT 0x00008000
925
926 /*
927 * Relevant times in microsecond
928 * To compensate antenna falling times shorten the write times
929 * and enlarge the gap ones.
930 */
931 #define START_GAP 250
932 #define WRITE_GAP 160
933 #define WRITE_0 144 // 192
934 #define WRITE_1 400 // 432 for T55x7; 448 for E5550
935
936 // Write one bit to card
937 void T55xxWriteBit(int bit)
938 {
939 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
940 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
941 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
942 if (bit == 0)
943 SpinDelayUs(WRITE_0);
944 else
945 SpinDelayUs(WRITE_1);
946 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
947 SpinDelayUs(WRITE_GAP);
948 }
949
950 // Write one card block in page 0, no lock
951 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
952 {
953 unsigned int i;
954
955 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
956 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
957 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
958
959 // Give it a bit of time for the resonant antenna to settle.
960 // And for the tag to fully power up
961 SpinDelay(150);
962
963 // Now start writting
964 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
965 SpinDelayUs(START_GAP);
966
967 // Opcode
968 T55xxWriteBit(1);
969 T55xxWriteBit(0); //Page 0
970 if (PwdMode == 1){
971 // Pwd
972 for (i = 0x80000000; i != 0; i >>= 1)
973 T55xxWriteBit(Pwd & i);
974 }
975 // Lock bit
976 T55xxWriteBit(0);
977
978 // Data
979 for (i = 0x80000000; i != 0; i >>= 1)
980 T55xxWriteBit(Data & i);
981
982 // Block
983 for (i = 0x04; i != 0; i >>= 1)
984 T55xxWriteBit(Block & i);
985
986 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
987 // so wait a little more)
988 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
989 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
990 SpinDelay(20);
991 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
992 }
993
994 // Read one card block in page 0
995 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
996 {
997 uint8_t *dest = (uint8_t *)BigBuf;
998 int m=0, i=0;
999
1000 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1001 m = sizeof(BigBuf);
1002 // Clear destination buffer before sending the command
1003 memset(dest, 128, m);
1004 // Connect the A/D to the peak-detected low-frequency path.
1005 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1006 // Now set up the SSC to get the ADC samples that are now streaming at us.
1007 FpgaSetupSsc();
1008
1009 LED_D_ON();
1010 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1011 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1012
1013 // Give it a bit of time for the resonant antenna to settle.
1014 // And for the tag to fully power up
1015 SpinDelay(150);
1016
1017 // Now start writting
1018 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1019 SpinDelayUs(START_GAP);
1020
1021 // Opcode
1022 T55xxWriteBit(1);
1023 T55xxWriteBit(0); //Page 0
1024 if (PwdMode == 1){
1025 // Pwd
1026 for (i = 0x80000000; i != 0; i >>= 1)
1027 T55xxWriteBit(Pwd & i);
1028 }
1029 // Lock bit
1030 T55xxWriteBit(0);
1031 // Block
1032 for (i = 0x04; i != 0; i >>= 1)
1033 T55xxWriteBit(Block & i);
1034
1035 // Turn field on to read the response
1036 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1037 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1038
1039 // Now do the acquisition
1040 i = 0;
1041 for(;;) {
1042 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1043 AT91C_BASE_SSC->SSC_THR = 0x43;
1044 }
1045 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1046 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1047 // we don't care about actual value, only if it's more or less than a
1048 // threshold essentially we capture zero crossings for later analysis
1049 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1050 i++;
1051 if (i >= m) break;
1052 }
1053 }
1054
1055 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1056 LED_D_OFF();
1057 DbpString("DONE!");
1058 }
1059
1060 // Read card traceability data (page 1)
1061 void T55xxReadTrace(void){
1062 uint8_t *dest = (uint8_t *)BigBuf;
1063 int m=0, i=0;
1064
1065 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1066 m = sizeof(BigBuf);
1067 // Clear destination buffer before sending the command
1068 memset(dest, 128, m);
1069 // Connect the A/D to the peak-detected low-frequency path.
1070 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1071 // Now set up the SSC to get the ADC samples that are now streaming at us.
1072 FpgaSetupSsc();
1073
1074 LED_D_ON();
1075 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1076 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1077
1078 // Give it a bit of time for the resonant antenna to settle.
1079 // And for the tag to fully power up
1080 SpinDelay(150);
1081
1082 // Now start writting
1083 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1084 SpinDelayUs(START_GAP);
1085
1086 // Opcode
1087 T55xxWriteBit(1);
1088 T55xxWriteBit(1); //Page 1
1089
1090 // Turn field on to read the response
1091 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1092 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1093
1094 // Now do the acquisition
1095 i = 0;
1096 for(;;) {
1097 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1098 AT91C_BASE_SSC->SSC_THR = 0x43;
1099 }
1100 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1101 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1102 i++;
1103 if (i >= m) break;
1104 }
1105 }
1106
1107 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1108 LED_D_OFF();
1109 DbpString("DONE!");
1110 }
1111
1112 /*-------------- Cloning routines -----------*/
1113 // Copy HID id to card and setup block 0 config
1114 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1115 {
1116 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1117 int last_block = 0;
1118
1119 if (longFMT){
1120 // Ensure no more than 84 bits supplied
1121 if (hi2>0xFFFFF) {
1122 DbpString("Tags can only have 84 bits.");
1123 return;
1124 }
1125 // Build the 6 data blocks for supplied 84bit ID
1126 last_block = 6;
1127 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1128 for (int i=0;i<4;i++) {
1129 if (hi2 & (1<<(19-i)))
1130 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1131 else
1132 data1 |= (1<<((3-i)*2)); // 0 -> 01
1133 }
1134
1135 data2 = 0;
1136 for (int i=0;i<16;i++) {
1137 if (hi2 & (1<<(15-i)))
1138 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1139 else
1140 data2 |= (1<<((15-i)*2)); // 0 -> 01
1141 }
1142
1143 data3 = 0;
1144 for (int i=0;i<16;i++) {
1145 if (hi & (1<<(31-i)))
1146 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1147 else
1148 data3 |= (1<<((15-i)*2)); // 0 -> 01
1149 }
1150
1151 data4 = 0;
1152 for (int i=0;i<16;i++) {
1153 if (hi & (1<<(15-i)))
1154 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1155 else
1156 data4 |= (1<<((15-i)*2)); // 0 -> 01
1157 }
1158
1159 data5 = 0;
1160 for (int i=0;i<16;i++) {
1161 if (lo & (1<<(31-i)))
1162 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1163 else
1164 data5 |= (1<<((15-i)*2)); // 0 -> 01
1165 }
1166
1167 data6 = 0;
1168 for (int i=0;i<16;i++) {
1169 if (lo & (1<<(15-i)))
1170 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1171 else
1172 data6 |= (1<<((15-i)*2)); // 0 -> 01
1173 }
1174 }
1175 else {
1176 // Ensure no more than 44 bits supplied
1177 if (hi>0xFFF) {
1178 DbpString("Tags can only have 44 bits.");
1179 return;
1180 }
1181
1182 // Build the 3 data blocks for supplied 44bit ID
1183 last_block = 3;
1184
1185 data1 = 0x1D000000; // load preamble
1186
1187 for (int i=0;i<12;i++) {
1188 if (hi & (1<<(11-i)))
1189 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1190 else
1191 data1 |= (1<<((11-i)*2)); // 0 -> 01
1192 }
1193
1194 data2 = 0;
1195 for (int i=0;i<16;i++) {
1196 if (lo & (1<<(31-i)))
1197 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1198 else
1199 data2 |= (1<<((15-i)*2)); // 0 -> 01
1200 }
1201
1202 data3 = 0;
1203 for (int i=0;i<16;i++) {
1204 if (lo & (1<<(15-i)))
1205 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1206 else
1207 data3 |= (1<<((15-i)*2)); // 0 -> 01
1208 }
1209 }
1210
1211 LED_D_ON();
1212 // Program the data blocks for supplied ID
1213 // and the block 0 for HID format
1214 T55xxWriteBlock(data1,1,0,0);
1215 T55xxWriteBlock(data2,2,0,0);
1216 T55xxWriteBlock(data3,3,0,0);
1217
1218 if (longFMT) { // if long format there are 6 blocks
1219 T55xxWriteBlock(data4,4,0,0);
1220 T55xxWriteBlock(data5,5,0,0);
1221 T55xxWriteBlock(data6,6,0,0);
1222 }
1223
1224 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1225 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1226 T55x7_MODULATION_FSK2a |
1227 last_block << T55x7_MAXBLOCK_SHIFT,
1228 0,0,0);
1229
1230 LED_D_OFF();
1231
1232 DbpString("DONE!");
1233 }
1234
1235 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1236 {
1237 int data1=0, data2=0; //up to six blocks for long format
1238
1239 data1 = hi; // load preamble
1240 data2 = lo;
1241
1242 LED_D_ON();
1243 // Program the data blocks for supplied ID
1244 // and the block 0 for HID format
1245 T55xxWriteBlock(data1,1,0,0);
1246 T55xxWriteBlock(data2,2,0,0);
1247
1248 //Config Block
1249 T55xxWriteBlock(0x00147040,0,0,0);
1250 LED_D_OFF();
1251
1252 DbpString("DONE!");
1253 }
1254
1255 // Define 9bit header for EM410x tags
1256 #define EM410X_HEADER 0x1FF
1257 #define EM410X_ID_LENGTH 40
1258
1259 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1260 {
1261 int i, id_bit;
1262 uint64_t id = EM410X_HEADER;
1263 uint64_t rev_id = 0; // reversed ID
1264 int c_parity[4]; // column parity
1265 int r_parity = 0; // row parity
1266 uint32_t clock = 0;
1267
1268 // Reverse ID bits given as parameter (for simpler operations)
1269 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1270 if (i < 32) {
1271 rev_id = (rev_id << 1) | (id_lo & 1);
1272 id_lo >>= 1;
1273 } else {
1274 rev_id = (rev_id << 1) | (id_hi & 1);
1275 id_hi >>= 1;
1276 }
1277 }
1278
1279 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1280 id_bit = rev_id & 1;
1281
1282 if (i % 4 == 0) {
1283 // Don't write row parity bit at start of parsing
1284 if (i)
1285 id = (id << 1) | r_parity;
1286 // Start counting parity for new row
1287 r_parity = id_bit;
1288 } else {
1289 // Count row parity
1290 r_parity ^= id_bit;
1291 }
1292
1293 // First elements in column?
1294 if (i < 4)
1295 // Fill out first elements
1296 c_parity[i] = id_bit;
1297 else
1298 // Count column parity
1299 c_parity[i % 4] ^= id_bit;
1300
1301 // Insert ID bit
1302 id = (id << 1) | id_bit;
1303 rev_id >>= 1;
1304 }
1305
1306 // Insert parity bit of last row
1307 id = (id << 1) | r_parity;
1308
1309 // Fill out column parity at the end of tag
1310 for (i = 0; i < 4; ++i)
1311 id = (id << 1) | c_parity[i];
1312
1313 // Add stop bit
1314 id <<= 1;
1315
1316 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1317 LED_D_ON();
1318
1319 // Write EM410x ID
1320 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1321 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1322
1323 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1324 if (card) {
1325 // Clock rate is stored in bits 8-15 of the card value
1326 clock = (card & 0xFF00) >> 8;
1327 Dbprintf("Clock rate: %d", clock);
1328 switch (clock)
1329 {
1330 case 32:
1331 clock = T55x7_BITRATE_RF_32;
1332 break;
1333 case 16:
1334 clock = T55x7_BITRATE_RF_16;
1335 break;
1336 case 0:
1337 // A value of 0 is assumed to be 64 for backwards-compatibility
1338 // Fall through...
1339 case 64:
1340 clock = T55x7_BITRATE_RF_64;
1341 break;
1342 default:
1343 Dbprintf("Invalid clock rate: %d", clock);
1344 return;
1345 }
1346
1347 // Writing configuration for T55x7 tag
1348 T55xxWriteBlock(clock |
1349 T55x7_MODULATION_MANCHESTER |
1350 2 << T55x7_MAXBLOCK_SHIFT,
1351 0, 0, 0);
1352 }
1353 else
1354 // Writing configuration for T5555(Q5) tag
1355 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1356 T5555_MODULATION_MANCHESTER |
1357 2 << T5555_MAXBLOCK_SHIFT,
1358 0, 0, 0);
1359
1360 LED_D_OFF();
1361 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1362 (uint32_t)(id >> 32), (uint32_t)id);
1363 }
1364
1365 // Clone Indala 64-bit tag by UID to T55x7
1366 void CopyIndala64toT55x7(int hi, int lo)
1367 {
1368
1369 //Program the 2 data blocks for supplied 64bit UID
1370 // and the block 0 for Indala64 format
1371 T55xxWriteBlock(hi,1,0,0);
1372 T55xxWriteBlock(lo,2,0,0);
1373 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1374 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1375 T55x7_MODULATION_PSK1 |
1376 2 << T55x7_MAXBLOCK_SHIFT,
1377 0, 0, 0);
1378 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1379 // T5567WriteBlock(0x603E1042,0);
1380
1381 DbpString("DONE!");
1382
1383 }
1384
1385 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1386 {
1387
1388 //Program the 7 data blocks for supplied 224bit UID
1389 // and the block 0 for Indala224 format
1390 T55xxWriteBlock(uid1,1,0,0);
1391 T55xxWriteBlock(uid2,2,0,0);
1392 T55xxWriteBlock(uid3,3,0,0);
1393 T55xxWriteBlock(uid4,4,0,0);
1394 T55xxWriteBlock(uid5,5,0,0);
1395 T55xxWriteBlock(uid6,6,0,0);
1396 T55xxWriteBlock(uid7,7,0,0);
1397 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1398 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1399 T55x7_MODULATION_PSK1 |
1400 7 << T55x7_MAXBLOCK_SHIFT,
1401 0,0,0);
1402 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1403 // T5567WriteBlock(0x603E10E2,0);
1404
1405 DbpString("DONE!");
1406
1407 }
1408
1409
1410 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1411 #define max(x,y) ( x<y ? y:x)
1412
1413 int DemodPCF7931(uint8_t **outBlocks) {
1414 uint8_t BitStream[256];
1415 uint8_t Blocks[8][16];
1416 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1417 int GraphTraceLen = sizeof(BigBuf);
1418 int i, j, lastval, bitidx, half_switch;
1419 int clock = 64;
1420 int tolerance = clock / 8;
1421 int pmc, block_done;
1422 int lc, warnings = 0;
1423 int num_blocks = 0;
1424 int lmin=128, lmax=128;
1425 uint8_t dir;
1426
1427 AcquireRawAdcSamples125k(0);
1428
1429 lmin = 64;
1430 lmax = 192;
1431
1432 i = 2;
1433
1434 /* Find first local max/min */
1435 if(GraphBuffer[1] > GraphBuffer[0]) {
1436 while(i < GraphTraceLen) {
1437 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1438 break;
1439 i++;
1440 }
1441 dir = 0;
1442 }
1443 else {
1444 while(i < GraphTraceLen) {
1445 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1446 break;
1447 i++;
1448 }
1449 dir = 1;
1450 }
1451
1452 lastval = i++;
1453 half_switch = 0;
1454 pmc = 0;
1455 block_done = 0;
1456
1457 for (bitidx = 0; i < GraphTraceLen; i++)
1458 {
1459 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1460 {
1461 lc = i - lastval;
1462 lastval = i;
1463
1464 // Switch depending on lc length:
1465 // Tolerance is 1/8 of clock rate (arbitrary)
1466 if (abs(lc-clock/4) < tolerance) {
1467 // 16T0
1468 if((i - pmc) == lc) { /* 16T0 was previous one */
1469 /* It's a PMC ! */
1470 i += (128+127+16+32+33+16)-1;
1471 lastval = i;
1472 pmc = 0;
1473 block_done = 1;
1474 }
1475 else {
1476 pmc = i;
1477 }
1478 } else if (abs(lc-clock/2) < tolerance) {
1479 // 32TO
1480 if((i - pmc) == lc) { /* 16T0 was previous one */
1481 /* It's a PMC ! */
1482 i += (128+127+16+32+33)-1;
1483 lastval = i;
1484 pmc = 0;
1485 block_done = 1;
1486 }
1487 else if(half_switch == 1) {
1488 BitStream[bitidx++] = 0;
1489 half_switch = 0;
1490 }
1491 else
1492 half_switch++;
1493 } else if (abs(lc-clock) < tolerance) {
1494 // 64TO
1495 BitStream[bitidx++] = 1;
1496 } else {
1497 // Error
1498 warnings++;
1499 if (warnings > 10)
1500 {
1501 Dbprintf("Error: too many detection errors, aborting.");
1502 return 0;
1503 }
1504 }
1505
1506 if(block_done == 1) {
1507 if(bitidx == 128) {
1508 for(j=0; j<16; j++) {
1509 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1510 64*BitStream[j*8+6]+
1511 32*BitStream[j*8+5]+
1512 16*BitStream[j*8+4]+
1513 8*BitStream[j*8+3]+
1514 4*BitStream[j*8+2]+
1515 2*BitStream[j*8+1]+
1516 BitStream[j*8];
1517 }
1518 num_blocks++;
1519 }
1520 bitidx = 0;
1521 block_done = 0;
1522 half_switch = 0;
1523 }
1524 if(i < GraphTraceLen)
1525 {
1526 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1527 else dir = 1;
1528 }
1529 }
1530 if(bitidx==255)
1531 bitidx=0;
1532 warnings = 0;
1533 if(num_blocks == 4) break;
1534 }
1535 memcpy(outBlocks, Blocks, 16*num_blocks);
1536 return num_blocks;
1537 }
1538
1539 int IsBlock0PCF7931(uint8_t *Block) {
1540 // Assume RFU means 0 :)
1541 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1542 return 1;
1543 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1544 return 1;
1545 return 0;
1546 }
1547
1548 int IsBlock1PCF7931(uint8_t *Block) {
1549 // Assume RFU means 0 :)
1550 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1551 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1552 return 1;
1553
1554 return 0;
1555 }
1556
1557 #define ALLOC 16
1558
1559 void ReadPCF7931() {
1560 uint8_t Blocks[8][17];
1561 uint8_t tmpBlocks[4][16];
1562 int i, j, ind, ind2, n;
1563 int num_blocks = 0;
1564 int max_blocks = 8;
1565 int ident = 0;
1566 int error = 0;
1567 int tries = 0;
1568
1569 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1570
1571 do {
1572 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1573 n = DemodPCF7931((uint8_t**)tmpBlocks);
1574 if(!n)
1575 error++;
1576 if(error==10 && num_blocks == 0) {
1577 Dbprintf("Error, no tag or bad tag");
1578 return;
1579 }
1580 else if (tries==20 || error==10) {
1581 Dbprintf("Error reading the tag");
1582 Dbprintf("Here is the partial content");
1583 goto end;
1584 }
1585
1586 for(i=0; i<n; i++)
1587 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1588 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1589 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1590 if(!ident) {
1591 for(i=0; i<n; i++) {
1592 if(IsBlock0PCF7931(tmpBlocks[i])) {
1593 // Found block 0 ?
1594 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1595 // Found block 1!
1596 // \o/
1597 ident = 1;
1598 memcpy(Blocks[0], tmpBlocks[i], 16);
1599 Blocks[0][ALLOC] = 1;
1600 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1601 Blocks[1][ALLOC] = 1;
1602 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1603 // Debug print
1604 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1605 num_blocks = 2;
1606 // Handle following blocks
1607 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1608 if(j==n) j=0;
1609 if(j==i) break;
1610 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1611 Blocks[ind2][ALLOC] = 1;
1612 }
1613 break;
1614 }
1615 }
1616 }
1617 }
1618 else {
1619 for(i=0; i<n; i++) { // Look for identical block in known blocks
1620 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1621 for(j=0; j<max_blocks; j++) {
1622 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1623 // Found an identical block
1624 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1625 if(ind2 < 0)
1626 ind2 = max_blocks;
1627 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1628 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1629 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1630 Blocks[ind2][ALLOC] = 1;
1631 num_blocks++;
1632 if(num_blocks == max_blocks) goto end;
1633 }
1634 }
1635 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1636 if(ind2 > max_blocks)
1637 ind2 = 0;
1638 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1639 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1640 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1641 Blocks[ind2][ALLOC] = 1;
1642 num_blocks++;
1643 if(num_blocks == max_blocks) goto end;
1644 }
1645 }
1646 }
1647 }
1648 }
1649 }
1650 }
1651 tries++;
1652 if (BUTTON_PRESS()) return;
1653 } while (num_blocks != max_blocks);
1654 end:
1655 Dbprintf("-----------------------------------------");
1656 Dbprintf("Memory content:");
1657 Dbprintf("-----------------------------------------");
1658 for(i=0; i<max_blocks; i++) {
1659 if(Blocks[i][ALLOC]==1)
1660 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1661 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1662 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1663 else
1664 Dbprintf("<missing block %d>", i);
1665 }
1666 Dbprintf("-----------------------------------------");
1667
1668 return ;
1669 }
1670
1671
1672 //-----------------------------------
1673 // EM4469 / EM4305 routines
1674 //-----------------------------------
1675 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1676 #define FWD_CMD_WRITE 0xA
1677 #define FWD_CMD_READ 0x9
1678 #define FWD_CMD_DISABLE 0x5
1679
1680
1681 uint8_t forwardLink_data[64]; //array of forwarded bits
1682 uint8_t * forward_ptr; //ptr for forward message preparation
1683 uint8_t fwd_bit_sz; //forwardlink bit counter
1684 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1685
1686 //====================================================================
1687 // prepares command bits
1688 // see EM4469 spec
1689 //====================================================================
1690 //--------------------------------------------------------------------
1691 uint8_t Prepare_Cmd( uint8_t cmd ) {
1692 //--------------------------------------------------------------------
1693
1694 *forward_ptr++ = 0; //start bit
1695 *forward_ptr++ = 0; //second pause for 4050 code
1696
1697 *forward_ptr++ = cmd;
1698 cmd >>= 1;
1699 *forward_ptr++ = cmd;
1700 cmd >>= 1;
1701 *forward_ptr++ = cmd;
1702 cmd >>= 1;
1703 *forward_ptr++ = cmd;
1704
1705 return 6; //return number of emited bits
1706 }
1707
1708 //====================================================================
1709 // prepares address bits
1710 // see EM4469 spec
1711 //====================================================================
1712
1713 //--------------------------------------------------------------------
1714 uint8_t Prepare_Addr( uint8_t addr ) {
1715 //--------------------------------------------------------------------
1716
1717 register uint8_t line_parity;
1718
1719 uint8_t i;
1720 line_parity = 0;
1721 for(i=0;i<6;i++) {
1722 *forward_ptr++ = addr;
1723 line_parity ^= addr;
1724 addr >>= 1;
1725 }
1726
1727 *forward_ptr++ = (line_parity & 1);
1728
1729 return 7; //return number of emited bits
1730 }
1731
1732 //====================================================================
1733 // prepares data bits intreleaved with parity bits
1734 // see EM4469 spec
1735 //====================================================================
1736
1737 //--------------------------------------------------------------------
1738 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1739 //--------------------------------------------------------------------
1740
1741 register uint8_t line_parity;
1742 register uint8_t column_parity;
1743 register uint8_t i, j;
1744 register uint16_t data;
1745
1746 data = data_low;
1747 column_parity = 0;
1748
1749 for(i=0; i<4; i++) {
1750 line_parity = 0;
1751 for(j=0; j<8; j++) {
1752 line_parity ^= data;
1753 column_parity ^= (data & 1) << j;
1754 *forward_ptr++ = data;
1755 data >>= 1;
1756 }
1757 *forward_ptr++ = line_parity;
1758 if(i == 1)
1759 data = data_hi;
1760 }
1761
1762 for(j=0; j<8; j++) {
1763 *forward_ptr++ = column_parity;
1764 column_parity >>= 1;
1765 }
1766 *forward_ptr = 0;
1767
1768 return 45; //return number of emited bits
1769 }
1770
1771 //====================================================================
1772 // Forward Link send function
1773 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1774 // fwd_bit_count set with number of bits to be sent
1775 //====================================================================
1776 void SendForward(uint8_t fwd_bit_count) {
1777
1778 fwd_write_ptr = forwardLink_data;
1779 fwd_bit_sz = fwd_bit_count;
1780
1781 LED_D_ON();
1782
1783 //Field on
1784 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1785 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1786 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1787
1788 // Give it a bit of time for the resonant antenna to settle.
1789 // And for the tag to fully power up
1790 SpinDelay(150);
1791
1792 // force 1st mod pulse (start gap must be longer for 4305)
1793 fwd_bit_sz--; //prepare next bit modulation
1794 fwd_write_ptr++;
1795 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1796 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1797 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1798 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1799 SpinDelayUs(16*8); //16 cycles on (8us each)
1800
1801 // now start writting
1802 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1803 if(((*fwd_write_ptr++) & 1) == 1)
1804 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1805 else {
1806 //These timings work for 4469/4269/4305 (with the 55*8 above)
1807 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1808 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1809 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1810 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1811 SpinDelayUs(9*8); //16 cycles on (8us each)
1812 }
1813 }
1814 }
1815
1816 void EM4xLogin(uint32_t Password) {
1817
1818 uint8_t fwd_bit_count;
1819
1820 forward_ptr = forwardLink_data;
1821 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1822 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1823
1824 SendForward(fwd_bit_count);
1825
1826 //Wait for command to complete
1827 SpinDelay(20);
1828
1829 }
1830
1831 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1832
1833 uint8_t fwd_bit_count;
1834 uint8_t *dest = (uint8_t *)BigBuf;
1835 int m=0, i=0;
1836
1837 //If password mode do login
1838 if (PwdMode == 1) EM4xLogin(Pwd);
1839
1840 forward_ptr = forwardLink_data;
1841 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1842 fwd_bit_count += Prepare_Addr( Address );
1843
1844 m = sizeof(BigBuf);
1845 // Clear destination buffer before sending the command
1846 memset(dest, 128, m);
1847 // Connect the A/D to the peak-detected low-frequency path.
1848 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1849 // Now set up the SSC to get the ADC samples that are now streaming at us.
1850 FpgaSetupSsc();
1851
1852 SendForward(fwd_bit_count);
1853
1854 // Now do the acquisition
1855 i = 0;
1856 for(;;) {
1857 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1858 AT91C_BASE_SSC->SSC_THR = 0x43;
1859 }
1860 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1861 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1862 i++;
1863 if (i >= m) break;
1864 }
1865 }
1866 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1867 LED_D_OFF();
1868 }
1869
1870 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1871
1872 uint8_t fwd_bit_count;
1873
1874 //If password mode do login
1875 if (PwdMode == 1) EM4xLogin(Pwd);
1876
1877 forward_ptr = forwardLink_data;
1878 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1879 fwd_bit_count += Prepare_Addr( Address );
1880 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1881
1882 SendForward(fwd_bit_count);
1883
1884 //Wait for write to complete
1885 SpinDelay(20);
1886 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1887 LED_D_OFF();
1888 }
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