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Merge pull request #175 from hiviah/master
[proxmark3-svn] / armsrc / iso14443b.c
1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, split Nov 2006
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // Routines to support ISO 14443B. This includes both the reader software and
9 // the `fake tag' modes.
10 //-----------------------------------------------------------------------------
11
12 #include "proxmark3.h"
13 #include "apps.h"
14 #include "util.h"
15 #include "string.h"
16
17 #include "iso14443crc.h"
18
19 #define RECEIVE_SAMPLES_TIMEOUT 2000
20 #define ISO14443B_DMA_BUFFER_SIZE 256
21
22 // PCB Block number for APDUs
23 static uint8_t pcb_blocknum = 0;
24
25 //=============================================================================
26 // An ISO 14443 Type B tag. We listen for commands from the reader, using
27 // a UART kind of thing that's implemented in software. When we get a
28 // frame (i.e., a group of bytes between SOF and EOF), we check the CRC.
29 // If it's good, then we can do something appropriate with it, and send
30 // a response.
31 //=============================================================================
32
33 //-----------------------------------------------------------------------------
34 // Code up a string of octets at layer 2 (including CRC, we don't generate
35 // that here) so that they can be transmitted to the reader. Doesn't transmit
36 // them yet, just leaves them ready to send in ToSend[].
37 //-----------------------------------------------------------------------------
38 static void CodeIso14443bAsTag(const uint8_t *cmd, int len)
39 {
40 int i;
41
42 ToSendReset();
43
44 // Transmit a burst of ones, as the initial thing that lets the
45 // reader get phase sync. This (TR1) must be > 80/fs, per spec,
46 // but tag that I've tried (a Paypass) exceeds that by a fair bit,
47 // so I will too.
48 for(i = 0; i < 20; i++) {
49 ToSendStuffBit(1);
50 ToSendStuffBit(1);
51 ToSendStuffBit(1);
52 ToSendStuffBit(1);
53 }
54
55 // Send SOF.
56 for(i = 0; i < 10; i++) {
57 ToSendStuffBit(0);
58 ToSendStuffBit(0);
59 ToSendStuffBit(0);
60 ToSendStuffBit(0);
61 }
62 for(i = 0; i < 2; i++) {
63 ToSendStuffBit(1);
64 ToSendStuffBit(1);
65 ToSendStuffBit(1);
66 ToSendStuffBit(1);
67 }
68
69 for(i = 0; i < len; i++) {
70 int j;
71 uint8_t b = cmd[i];
72
73 // Start bit
74 ToSendStuffBit(0);
75 ToSendStuffBit(0);
76 ToSendStuffBit(0);
77 ToSendStuffBit(0);
78
79 // Data bits
80 for(j = 0; j < 8; j++) {
81 if(b & 1) {
82 ToSendStuffBit(1);
83 ToSendStuffBit(1);
84 ToSendStuffBit(1);
85 ToSendStuffBit(1);
86 } else {
87 ToSendStuffBit(0);
88 ToSendStuffBit(0);
89 ToSendStuffBit(0);
90 ToSendStuffBit(0);
91 }
92 b >>= 1;
93 }
94
95 // Stop bit
96 ToSendStuffBit(1);
97 ToSendStuffBit(1);
98 ToSendStuffBit(1);
99 ToSendStuffBit(1);
100 }
101
102 // Send EOF.
103 for(i = 0; i < 10; i++) {
104 ToSendStuffBit(0);
105 ToSendStuffBit(0);
106 ToSendStuffBit(0);
107 ToSendStuffBit(0);
108 }
109 for(i = 0; i < 2; i++) {
110 ToSendStuffBit(1);
111 ToSendStuffBit(1);
112 ToSendStuffBit(1);
113 ToSendStuffBit(1);
114 }
115
116 // Convert from last byte pos to length
117 ToSendMax++;
118 }
119
120 //-----------------------------------------------------------------------------
121 // The software UART that receives commands from the reader, and its state
122 // variables.
123 //-----------------------------------------------------------------------------
124 static struct {
125 enum {
126 STATE_UNSYNCD,
127 STATE_GOT_FALLING_EDGE_OF_SOF,
128 STATE_AWAITING_START_BIT,
129 STATE_RECEIVING_DATA
130 } state;
131 uint16_t shiftReg;
132 int bitCnt;
133 int byteCnt;
134 int byteCntMax;
135 int posCnt;
136 uint8_t *output;
137 } Uart;
138
139 /* Receive & handle a bit coming from the reader.
140 *
141 * This function is called 4 times per bit (every 2 subcarrier cycles).
142 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 2,36us
143 *
144 * LED handling:
145 * LED A -> ON once we have received the SOF and are expecting the rest.
146 * LED A -> OFF once we have received EOF or are in error state or unsynced
147 *
148 * Returns: true if we received a EOF
149 * false if we are still waiting for some more
150 */
151 static RAMFUNC int Handle14443bUartBit(uint8_t bit)
152 {
153 switch(Uart.state) {
154 case STATE_UNSYNCD:
155 if(!bit) {
156 // we went low, so this could be the beginning
157 // of an SOF
158 Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
159 Uart.posCnt = 0;
160 Uart.bitCnt = 0;
161 }
162 break;
163
164 case STATE_GOT_FALLING_EDGE_OF_SOF:
165 Uart.posCnt++;
166 if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
167 if(bit) {
168 if(Uart.bitCnt > 9) {
169 // we've seen enough consecutive
170 // zeros that it's a valid SOF
171 Uart.posCnt = 0;
172 Uart.byteCnt = 0;
173 Uart.state = STATE_AWAITING_START_BIT;
174 LED_A_ON(); // Indicate we got a valid SOF
175 } else {
176 // didn't stay down long enough
177 // before going high, error
178 Uart.state = STATE_UNSYNCD;
179 }
180 } else {
181 // do nothing, keep waiting
182 }
183 Uart.bitCnt++;
184 }
185 if(Uart.posCnt >= 4) Uart.posCnt = 0;
186 if(Uart.bitCnt > 12) {
187 // Give up if we see too many zeros without
188 // a one, too.
189 LED_A_OFF();
190 Uart.state = STATE_UNSYNCD;
191 }
192 break;
193
194 case STATE_AWAITING_START_BIT:
195 Uart.posCnt++;
196 if(bit) {
197 if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
198 // stayed high for too long between
199 // characters, error
200 Uart.state = STATE_UNSYNCD;
201 }
202 } else {
203 // falling edge, this starts the data byte
204 Uart.posCnt = 0;
205 Uart.bitCnt = 0;
206 Uart.shiftReg = 0;
207 Uart.state = STATE_RECEIVING_DATA;
208 }
209 break;
210
211 case STATE_RECEIVING_DATA:
212 Uart.posCnt++;
213 if(Uart.posCnt == 2) {
214 // time to sample a bit
215 Uart.shiftReg >>= 1;
216 if(bit) {
217 Uart.shiftReg |= 0x200;
218 }
219 Uart.bitCnt++;
220 }
221 if(Uart.posCnt >= 4) {
222 Uart.posCnt = 0;
223 }
224 if(Uart.bitCnt == 10) {
225 if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
226 {
227 // this is a data byte, with correct
228 // start and stop bits
229 Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
230 Uart.byteCnt++;
231
232 if(Uart.byteCnt >= Uart.byteCntMax) {
233 // Buffer overflowed, give up
234 LED_A_OFF();
235 Uart.state = STATE_UNSYNCD;
236 } else {
237 // so get the next byte now
238 Uart.posCnt = 0;
239 Uart.state = STATE_AWAITING_START_BIT;
240 }
241 } else if (Uart.shiftReg == 0x000) {
242 // this is an EOF byte
243 LED_A_OFF(); // Finished receiving
244 Uart.state = STATE_UNSYNCD;
245 if (Uart.byteCnt != 0) {
246 return TRUE;
247 }
248 } else {
249 // this is an error
250 LED_A_OFF();
251 Uart.state = STATE_UNSYNCD;
252 }
253 }
254 break;
255
256 default:
257 LED_A_OFF();
258 Uart.state = STATE_UNSYNCD;
259 break;
260 }
261
262 return FALSE;
263 }
264
265
266 static void UartReset()
267 {
268 Uart.byteCntMax = MAX_FRAME_SIZE;
269 Uart.state = STATE_UNSYNCD;
270 Uart.byteCnt = 0;
271 Uart.bitCnt = 0;
272 }
273
274
275 static void UartInit(uint8_t *data)
276 {
277 Uart.output = data;
278 UartReset();
279 }
280
281
282 //-----------------------------------------------------------------------------
283 // Receive a command (from the reader to us, where we are the simulated tag),
284 // and store it in the given buffer, up to the given maximum length. Keeps
285 // spinning, waiting for a well-framed command, until either we get one
286 // (returns TRUE) or someone presses the pushbutton on the board (FALSE).
287 //
288 // Assume that we're called with the SSC (to the FPGA) and ADC path set
289 // correctly.
290 //-----------------------------------------------------------------------------
291 static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len)
292 {
293 // Set FPGA mode to "simulated ISO 14443B tag", no modulation (listen
294 // only, since we are receiving, not transmitting).
295 // Signal field is off with the appropriate LED
296 LED_D_OFF();
297 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
298
299 // Now run a `software UART' on the stream of incoming samples.
300 UartInit(received);
301
302 for(;;) {
303 WDT_HIT();
304
305 if(BUTTON_PRESS()) return FALSE;
306
307 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
308 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
309 for(uint8_t mask = 0x80; mask != 0x00; mask >>= 1) {
310 if(Handle14443bUartBit(b & mask)) {
311 *len = Uart.byteCnt;
312 return TRUE;
313 }
314 }
315 }
316 }
317
318 return FALSE;
319 }
320
321 //-----------------------------------------------------------------------------
322 // Main loop of simulated tag: receive commands from reader, decide what
323 // response to send, and send it.
324 //-----------------------------------------------------------------------------
325 void SimulateIso14443bTag(void)
326 {
327 // the only commands we understand is WUPB, AFI=0, Select All, N=1:
328 static const uint8_t cmd1[] = { 0x05, 0x00, 0x08, 0x39, 0x73 }; // WUPB
329 // ... and REQB, AFI=0, Normal Request, N=1:
330 static const uint8_t cmd2[] = { 0x05, 0x00, 0x00, 0x71, 0xFF }; // REQB
331 // ... and HLTB
332 static const uint8_t cmd3[] = { 0x50, 0xff, 0xff, 0xff, 0xff }; // HLTB
333 // ... and ATTRIB
334 static const uint8_t cmd4[] = { 0x1D, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; // ATTRIB
335
336 // ... and we always respond with ATQB, PUPI = 820de174, Application Data = 0x20381922,
337 // supports only 106kBit/s in both directions, max frame size = 32Bytes,
338 // supports ISO14443-4, FWI=8 (77ms), NAD supported, CID not supported:
339 static const uint8_t response1[] = {
340 0x50, 0x82, 0x0d, 0xe1, 0x74, 0x20, 0x38, 0x19, 0x22,
341 0x00, 0x21, 0x85, 0x5e, 0xd7
342 };
343 // response to HLTB and ATTRIB
344 static const uint8_t response2[] = {0x00, 0x78, 0xF0};
345
346
347 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
348
349 clear_trace();
350 set_tracing(TRUE);
351
352 const uint8_t *resp;
353 uint8_t *respCode;
354 uint16_t respLen, respCodeLen;
355
356 // allocate command receive buffer
357 BigBuf_free();
358 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
359
360 uint16_t len;
361 uint16_t cmdsRecvd = 0;
362
363 // prepare the (only one) tag answer:
364 CodeIso14443bAsTag(response1, sizeof(response1));
365 uint8_t *resp1Code = BigBuf_malloc(ToSendMax);
366 memcpy(resp1Code, ToSend, ToSendMax);
367 uint16_t resp1CodeLen = ToSendMax;
368
369 // prepare the (other) tag answer:
370 CodeIso14443bAsTag(response2, sizeof(response2));
371 uint8_t *resp2Code = BigBuf_malloc(ToSendMax);
372 memcpy(resp2Code, ToSend, ToSendMax);
373 uint16_t resp2CodeLen = ToSendMax;
374
375 // We need to listen to the high-frequency, peak-detected path.
376 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
377 FpgaSetupSsc();
378
379 cmdsRecvd = 0;
380
381 for(;;) {
382
383 if(!GetIso14443bCommandFromReader(receivedCmd, &len)) {
384 Dbprintf("button pressed, received %d commands", cmdsRecvd);
385 break;
386 }
387
388 if (tracing) {
389 uint8_t parity[MAX_PARITY_SIZE];
390 LogTrace(receivedCmd, len, 0, 0, parity, TRUE);
391 }
392
393 // Good, look at the command now.
394 if ( (len == sizeof(cmd1) && memcmp(receivedCmd, cmd1, len) == 0)
395 || (len == sizeof(cmd2) && memcmp(receivedCmd, cmd2, len) == 0) ) {
396 resp = response1;
397 respLen = sizeof(response1);
398 respCode = resp1Code;
399 respCodeLen = resp1CodeLen;
400 } else if ( (len == sizeof(cmd3) && receivedCmd[0] == cmd3[0])
401 || (len == sizeof(cmd4) && receivedCmd[0] == cmd4[0]) ) {
402 resp = response2;
403 respLen = sizeof(response2);
404 respCode = resp2Code;
405 respCodeLen = resp2CodeLen;
406 } else {
407 Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsRecvd);
408 // And print whether the CRC fails, just for good measure
409 uint8_t b1, b2;
410 if (len >= 3){ // if crc exists
411 ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);
412 if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1]) {
413 // Not so good, try again.
414 DbpString("+++CRC fail");
415
416 } else {
417 DbpString("CRC passes");
418 }
419 }
420 //get rid of compiler warning
421 respCodeLen = 0;
422 resp = response1;
423 respLen = 0;
424 respCode = resp1Code;
425 //don't crash at new command just wait and see if reader will send other new cmds.
426 //break;
427 }
428
429 cmdsRecvd++;
430
431 if(cmdsRecvd > 0x30) {
432 DbpString("many commands later...");
433 break;
434 }
435
436 if(respCodeLen <= 0) continue;
437
438 // Modulate BPSK
439 // Signal field is off with the appropriate LED
440 LED_D_OFF();
441 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
442 AT91C_BASE_SSC->SSC_THR = 0xff;
443 FpgaSetupSsc();
444
445 // Transmit the response.
446 uint16_t i = 0;
447 for(;;) {
448 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
449 uint8_t b = respCode[i];
450
451 AT91C_BASE_SSC->SSC_THR = b;
452
453 i++;
454 if(i > respCodeLen) {
455 break;
456 }
457 }
458 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
459 volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
460 (void)b;
461 }
462 }
463
464 // trace the response:
465 if (tracing) {
466 uint8_t parity[MAX_PARITY_SIZE];
467 LogTrace(resp, respLen, 0, 0, parity, FALSE);
468 }
469
470 }
471 }
472
473 //=============================================================================
474 // An ISO 14443 Type B reader. We take layer two commands, code them
475 // appropriately, and then send them to the tag. We then listen for the
476 // tag's response, which we leave in the buffer to be demodulated on the
477 // PC side.
478 //=============================================================================
479
480 static struct {
481 enum {
482 DEMOD_UNSYNCD,
483 DEMOD_PHASE_REF_TRAINING,
484 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
485 DEMOD_GOT_FALLING_EDGE_OF_SOF,
486 DEMOD_AWAITING_START_BIT,
487 DEMOD_RECEIVING_DATA
488 } state;
489 int bitCount;
490 int posCount;
491 int thisBit;
492 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
493 int metric;
494 int metricN;
495 */
496 uint16_t shiftReg;
497 uint8_t *output;
498 int len;
499 int sumI;
500 int sumQ;
501 } Demod;
502
503 /*
504 * Handles reception of a bit from the tag
505 *
506 * This function is called 2 times per bit (every 4 subcarrier cycles).
507 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 4,72us
508 *
509 * LED handling:
510 * LED C -> ON once we have received the SOF and are expecting the rest.
511 * LED C -> OFF once we have received EOF or are unsynced
512 *
513 * Returns: true if we received a EOF
514 * false if we are still waiting for some more
515 *
516 */
517 static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
518 {
519 int v;
520
521 // The soft decision on the bit uses an estimate of just the
522 // quadrant of the reference angle, not the exact angle.
523 #define MAKE_SOFT_DECISION() { \
524 if(Demod.sumI > 0) { \
525 v = ci; \
526 } else { \
527 v = -ci; \
528 } \
529 if(Demod.sumQ > 0) { \
530 v += cq; \
531 } else { \
532 v -= cq; \
533 } \
534 }
535
536 #define SUBCARRIER_DETECT_THRESHOLD 8
537
538 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by abs(ci) + abs(cq)
539 /* #define CHECK_FOR_SUBCARRIER() { \
540 v = ci; \
541 if(v < 0) v = -v; \
542 if(cq > 0) { \
543 v += cq; \
544 } else { \
545 v -= cq; \
546 } \
547 }
548 */
549 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
550 #define CHECK_FOR_SUBCARRIER() { \
551 if(ci < 0) { \
552 if(cq < 0) { /* ci < 0, cq < 0 */ \
553 if (cq < ci) { \
554 v = -cq - (ci >> 1); \
555 } else { \
556 v = -ci - (cq >> 1); \
557 } \
558 } else { /* ci < 0, cq >= 0 */ \
559 if (cq < -ci) { \
560 v = -ci + (cq >> 1); \
561 } else { \
562 v = cq - (ci >> 1); \
563 } \
564 } \
565 } else { \
566 if(cq < 0) { /* ci >= 0, cq < 0 */ \
567 if (-cq < ci) { \
568 v = ci - (cq >> 1); \
569 } else { \
570 v = -cq + (ci >> 1); \
571 } \
572 } else { /* ci >= 0, cq >= 0 */ \
573 if (cq < ci) { \
574 v = ci + (cq >> 1); \
575 } else { \
576 v = cq + (ci >> 1); \
577 } \
578 } \
579 } \
580 }
581
582 switch(Demod.state) {
583 case DEMOD_UNSYNCD:
584 CHECK_FOR_SUBCARRIER();
585 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
586 Demod.state = DEMOD_PHASE_REF_TRAINING;
587 Demod.sumI = ci;
588 Demod.sumQ = cq;
589 Demod.posCount = 1;
590 }
591 break;
592
593 case DEMOD_PHASE_REF_TRAINING:
594 if(Demod.posCount < 8) {
595 CHECK_FOR_SUBCARRIER();
596 if (v > SUBCARRIER_DETECT_THRESHOLD) {
597 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
598 // note: synchronization time > 80 1/fs
599 Demod.sumI += ci;
600 Demod.sumQ += cq;
601 Demod.posCount++;
602 } else { // subcarrier lost
603 Demod.state = DEMOD_UNSYNCD;
604 }
605 } else {
606 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
607 }
608 break;
609
610 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
611 MAKE_SOFT_DECISION();
612 if(v < 0) { // logic '0' detected
613 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
614 Demod.posCount = 0; // start of SOF sequence
615 } else {
616 if(Demod.posCount > 200/4) { // maximum length of TR1 = 200 1/fs
617 Demod.state = DEMOD_UNSYNCD;
618 }
619 }
620 Demod.posCount++;
621 break;
622
623 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
624 Demod.posCount++;
625 MAKE_SOFT_DECISION();
626 if(v > 0) {
627 if(Demod.posCount < 9*2) { // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
628 Demod.state = DEMOD_UNSYNCD;
629 } else {
630 LED_C_ON(); // Got SOF
631 Demod.state = DEMOD_AWAITING_START_BIT;
632 Demod.posCount = 0;
633 Demod.len = 0;
634 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
635 Demod.metricN = 0;
636 Demod.metric = 0;
637 */
638 }
639 } else {
640 if(Demod.posCount > 12*2) { // low phase of SOF too long (> 12 etu)
641 Demod.state = DEMOD_UNSYNCD;
642 LED_C_OFF();
643 }
644 }
645 break;
646
647 case DEMOD_AWAITING_START_BIT:
648 Demod.posCount++;
649 MAKE_SOFT_DECISION();
650 if(v > 0) {
651 if(Demod.posCount > 3*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
652 Demod.state = DEMOD_UNSYNCD;
653 LED_C_OFF();
654 }
655 } else { // start bit detected
656 Demod.bitCount = 0;
657 Demod.posCount = 1; // this was the first half
658 Demod.thisBit = v;
659 Demod.shiftReg = 0;
660 Demod.state = DEMOD_RECEIVING_DATA;
661 }
662 break;
663
664 case DEMOD_RECEIVING_DATA:
665 MAKE_SOFT_DECISION();
666 if(Demod.posCount == 0) { // first half of bit
667 Demod.thisBit = v;
668 Demod.posCount = 1;
669 } else { // second half of bit
670 Demod.thisBit += v;
671
672 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
673 if(Demod.thisBit > 0) {
674 Demod.metric += Demod.thisBit;
675 } else {
676 Demod.metric -= Demod.thisBit;
677 }
678 (Demod.metricN)++;
679 */
680
681 Demod.shiftReg >>= 1;
682 if(Demod.thisBit > 0) { // logic '1'
683 Demod.shiftReg |= 0x200;
684 }
685
686 Demod.bitCount++;
687 if(Demod.bitCount == 10) {
688 uint16_t s = Demod.shiftReg;
689 if((s & 0x200) && !(s & 0x001)) { // stop bit == '1', start bit == '0'
690 uint8_t b = (s >> 1);
691 Demod.output[Demod.len] = b;
692 Demod.len++;
693 Demod.state = DEMOD_AWAITING_START_BIT;
694 } else {
695 Demod.state = DEMOD_UNSYNCD;
696 LED_C_OFF();
697 if(s == 0x000) {
698 // This is EOF (start, stop and all data bits == '0'
699 return TRUE;
700 }
701 }
702 }
703 Demod.posCount = 0;
704 }
705 break;
706
707 default:
708 Demod.state = DEMOD_UNSYNCD;
709 LED_C_OFF();
710 break;
711 }
712
713 return FALSE;
714 }
715
716
717 static void DemodReset()
718 {
719 // Clear out the state of the "UART" that receives from the tag.
720 Demod.len = 0;
721 Demod.state = DEMOD_UNSYNCD;
722 Demod.posCount = 0;
723 memset(Demod.output, 0x00, MAX_FRAME_SIZE);
724 }
725
726
727 static void DemodInit(uint8_t *data)
728 {
729 Demod.output = data;
730 DemodReset();
731 }
732
733
734 /*
735 * Demodulate the samples we received from the tag, also log to tracebuffer
736 * quiet: set to 'TRUE' to disable debug output
737 */
738 static void GetSamplesFor14443bDemod(int n, bool quiet)
739 {
740 int max = 0;
741 bool gotFrame = FALSE;
742 int lastRxCounter, ci, cq, samples = 0;
743
744 // Allocate memory from BigBuf for some buffers
745 // free all previous allocations first
746 BigBuf_free();
747
748 // The response (tag -> reader) that we're receiving.
749 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
750
751 // The DMA buffer, used to stream samples from the FPGA
752 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
753
754 // Set up the demodulator for tag -> reader responses.
755 DemodInit(receivedResponse);
756
757 // Setup and start DMA.
758 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
759
760 int8_t *upTo = dmaBuf;
761 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
762
763 // Signal field is ON with the appropriate LED:
764 LED_D_ON();
765 // And put the FPGA in the appropriate mode
766 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
767
768 for(;;) {
769 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
770 if(behindBy > max) max = behindBy;
771
772 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO14443B_DMA_BUFFER_SIZE-1)) > 2) {
773 ci = upTo[0];
774 cq = upTo[1];
775 upTo += 2;
776 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
777 upTo = dmaBuf;
778 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
779 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
780 }
781 lastRxCounter -= 2;
782 if(lastRxCounter <= 0) {
783 lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
784 }
785
786 samples += 2;
787
788 if(Handle14443bSamplesDemod(ci, cq)) {
789 gotFrame = TRUE;
790 break;
791 }
792 }
793
794 if(samples > n || gotFrame) {
795 break;
796 }
797 }
798
799 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
800
801 if (!quiet) Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d", max, samples, gotFrame, Demod.len, Demod.sumI, Demod.sumQ);
802 //Tracing
803 if (tracing && Demod.len > 0) {
804 uint8_t parity[MAX_PARITY_SIZE];
805 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
806 }
807 }
808
809
810 //-----------------------------------------------------------------------------
811 // Transmit the command (to the tag) that was placed in ToSend[].
812 //-----------------------------------------------------------------------------
813 static void TransmitFor14443b(void)
814 {
815 int c;
816
817 FpgaSetupSsc();
818
819 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
820 AT91C_BASE_SSC->SSC_THR = 0xff;
821 }
822
823 // Signal field is ON with the appropriate Red LED
824 LED_D_ON();
825 // Signal we are transmitting with the Green LED
826 LED_B_ON();
827 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
828
829 for(c = 0; c < 10;) {
830 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
831 AT91C_BASE_SSC->SSC_THR = 0xff;
832 c++;
833 }
834 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
835 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
836 (void)r;
837 }
838 WDT_HIT();
839 }
840
841 c = 0;
842 for(;;) {
843 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
844 AT91C_BASE_SSC->SSC_THR = ToSend[c];
845 c++;
846 if(c >= ToSendMax) {
847 break;
848 }
849 }
850 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
851 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
852 (void)r;
853 }
854 WDT_HIT();
855 }
856 LED_B_OFF(); // Finished sending
857 }
858
859
860 //-----------------------------------------------------------------------------
861 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
862 // so that it is ready to transmit to the tag using TransmitFor14443b().
863 //-----------------------------------------------------------------------------
864 static void CodeIso14443bAsReader(const uint8_t *cmd, int len)
865 {
866 int i, j;
867 uint8_t b;
868
869 ToSendReset();
870
871 // Establish initial reference level
872 for(i = 0; i < 40; i++) {
873 ToSendStuffBit(1);
874 }
875 // Send SOF
876 for(i = 0; i < 10; i++) {
877 ToSendStuffBit(0);
878 }
879
880 for(i = 0; i < len; i++) {
881 // Stop bits/EGT
882 ToSendStuffBit(1);
883 ToSendStuffBit(1);
884 // Start bit
885 ToSendStuffBit(0);
886 // Data bits
887 b = cmd[i];
888 for(j = 0; j < 8; j++) {
889 if(b & 1) {
890 ToSendStuffBit(1);
891 } else {
892 ToSendStuffBit(0);
893 }
894 b >>= 1;
895 }
896 }
897 // Send EOF
898 ToSendStuffBit(1);
899 for(i = 0; i < 10; i++) {
900 ToSendStuffBit(0);
901 }
902 for(i = 0; i < 8; i++) {
903 ToSendStuffBit(1);
904 }
905
906 // And then a little more, to make sure that the last character makes
907 // it out before we switch to rx mode.
908 for(i = 0; i < 24; i++) {
909 ToSendStuffBit(1);
910 }
911
912 // Convert from last character reference to length
913 ToSendMax++;
914 }
915
916
917 /**
918 Convenience function to encode, transmit and trace iso 14443b comms
919 **/
920 static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len)
921 {
922 CodeIso14443bAsReader(cmd, len);
923 TransmitFor14443b();
924 if (tracing) {
925 uint8_t parity[MAX_PARITY_SIZE];
926 LogTrace(cmd,len, 0, 0, parity, TRUE);
927 }
928 }
929
930 /* Sends an APDU to the tag
931 * TODO: check CRC and preamble
932 */
933 int iso14443b_apdu(uint8_t const *message, size_t message_length, uint8_t *response)
934 {
935 uint8_t message_frame[message_length + 4];
936 // PCB
937 message_frame[0] = 0x0A | pcb_blocknum;
938 pcb_blocknum ^= 1;
939 // CID
940 message_frame[1] = 0;
941 // INF
942 memcpy(message_frame + 2, message, message_length);
943 // EDC (CRC)
944 ComputeCrc14443(CRC_14443_B, message_frame, message_length + 2, &message_frame[message_length + 2], &message_frame[message_length + 3]);
945 // send
946 CodeAndTransmit14443bAsReader(message_frame, message_length + 4);
947 // get response
948 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT*100, TRUE);
949 if(Demod.len < 3)
950 {
951 return 0;
952 }
953 // TODO: Check CRC
954 // copy response contents
955 if(response != NULL)
956 {
957 memcpy(response, Demod.output, Demod.len);
958 }
959 return Demod.len;
960 }
961
962 /* Perform the ISO 14443 B Card Selection procedure
963 * Currently does NOT do any collision handling.
964 * It expects 0-1 cards in the device's range.
965 * TODO: Support multiple cards (perform anticollision)
966 * TODO: Verify CRC checksums
967 */
968 int iso14443b_select_card()
969 {
970 // WUPB command (including CRC)
971 // Note: WUPB wakes up all tags, REQB doesn't wake up tags in HALT state
972 static const uint8_t wupb[] = { 0x05, 0x00, 0x08, 0x39, 0x73 };
973 // ATTRIB command (with space for CRC)
974 uint8_t attrib[] = { 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00};
975
976 // first, wake up the tag
977 CodeAndTransmit14443bAsReader(wupb, sizeof(wupb));
978 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
979 // ATQB too short?
980 if (Demod.len < 14)
981 {
982 return 2;
983 }
984
985 // select the tag
986 // copy the PUPI to ATTRIB
987 memcpy(attrib + 1, Demod.output + 1, 4);
988 /* copy the protocol info from ATQB (Protocol Info -> Protocol_Type) into
989 ATTRIB (Param 3) */
990 attrib[7] = Demod.output[10] & 0x0F;
991 ComputeCrc14443(CRC_14443_B, attrib, 9, attrib + 9, attrib + 10);
992 CodeAndTransmit14443bAsReader(attrib, sizeof(attrib));
993 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
994 // Answer to ATTRIB too short?
995 if(Demod.len < 3)
996 {
997 return 2;
998 }
999 // reset PCB block number
1000 pcb_blocknum = 0;
1001 return 1;
1002 }
1003
1004 // Set up ISO 14443 Type B communication (similar to iso14443a_setup)
1005 void iso14443b_setup() {
1006 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1007 // Set up the synchronous serial port
1008 FpgaSetupSsc();
1009 // connect Demodulated Signal to ADC:
1010 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1011
1012 // Signal field is on with the appropriate LED
1013 LED_D_ON();
1014 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1015
1016 // Start the timer
1017 StartCountSspClk();
1018
1019 DemodReset();
1020 UartReset();
1021 }
1022
1023 //-----------------------------------------------------------------------------
1024 // Read a SRI512 ISO 14443B tag.
1025 //
1026 // SRI512 tags are just simple memory tags, here we're looking at making a dump
1027 // of the contents of the memory. No anticollision algorithm is done, we assume
1028 // we have a single tag in the field.
1029 //
1030 // I tried to be systematic and check every answer of the tag, every CRC, etc...
1031 //-----------------------------------------------------------------------------
1032 void ReadSTMemoryIso14443b(uint32_t dwLast)
1033 {
1034 uint8_t i = 0x00;
1035
1036 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1037 // Make sure that we start from off, since the tags are stateful;
1038 // confusing things will happen if we don't reset them between reads.
1039 LED_D_OFF();
1040 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1041 SpinDelay(200);
1042
1043 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1044 FpgaSetupSsc();
1045
1046 // Now give it time to spin up.
1047 // Signal field is on with the appropriate LED
1048 LED_D_ON();
1049 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
1050 SpinDelay(200);
1051
1052 clear_trace();
1053 set_tracing(TRUE);
1054
1055 // First command: wake up the tag using the INITIATE command
1056 uint8_t cmd1[] = {0x06, 0x00, 0x97, 0x5b};
1057 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1058 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1059
1060 if (Demod.len == 0) {
1061 DbpString("No response from tag");
1062 return;
1063 } else {
1064 Dbprintf("Randomly generated Chip ID (+ 2 byte CRC): %02x %02x %02x",
1065 Demod.output[0], Demod.output[1], Demod.output[2]);
1066 }
1067
1068 // There is a response, SELECT the uid
1069 DbpString("Now SELECT tag:");
1070 cmd1[0] = 0x0E; // 0x0E is SELECT
1071 cmd1[1] = Demod.output[0];
1072 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1073 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1074 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1075 if (Demod.len != 3) {
1076 Dbprintf("Expected 3 bytes from tag, got %d", Demod.len);
1077 return;
1078 }
1079 // Check the CRC of the answer:
1080 ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]);
1081 if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) {
1082 DbpString("CRC Error reading select response.");
1083 return;
1084 }
1085 // Check response from the tag: should be the same UID as the command we just sent:
1086 if (cmd1[1] != Demod.output[0]) {
1087 Dbprintf("Bad response to SELECT from Tag, aborting: %02x %02x", cmd1[1], Demod.output[0]);
1088 return;
1089 }
1090
1091 // Tag is now selected,
1092 // First get the tag's UID:
1093 cmd1[0] = 0x0B;
1094 ComputeCrc14443(CRC_14443_B, cmd1, 1 , &cmd1[1], &cmd1[2]);
1095 CodeAndTransmit14443bAsReader(cmd1, 3); // Only first three bytes for this one
1096 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1097 if (Demod.len != 10) {
1098 Dbprintf("Expected 10 bytes from tag, got %d", Demod.len);
1099 return;
1100 }
1101 // The check the CRC of the answer (use cmd1 as temporary variable):
1102 ComputeCrc14443(CRC_14443_B, Demod.output, 8, &cmd1[2], &cmd1[3]);
1103 if(cmd1[2] != Demod.output[8] || cmd1[3] != Demod.output[9]) {
1104 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1105 (cmd1[2]<<8)+cmd1[3], (Demod.output[8]<<8)+Demod.output[9]);
1106 // Do not return;, let's go on... (we should retry, maybe ?)
1107 }
1108 Dbprintf("Tag UID (64 bits): %08x %08x",
1109 (Demod.output[7]<<24) + (Demod.output[6]<<16) + (Demod.output[5]<<8) + Demod.output[4],
1110 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0]);
1111
1112 // Now loop to read all 16 blocks, address from 0 to last block
1113 Dbprintf("Tag memory dump, block 0 to %d", dwLast);
1114 cmd1[0] = 0x08;
1115 i = 0x00;
1116 dwLast++;
1117 for (;;) {
1118 if (i == dwLast) {
1119 DbpString("System area block (0xff):");
1120 i = 0xff;
1121 }
1122 cmd1[1] = i;
1123 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1124 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1125 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1126 if (Demod.len != 6) { // Check if we got an answer from the tag
1127 DbpString("Expected 6 bytes from tag, got less...");
1128 return;
1129 }
1130 // The check the CRC of the answer (use cmd1 as temporary variable):
1131 ComputeCrc14443(CRC_14443_B, Demod.output, 4, &cmd1[2], &cmd1[3]);
1132 if(cmd1[2] != Demod.output[4] || cmd1[3] != Demod.output[5]) {
1133 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1134 (cmd1[2]<<8)+cmd1[3], (Demod.output[4]<<8)+Demod.output[5]);
1135 // Do not return;, let's go on... (we should retry, maybe ?)
1136 }
1137 // Now print out the memory location:
1138 Dbprintf("Address=%02x, Contents=%08x, CRC=%04x", i,
1139 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0],
1140 (Demod.output[4]<<8)+Demod.output[5]);
1141 if (i == 0xff) {
1142 break;
1143 }
1144 i++;
1145 }
1146 }
1147
1148
1149 //=============================================================================
1150 // Finally, the `sniffer' combines elements from both the reader and
1151 // simulated tag, to show both sides of the conversation.
1152 //=============================================================================
1153
1154 //-----------------------------------------------------------------------------
1155 // Record the sequence of commands sent by the reader to the tag, with
1156 // triggering so that we start recording at the point that the tag is moved
1157 // near the reader.
1158 //-----------------------------------------------------------------------------
1159 /*
1160 * Memory usage for this function, (within BigBuf)
1161 * Last Received command (reader->tag) - MAX_FRAME_SIZE
1162 * Last Received command (tag->reader) - MAX_FRAME_SIZE
1163 * DMA Buffer - ISO14443B_DMA_BUFFER_SIZE
1164 * Demodulated samples received - all the rest
1165 */
1166 void RAMFUNC SnoopIso14443b(void)
1167 {
1168 // We won't start recording the frames that we acquire until we trigger;
1169 // a good trigger condition to get started is probably when we see a
1170 // response from the tag.
1171 int triggered = TRUE; // TODO: set and evaluate trigger condition
1172
1173 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1174 BigBuf_free();
1175
1176 clear_trace();
1177 set_tracing(TRUE);
1178
1179 // The DMA buffer, used to stream samples from the FPGA
1180 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
1181 int lastRxCounter;
1182 int8_t *upTo;
1183 int ci, cq;
1184 int maxBehindBy = 0;
1185
1186 // Count of samples received so far, so that we can include timing
1187 // information in the trace buffer.
1188 int samples = 0;
1189
1190 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1191 UartInit(BigBuf_malloc(MAX_FRAME_SIZE));
1192
1193 // Print some debug information about the buffer sizes
1194 Dbprintf("Snooping buffers initialized:");
1195 Dbprintf(" Trace: %i bytes", BigBuf_max_traceLen());
1196 Dbprintf(" Reader -> tag: %i bytes", MAX_FRAME_SIZE);
1197 Dbprintf(" tag -> Reader: %i bytes", MAX_FRAME_SIZE);
1198 Dbprintf(" DMA: %i bytes", ISO14443B_DMA_BUFFER_SIZE);
1199
1200 // Signal field is off, no reader signal, no tag signal
1201 LEDsoff();
1202
1203 // And put the FPGA in the appropriate mode
1204 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP);
1205 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1206
1207 // Setup for the DMA.
1208 FpgaSetupSsc();
1209 upTo = dmaBuf;
1210 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
1211 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
1212 uint8_t parity[MAX_PARITY_SIZE];
1213
1214 bool TagIsActive = FALSE;
1215 bool ReaderIsActive = FALSE;
1216
1217 // And now we loop, receiving samples.
1218 for(;;) {
1219 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) &
1220 (ISO14443B_DMA_BUFFER_SIZE-1);
1221 if(behindBy > maxBehindBy) {
1222 maxBehindBy = behindBy;
1223 }
1224
1225 if(behindBy < 2) continue;
1226
1227 ci = upTo[0];
1228 cq = upTo[1];
1229 upTo += 2;
1230 lastRxCounter -= 2;
1231 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
1232 upTo = dmaBuf;
1233 lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
1234 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
1235 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
1236 WDT_HIT();
1237 if(behindBy > (9*ISO14443B_DMA_BUFFER_SIZE/10)) { // TODO: understand whether we can increase/decrease as we want or not?
1238 Dbprintf("blew circular buffer! behindBy=%d", behindBy);
1239 break;
1240 }
1241 if(!tracing) {
1242 DbpString("Reached trace limit");
1243 break;
1244 }
1245 if(BUTTON_PRESS()) {
1246 DbpString("cancelled");
1247 break;
1248 }
1249 }
1250
1251 samples += 2;
1252
1253 if (!TagIsActive) { // no need to try decoding reader data if the tag is sending
1254 if(Handle14443bUartBit(ci & 0x01)) {
1255 if(triggered && tracing) {
1256 LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
1257 }
1258 /* And ready to receive another command. */
1259 UartReset();
1260 /* And also reset the demod code, which might have been */
1261 /* false-triggered by the commands from the reader. */
1262 DemodReset();
1263 }
1264 if(Handle14443bUartBit(cq & 0x01)) {
1265 if(triggered && tracing) {
1266 LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
1267 }
1268 /* And ready to receive another command. */
1269 UartReset();
1270 /* And also reset the demod code, which might have been */
1271 /* false-triggered by the commands from the reader. */
1272 DemodReset();
1273 }
1274 ReaderIsActive = (Uart.state > STATE_GOT_FALLING_EDGE_OF_SOF);
1275 }
1276
1277 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
1278 if(Handle14443bSamplesDemod(ci | 0x01, cq | 0x01)) {
1279
1280 //Use samples as a time measurement
1281 if(tracing)
1282 {
1283 uint8_t parity[MAX_PARITY_SIZE];
1284 LogTrace(Demod.output, Demod.len, samples, samples, parity, FALSE);
1285 }
1286 triggered = TRUE;
1287
1288 // And ready to receive another response.
1289 DemodReset();
1290 }
1291 TagIsActive = (Demod.state > DEMOD_GOT_FALLING_EDGE_OF_SOF);
1292 }
1293
1294 }
1295
1296 FpgaDisableSscDma();
1297 LEDsoff();
1298 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
1299 DbpString("Snoop statistics:");
1300 Dbprintf(" Max behind by: %i", maxBehindBy);
1301 Dbprintf(" Uart State: %x", Uart.state);
1302 Dbprintf(" Uart ByteCnt: %i", Uart.byteCnt);
1303 Dbprintf(" Uart ByteCntMax: %i", Uart.byteCntMax);
1304 Dbprintf(" Trace length: %i", BigBuf_get_traceLen());
1305 }
1306
1307
1308 /*
1309 * Send raw command to tag ISO14443B
1310 * @Input
1311 * datalen len of buffer data
1312 * recv bool when true wait for data from tag and send to client
1313 * powerfield bool leave the field on when true
1314 * data buffer with byte to send
1315 *
1316 * @Output
1317 * none
1318 *
1319 */
1320 void SendRawCommand14443B(uint32_t datalen, uint32_t recv, uint8_t powerfield, uint8_t data[])
1321 {
1322 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1323 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1324 FpgaSetupSsc();
1325
1326 if (datalen){
1327 set_tracing(TRUE);
1328
1329 CodeAndTransmit14443bAsReader(data, datalen);
1330
1331 if(recv) {
1332 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1333 uint16_t iLen = MIN(Demod.len, USB_CMD_DATA_SIZE);
1334 cmd_send(CMD_ACK, iLen, 0, 0, Demod.output, iLen);
1335 }
1336 }
1337
1338 if(!powerfield) {
1339 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1340 LED_D_OFF();
1341 }
1342 }
1343
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