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mf 1k sim reader attack cleanup
[proxmark3-svn] / armsrc / iso14443a.c
1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12
13 #include "proxmark3.h"
14 #include "apps.h"
15 #include "util.h"
16 #include "string.h"
17 #include "cmd.h"
18 #include "iso14443crc.h"
19 #include "iso14443a.h"
20 #include "crapto1.h"
21 #include "mifareutil.h"
22 #include "BigBuf.h"
23 #include "protocols.h"
24
25 static uint32_t iso14a_timeout;
26 int rsamples = 0;
27 uint8_t trigger = 0;
28 // the block number for the ISO14443-4 PCB
29 static uint8_t iso14_pcb_blocknum = 0;
30
31 //
32 // ISO14443 timing:
33 //
34 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
35 #define REQUEST_GUARD_TIME (7000/16 + 1)
36 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
37 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
38 // bool LastCommandWasRequest = FALSE;
39
40 //
41 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
42 //
43 // When the PM acts as reader and is receiving tag data, it takes
44 // 3 ticks delay in the AD converter
45 // 16 ticks until the modulation detector completes and sets curbit
46 // 8 ticks until bit_to_arm is assigned from curbit
47 // 8*16 ticks for the transfer from FPGA to ARM
48 // 4*16 ticks until we measure the time
49 // - 8*16 ticks because we measure the time of the previous transfer
50 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
51
52 // When the PM acts as a reader and is sending, it takes
53 // 4*16 ticks until we can write data to the sending hold register
54 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
55 // 8 ticks until the first transfer starts
56 // 8 ticks later the FPGA samples the data
57 // 1 tick to assign mod_sig_coil
58 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
59
60 // When the PM acts as tag and is receiving it takes
61 // 2 ticks delay in the RF part (for the first falling edge),
62 // 3 ticks for the A/D conversion,
63 // 8 ticks on average until the start of the SSC transfer,
64 // 8 ticks until the SSC samples the first data
65 // 7*16 ticks to complete the transfer from FPGA to ARM
66 // 8 ticks until the next ssp_clk rising edge
67 // 4*16 ticks until we measure the time
68 // - 8*16 ticks because we measure the time of the previous transfer
69 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
70
71 // The FPGA will report its internal sending delay in
72 uint16_t FpgaSendQueueDelay;
73 // the 5 first bits are the number of bits buffered in mod_sig_buf
74 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
75 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
76
77 // When the PM acts as tag and is sending, it takes
78 // 4*16 ticks until we can write data to the sending hold register
79 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
80 // 8 ticks until the first transfer starts
81 // 8 ticks later the FPGA samples the data
82 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
83 // + 1 tick to assign mod_sig_coil
84 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
85
86 // When the PM acts as sniffer and is receiving tag data, it takes
87 // 3 ticks A/D conversion
88 // 14 ticks to complete the modulation detection
89 // 8 ticks (on average) until the result is stored in to_arm
90 // + the delays in transferring data - which is the same for
91 // sniffing reader and tag data and therefore not relevant
92 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
93
94 // When the PM acts as sniffer and is receiving reader data, it takes
95 // 2 ticks delay in analogue RF receiver (for the falling edge of the
96 // start bit, which marks the start of the communication)
97 // 3 ticks A/D conversion
98 // 8 ticks on average until the data is stored in to_arm.
99 // + the delays in transferring data - which is the same for
100 // sniffing reader and tag data and therefore not relevant
101 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
102
103 //variables used for timing purposes:
104 //these are in ssp_clk cycles:
105 static uint32_t NextTransferTime;
106 static uint32_t LastTimeProxToAirStart;
107 static uint32_t LastProxToAirDuration;
108
109
110
111 // CARD TO READER - manchester
112 // Sequence D: 11110000 modulation with subcarrier during first half
113 // Sequence E: 00001111 modulation with subcarrier during second half
114 // Sequence F: 00000000 no modulation with subcarrier
115 // READER TO CARD - miller
116 // Sequence X: 00001100 drop after half a period
117 // Sequence Y: 00000000 no drop
118 // Sequence Z: 11000000 drop at start
119 #define SEC_D 0xf0
120 #define SEC_E 0x0f
121 #define SEC_F 0x00
122 #define SEC_X 0x0c
123 #define SEC_Y 0x00
124 #define SEC_Z 0xc0
125
126 const uint8_t OddByteParity[256] = {
127 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
128 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
129 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
130 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
131 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
132 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
133 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
134 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
135 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
136 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
137 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
138 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
139 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
140 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
141 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
142 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
143 };
144
145
146 void iso14a_set_trigger(bool enable) {
147 trigger = enable;
148 }
149
150
151 void iso14a_set_timeout(uint32_t timeout) {
152 iso14a_timeout = timeout;
153 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
154 }
155
156
157 void iso14a_set_ATS_timeout(uint8_t *ats) {
158
159 uint8_t tb1;
160 uint8_t fwi;
161 uint32_t fwt;
162
163 if (ats[0] > 1) { // there is a format byte T0
164 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
165 if ((ats[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
166 tb1 = ats[3];
167 } else {
168 tb1 = ats[2];
169 }
170 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
171 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
172
173 iso14a_set_timeout(fwt/(8*16));
174 }
175 }
176 }
177
178
179 //-----------------------------------------------------------------------------
180 // Generate the parity value for a byte sequence
181 //
182 //-----------------------------------------------------------------------------
183 byte_t oddparity (const byte_t bt)
184 {
185 return OddByteParity[bt];
186 }
187
188 void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
189 {
190 uint16_t paritybit_cnt = 0;
191 uint16_t paritybyte_cnt = 0;
192 uint8_t parityBits = 0;
193
194 for (uint16_t i = 0; i < iLen; i++) {
195 // Generate the parity bits
196 parityBits |= ((OddByteParity[pbtCmd[i]]) << (7-paritybit_cnt));
197 if (paritybit_cnt == 7) {
198 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
199 parityBits = 0; // and advance to next Parity Byte
200 paritybyte_cnt++;
201 paritybit_cnt = 0;
202 } else {
203 paritybit_cnt++;
204 }
205 }
206
207 // save remaining parity bits
208 par[paritybyte_cnt] = parityBits;
209
210 }
211
212 void AppendCrc14443a(uint8_t* data, int len)
213 {
214 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
215 }
216
217 void AppendCrc14443b(uint8_t* data, int len)
218 {
219 ComputeCrc14443(CRC_14443_B,data,len,data+len,data+len+1);
220 }
221
222
223 //=============================================================================
224 // ISO 14443 Type A - Miller decoder
225 //=============================================================================
226 // Basics:
227 // This decoder is used when the PM3 acts as a tag.
228 // The reader will generate "pauses" by temporarily switching of the field.
229 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
230 // The FPGA does a comparison with a threshold and would deliver e.g.:
231 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
232 // The Miller decoder needs to identify the following sequences:
233 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
234 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
235 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
236 // Note 1: the bitstream may start at any time. We therefore need to sync.
237 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
238 //-----------------------------------------------------------------------------
239 static tUart Uart;
240
241 // Lookup-Table to decide if 4 raw bits are a modulation.
242 // We accept the following:
243 // 0001 - a 3 tick wide pause
244 // 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
245 // 0111 - a 2 tick wide pause shifted left
246 // 1001 - a 2 tick wide pause shifted right
247 const bool Mod_Miller_LUT[] = {
248 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
249 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
250 };
251 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
252 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
253
254 void UartReset()
255 {
256 Uart.state = STATE_UNSYNCD;
257 Uart.bitCount = 0;
258 Uart.len = 0; // number of decoded data bytes
259 Uart.parityLen = 0; // number of decoded parity bytes
260 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
261 Uart.parityBits = 0; // holds 8 parity bits
262 Uart.startTime = 0;
263 Uart.endTime = 0;
264 }
265
266 void UartInit(uint8_t *data, uint8_t *parity)
267 {
268 Uart.output = data;
269 Uart.parity = parity;
270 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
271 UartReset();
272 }
273
274 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
275 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
276 {
277
278 Uart.fourBits = (Uart.fourBits << 8) | bit;
279
280 if (Uart.state == STATE_UNSYNCD) { // not yet synced
281
282 Uart.syncBit = 9999; // not set
283 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
284 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
285 // we therefore look for a ...xx11111111111100x11111xxxxxx... pattern
286 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
287 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00000111 11111111 11101111 10000000
288 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00000111 11111111 10001111 10000000
289 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
290 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
291 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
292 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
293 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
294 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
295 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
296 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
297
298 if (Uart.syncBit != 9999) { // found a sync bit
299 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
300 Uart.startTime -= Uart.syncBit;
301 Uart.endTime = Uart.startTime;
302 Uart.state = STATE_START_OF_COMMUNICATION;
303 }
304
305 } else {
306
307 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
308 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
309 UartReset();
310 } else { // Modulation in first half = Sequence Z = logic "0"
311 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
312 UartReset();
313 } else {
314 Uart.bitCount++;
315 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
316 Uart.state = STATE_MILLER_Z;
317 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
318 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
319 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
320 Uart.parityBits <<= 1; // make room for the parity bit
321 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
322 Uart.bitCount = 0;
323 Uart.shiftReg = 0;
324 if((Uart.len&0x0007) == 0) { // every 8 data bytes
325 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
326 Uart.parityBits = 0;
327 }
328 }
329 }
330 }
331 } else {
332 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
333 Uart.bitCount++;
334 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
335 Uart.state = STATE_MILLER_X;
336 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
337 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
338 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
339 Uart.parityBits <<= 1; // make room for the new parity bit
340 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
341 Uart.bitCount = 0;
342 Uart.shiftReg = 0;
343 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
344 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
345 Uart.parityBits = 0;
346 }
347 }
348 } else { // no modulation in both halves - Sequence Y
349 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
350 Uart.state = STATE_UNSYNCD;
351 Uart.bitCount--; // last "0" was part of EOC sequence
352 Uart.shiftReg <<= 1; // drop it
353 if(Uart.bitCount > 0) { // if we decoded some bits
354 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
355 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
356 Uart.parityBits <<= 1; // add a (void) parity bit
357 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
358 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
359 return TRUE;
360 } else if (Uart.len & 0x0007) { // there are some parity bits to store
361 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
362 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
363 }
364 if (Uart.len) {
365 return TRUE; // we are finished with decoding the raw data sequence
366 } else {
367 UartReset(); // Nothing received - start over
368 }
369 }
370 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
371 UartReset();
372 } else { // a logic "0"
373 Uart.bitCount++;
374 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
375 Uart.state = STATE_MILLER_Y;
376 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
377 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
378 Uart.parityBits <<= 1; // make room for the parity bit
379 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
380 Uart.bitCount = 0;
381 Uart.shiftReg = 0;
382 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
383 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
384 Uart.parityBits = 0;
385 }
386 }
387 }
388 }
389 }
390
391 }
392
393 return FALSE; // not finished yet, need more data
394 }
395
396
397
398 //=============================================================================
399 // ISO 14443 Type A - Manchester decoder
400 //=============================================================================
401 // Basics:
402 // This decoder is used when the PM3 acts as a reader.
403 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
404 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
405 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
406 // The Manchester decoder needs to identify the following sequences:
407 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
408 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
409 // 8 ticks unmodulated: Sequence F = end of communication
410 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
411 // Note 1: the bitstream may start at any time. We therefore need to sync.
412 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
413 static tDemod Demod;
414
415 // Lookup-Table to decide if 4 raw bits are a modulation.
416 // We accept three or four "1" in any position
417 const bool Mod_Manchester_LUT[] = {
418 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
419 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
420 };
421
422 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
423 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
424
425
426 void DemodReset()
427 {
428 Demod.state = DEMOD_UNSYNCD;
429 Demod.len = 0; // number of decoded data bytes
430 Demod.parityLen = 0;
431 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
432 Demod.parityBits = 0; //
433 Demod.collisionPos = 0; // Position of collision bit
434 Demod.twoBits = 0xffff; // buffer for 2 Bits
435 Demod.highCnt = 0;
436 Demod.startTime = 0;
437 Demod.endTime = 0;
438 }
439
440 void DemodInit(uint8_t *data, uint8_t *parity)
441 {
442 Demod.output = data;
443 Demod.parity = parity;
444 DemodReset();
445 }
446
447 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
448 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
449 {
450
451 Demod.twoBits = (Demod.twoBits << 8) | bit;
452
453 if (Demod.state == DEMOD_UNSYNCD) {
454
455 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
456 if (Demod.twoBits == 0x0000) {
457 Demod.highCnt++;
458 } else {
459 Demod.highCnt = 0;
460 }
461 } else {
462 Demod.syncBit = 0xFFFF; // not set
463 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
464 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
465 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
466 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
467 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
468 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
469 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
470 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
471 if (Demod.syncBit != 0xFFFF) {
472 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
473 Demod.startTime -= Demod.syncBit;
474 Demod.bitCount = offset; // number of decoded data bits
475 Demod.state = DEMOD_MANCHESTER_DATA;
476 }
477 }
478
479 } else {
480
481 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
482 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
483 if (!Demod.collisionPos) {
484 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
485 }
486 } // modulation in first half only - Sequence D = 1
487 Demod.bitCount++;
488 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
489 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
490 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
491 Demod.parityBits <<= 1; // make room for the parity bit
492 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
493 Demod.bitCount = 0;
494 Demod.shiftReg = 0;
495 if((Demod.len&0x0007) == 0) { // every 8 data bytes
496 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
497 Demod.parityBits = 0;
498 }
499 }
500 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
501 } else { // no modulation in first half
502 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
503 Demod.bitCount++;
504 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
505 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
506 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
507 Demod.parityBits <<= 1; // make room for the new parity bit
508 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
509 Demod.bitCount = 0;
510 Demod.shiftReg = 0;
511 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
512 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
513 Demod.parityBits = 0;
514 }
515 }
516 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
517 } else { // no modulation in both halves - End of communication
518 if(Demod.bitCount > 0) { // there are some remaining data bits
519 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
520 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
521 Demod.parityBits <<= 1; // add a (void) parity bit
522 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
523 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
524 return TRUE;
525 } else if (Demod.len & 0x0007) { // there are some parity bits to store
526 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
527 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
528 }
529 if (Demod.len) {
530 return TRUE; // we are finished with decoding the raw data sequence
531 } else { // nothing received. Start over
532 DemodReset();
533 }
534 }
535 }
536
537 }
538
539 return FALSE; // not finished yet, need more data
540 }
541
542 //=============================================================================
543 // Finally, a `sniffer' for ISO 14443 Type A
544 // Both sides of communication!
545 //=============================================================================
546
547 //-----------------------------------------------------------------------------
548 // Record the sequence of commands sent by the reader to the tag, with
549 // triggering so that we start recording at the point that the tag is moved
550 // near the reader.
551 //-----------------------------------------------------------------------------
552 void RAMFUNC SnoopIso14443a(uint8_t param) {
553 // param:
554 // bit 0 - trigger from first card answer
555 // bit 1 - trigger from first reader 7-bit request
556
557 LEDsoff();
558
559 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
560
561 // Allocate memory from BigBuf for some buffers
562 // free all previous allocations first
563 BigBuf_free();
564
565 // The command (reader -> tag) that we're receiving.
566 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
567 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
568
569 // The response (tag -> reader) that we're receiving.
570 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
571 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
572
573 // The DMA buffer, used to stream samples from the FPGA
574 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
575
576 // init trace buffer
577 clear_trace();
578 set_tracing(TRUE);
579
580 uint8_t *data = dmaBuf;
581 uint8_t previous_data = 0;
582 int maxDataLen = 0;
583 int dataLen = 0;
584 bool TagIsActive = FALSE;
585 bool ReaderIsActive = FALSE;
586
587 // Set up the demodulator for tag -> reader responses.
588 DemodInit(receivedResponse, receivedResponsePar);
589
590 // Set up the demodulator for the reader -> tag commands
591 UartInit(receivedCmd, receivedCmdPar);
592
593 // Setup and start DMA.
594 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
595
596 // We won't start recording the frames that we acquire until we trigger;
597 // a good trigger condition to get started is probably when we see a
598 // response from the tag.
599 // triggered == FALSE -- to wait first for card
600 bool triggered = !(param & 0x03);
601
602 // And now we loop, receiving samples.
603 for(uint32_t rsamples = 0; TRUE; ) {
604
605 if(BUTTON_PRESS()) {
606 DbpString("cancelled by button");
607 break;
608 }
609
610 LED_A_ON();
611 WDT_HIT();
612
613 int register readBufDataP = data - dmaBuf;
614 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
615 if (readBufDataP <= dmaBufDataP){
616 dataLen = dmaBufDataP - readBufDataP;
617 } else {
618 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
619 }
620 // test for length of buffer
621 if(dataLen > maxDataLen) {
622 maxDataLen = dataLen;
623 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
624 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
625 break;
626 }
627 }
628 if(dataLen < 1) continue;
629
630 // primary buffer was stopped( <-- we lost data!
631 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
632 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
633 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
634 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
635 }
636 // secondary buffer sets as primary, secondary buffer was stopped
637 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
638 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
639 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
640 }
641
642 LED_A_OFF();
643
644 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
645
646 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
647 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
648 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
649 LED_C_ON();
650
651 // check - if there is a short 7bit request from reader
652 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
653
654 if(triggered) {
655 if (!LogTrace(receivedCmd,
656 Uart.len,
657 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
658 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
659 Uart.parity,
660 TRUE)) break;
661 }
662 /* And ready to receive another command. */
663 UartReset();
664 /* And also reset the demod code, which might have been */
665 /* false-triggered by the commands from the reader. */
666 DemodReset();
667 LED_B_OFF();
668 }
669 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
670 }
671
672 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
673 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
674 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
675 LED_B_ON();
676
677 if (!LogTrace(receivedResponse,
678 Demod.len,
679 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
680 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
681 Demod.parity,
682 FALSE)) break;
683
684 if ((!triggered) && (param & 0x01)) triggered = TRUE;
685
686 // And ready to receive another response.
687 DemodReset();
688 // And reset the Miller decoder including itS (now outdated) input buffer
689 UartInit(receivedCmd, receivedCmdPar);
690
691 LED_C_OFF();
692 }
693 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
694 }
695 }
696
697 previous_data = *data;
698 rsamples++;
699 data++;
700 if(data == dmaBuf + DMA_BUFFER_SIZE) {
701 data = dmaBuf;
702 }
703 } // main cycle
704
705 DbpString("COMMAND FINISHED");
706
707 FpgaDisableSscDma();
708 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
709 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
710 LEDsoff();
711 }
712
713 //-----------------------------------------------------------------------------
714 // Prepare tag messages
715 //-----------------------------------------------------------------------------
716 static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
717 {
718 ToSendReset();
719
720 // Correction bit, might be removed when not needed
721 ToSendStuffBit(0);
722 ToSendStuffBit(0);
723 ToSendStuffBit(0);
724 ToSendStuffBit(0);
725 ToSendStuffBit(1); // 1
726 ToSendStuffBit(0);
727 ToSendStuffBit(0);
728 ToSendStuffBit(0);
729
730 // Send startbit
731 ToSend[++ToSendMax] = SEC_D;
732 LastProxToAirDuration = 8 * ToSendMax - 4;
733
734 for(uint16_t i = 0; i < len; i++) {
735 uint8_t b = cmd[i];
736
737 // Data bits
738 for(uint16_t j = 0; j < 8; j++) {
739 if(b & 1) {
740 ToSend[++ToSendMax] = SEC_D;
741 } else {
742 ToSend[++ToSendMax] = SEC_E;
743 }
744 b >>= 1;
745 }
746
747 // Get the parity bit
748 if (parity[i>>3] & (0x80>>(i&0x0007))) {
749 ToSend[++ToSendMax] = SEC_D;
750 LastProxToAirDuration = 8 * ToSendMax - 4;
751 } else {
752 ToSend[++ToSendMax] = SEC_E;
753 LastProxToAirDuration = 8 * ToSendMax;
754 }
755 }
756
757 // Send stopbit
758 ToSend[++ToSendMax] = SEC_F;
759
760 // Convert from last byte pos to length
761 ToSendMax++;
762 }
763
764 static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
765 {
766 uint8_t par[MAX_PARITY_SIZE];
767
768 GetParity(cmd, len, par);
769 CodeIso14443aAsTagPar(cmd, len, par);
770 }
771
772
773 static void Code4bitAnswerAsTag(uint8_t cmd)
774 {
775 int i;
776
777 ToSendReset();
778
779 // Correction bit, might be removed when not needed
780 ToSendStuffBit(0);
781 ToSendStuffBit(0);
782 ToSendStuffBit(0);
783 ToSendStuffBit(0);
784 ToSendStuffBit(1); // 1
785 ToSendStuffBit(0);
786 ToSendStuffBit(0);
787 ToSendStuffBit(0);
788
789 // Send startbit
790 ToSend[++ToSendMax] = SEC_D;
791
792 uint8_t b = cmd;
793 for(i = 0; i < 4; i++) {
794 if(b & 1) {
795 ToSend[++ToSendMax] = SEC_D;
796 LastProxToAirDuration = 8 * ToSendMax - 4;
797 } else {
798 ToSend[++ToSendMax] = SEC_E;
799 LastProxToAirDuration = 8 * ToSendMax;
800 }
801 b >>= 1;
802 }
803
804 // Send stopbit
805 ToSend[++ToSendMax] = SEC_F;
806
807 // Convert from last byte pos to length
808 ToSendMax++;
809 }
810
811 //-----------------------------------------------------------------------------
812 // Wait for commands from reader
813 // Stop when button is pressed
814 // Or return TRUE when command is captured
815 //-----------------------------------------------------------------------------
816 static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
817 {
818 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
819 // only, since we are receiving, not transmitting).
820 // Signal field is off with the appropriate LED
821 LED_D_OFF();
822 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
823
824 // Now run a `software UART' on the stream of incoming samples.
825 UartInit(received, parity);
826
827 // clear RXRDY:
828 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
829
830 for(;;) {
831 WDT_HIT();
832
833 if(BUTTON_PRESS()) return FALSE;
834
835 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
836 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
837 if(MillerDecoding(b, 0)) {
838 *len = Uart.len;
839 return TRUE;
840 }
841 }
842 }
843 }
844
845 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
846 int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
847 int EmSend4bit(uint8_t resp);
848 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
849 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
850 int EmSendCmd(uint8_t *resp, uint16_t respLen);
851 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
852 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
853 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
854
855 static uint8_t* free_buffer_pointer;
856
857 typedef struct {
858 uint8_t* response;
859 size_t response_n;
860 uint8_t* modulation;
861 size_t modulation_n;
862 uint32_t ProxToAirDuration;
863 } tag_response_info_t;
864
865 bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
866 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
867 // This will need the following byte array for a modulation sequence
868 // 144 data bits (18 * 8)
869 // 18 parity bits
870 // 2 Start and stop
871 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
872 // 1 just for the case
873 // ----------- +
874 // 166 bytes, since every bit that needs to be send costs us a byte
875 //
876
877
878 // Prepare the tag modulation bits from the message
879 CodeIso14443aAsTag(response_info->response,response_info->response_n);
880
881 // Make sure we do not exceed the free buffer space
882 if (ToSendMax > max_buffer_size) {
883 Dbprintf("Out of memory, when modulating bits for tag answer:");
884 Dbhexdump(response_info->response_n,response_info->response,false);
885 return false;
886 }
887
888 // Copy the byte array, used for this modulation to the buffer position
889 memcpy(response_info->modulation,ToSend,ToSendMax);
890
891 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
892 response_info->modulation_n = ToSendMax;
893 response_info->ProxToAirDuration = LastProxToAirDuration;
894
895 return true;
896 }
897
898
899 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
900 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
901 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
902 // -> need 273 bytes buffer
903 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
904
905 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
906 // Retrieve and store the current buffer index
907 response_info->modulation = free_buffer_pointer;
908
909 // Determine the maximum size we can use from our buffer
910 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
911
912 // Forward the prepare tag modulation function to the inner function
913 if (prepare_tag_modulation(response_info, max_buffer_size)) {
914 // Update the free buffer offset
915 free_buffer_pointer += ToSendMax;
916 return true;
917 } else {
918 return false;
919 }
920 }
921
922 //-----------------------------------------------------------------------------
923 // Main loop of simulated tag: receive commands from reader, decide what
924 // response to send, and send it.
925 //-----------------------------------------------------------------------------
926 void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
927 {
928 uint8_t sak;
929
930 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
931 uint8_t response1[2];
932
933 switch (tagType) {
934 case 1: { // MIFARE Classic
935 // Says: I am Mifare 1k - original line
936 response1[0] = 0x04;
937 response1[1] = 0x00;
938 sak = 0x08;
939 } break;
940 case 2: { // MIFARE Ultralight
941 // Says: I am a stupid memory tag, no crypto
942 response1[0] = 0x04;
943 response1[1] = 0x00;
944 sak = 0x00;
945 } break;
946 case 3: { // MIFARE DESFire
947 // Says: I am a DESFire tag, ph33r me
948 response1[0] = 0x04;
949 response1[1] = 0x03;
950 sak = 0x20;
951 } break;
952 case 4: { // ISO/IEC 14443-4
953 // Says: I am a javacard (JCOP)
954 response1[0] = 0x04;
955 response1[1] = 0x00;
956 sak = 0x28;
957 } break;
958 case 5: { // MIFARE TNP3XXX
959 // Says: I am a toy
960 response1[0] = 0x01;
961 response1[1] = 0x0f;
962 sak = 0x01;
963 } break;
964 default: {
965 Dbprintf("Error: unkown tagtype (%d)",tagType);
966 return;
967 } break;
968 }
969
970 // The second response contains the (mandatory) first 24 bits of the UID
971 uint8_t response2[5] = {0x00};
972
973 // Check if the uid uses the (optional) part
974 uint8_t response2a[5] = {0x00};
975
976 if (uid_2nd) {
977 response2[0] = 0x88;
978 num_to_bytes(uid_1st,3,response2+1);
979 num_to_bytes(uid_2nd,4,response2a);
980 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
981
982 // Configure the ATQA and SAK accordingly
983 response1[0] |= 0x40;
984 sak |= 0x04;
985 } else {
986 num_to_bytes(uid_1st,4,response2);
987 // Configure the ATQA and SAK accordingly
988 response1[0] &= 0xBF;
989 sak &= 0xFB;
990 }
991
992 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
993 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
994
995 // Prepare the mandatory SAK (for 4 and 7 byte UID)
996 uint8_t response3[3] = {0x00};
997 response3[0] = sak;
998 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
999
1000 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
1001 uint8_t response3a[3] = {0x00};
1002 response3a[0] = sak & 0xFB;
1003 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
1004
1005 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
1006 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1007 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1008 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1009 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1010 // TC(1) = 0x02: CID supported, NAD not supported
1011 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1012
1013 #define TAG_RESPONSE_COUNT 7
1014 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1015 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1016 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1017 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1018 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1019 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1020 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1021 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1022 };
1023
1024 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1025 // Such a response is less time critical, so we can prepare them on the fly
1026 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1027 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1028 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1029 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1030 tag_response_info_t dynamic_response_info = {
1031 .response = dynamic_response_buffer,
1032 .response_n = 0,
1033 .modulation = dynamic_modulation_buffer,
1034 .modulation_n = 0
1035 };
1036
1037 // We need to listen to the high-frequency, peak-detected path.
1038 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1039
1040 BigBuf_free_keep_EM();
1041
1042 // allocate buffers:
1043 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1044 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1045 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1046
1047 // clear trace
1048 clear_trace();
1049 set_tracing(TRUE);
1050
1051 // Prepare the responses of the anticollision phase
1052 // there will be not enough time to do this at the moment the reader sends it REQA
1053 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1054 prepare_allocated_tag_modulation(&responses[i]);
1055 }
1056
1057 int len = 0;
1058
1059 // To control where we are in the protocol
1060 int order = 0;
1061 int lastorder;
1062
1063 // Just to allow some checks
1064 int happened = 0;
1065 int happened2 = 0;
1066 int cmdsRecvd = 0;
1067
1068 cmdsRecvd = 0;
1069 tag_response_info_t* p_response;
1070
1071 LED_A_ON();
1072 for(;;) {
1073 // Clean receive command buffer
1074 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
1075 DbpString("Button press");
1076 break;
1077 }
1078
1079 p_response = NULL;
1080
1081 // Okay, look at the command now.
1082 lastorder = order;
1083 if(receivedCmd[0] == 0x26) { // Received a REQUEST
1084 p_response = &responses[0]; order = 1;
1085 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
1086 p_response = &responses[0]; order = 6;
1087 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
1088 p_response = &responses[1]; order = 2;
1089 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
1090 p_response = &responses[2]; order = 20;
1091 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
1092 p_response = &responses[3]; order = 3;
1093 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
1094 p_response = &responses[4]; order = 30;
1095 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
1096 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
1097 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1098 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1099 p_response = NULL;
1100 } else if(receivedCmd[0] == 0x50) { // Received a HALT
1101
1102 if (tracing) {
1103 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1104 }
1105 p_response = NULL;
1106 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
1107 p_response = &responses[5]; order = 7;
1108 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
1109 if (tagType == 1 || tagType == 2) { // RATS not supported
1110 EmSend4bit(CARD_NACK_NA);
1111 p_response = NULL;
1112 } else {
1113 p_response = &responses[6]; order = 70;
1114 }
1115 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
1116 if (tracing) {
1117 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1118 }
1119 uint32_t nr = bytes_to_num(receivedCmd,4);
1120 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1121 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1122 } else {
1123 // Check for ISO 14443A-4 compliant commands, look at left nibble
1124 switch (receivedCmd[0]) {
1125
1126 case 0x0B:
1127 case 0x0A: { // IBlock (command)
1128 dynamic_response_info.response[0] = receivedCmd[0];
1129 dynamic_response_info.response[1] = 0x00;
1130 dynamic_response_info.response[2] = 0x90;
1131 dynamic_response_info.response[3] = 0x00;
1132 dynamic_response_info.response_n = 4;
1133 } break;
1134
1135 case 0x1A:
1136 case 0x1B: { // Chaining command
1137 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1138 dynamic_response_info.response_n = 2;
1139 } break;
1140
1141 case 0xaa:
1142 case 0xbb: {
1143 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1144 dynamic_response_info.response_n = 2;
1145 } break;
1146
1147 case 0xBA: { //
1148 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1149 dynamic_response_info.response_n = 2;
1150 } break;
1151
1152 case 0xCA:
1153 case 0xC2: { // Readers sends deselect command
1154 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1155 dynamic_response_info.response_n = 2;
1156 } break;
1157
1158 default: {
1159 // Never seen this command before
1160 if (tracing) {
1161 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1162 }
1163 Dbprintf("Received unknown command (len=%d):",len);
1164 Dbhexdump(len,receivedCmd,false);
1165 // Do not respond
1166 dynamic_response_info.response_n = 0;
1167 } break;
1168 }
1169
1170 if (dynamic_response_info.response_n > 0) {
1171 // Copy the CID from the reader query
1172 dynamic_response_info.response[1] = receivedCmd[1];
1173
1174 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1175 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1176 dynamic_response_info.response_n += 2;
1177
1178 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1179 Dbprintf("Error preparing tag response");
1180 if (tracing) {
1181 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1182 }
1183 break;
1184 }
1185 p_response = &dynamic_response_info;
1186 }
1187 }
1188
1189 // Count number of wakeups received after a halt
1190 if(order == 6 && lastorder == 5) { happened++; }
1191
1192 // Count number of other messages after a halt
1193 if(order != 6 && lastorder == 5) { happened2++; }
1194
1195 if(cmdsRecvd > 999) {
1196 DbpString("1000 commands later...");
1197 break;
1198 }
1199 cmdsRecvd++;
1200
1201 if (p_response != NULL) {
1202 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1203 // do the tracing for the previous reader request and this tag answer:
1204 uint8_t par[MAX_PARITY_SIZE];
1205 GetParity(p_response->response, p_response->response_n, par);
1206
1207 EmLogTrace(Uart.output,
1208 Uart.len,
1209 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1210 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1211 Uart.parity,
1212 p_response->response,
1213 p_response->response_n,
1214 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1215 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1216 par);
1217 }
1218
1219 if (!tracing) {
1220 Dbprintf("Trace Full. Simulation stopped.");
1221 break;
1222 }
1223 }
1224
1225 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1226 LED_A_OFF();
1227 BigBuf_free_keep_EM();
1228 }
1229
1230
1231 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1232 // of bits specified in the delay parameter.
1233 void PrepareDelayedTransfer(uint16_t delay)
1234 {
1235 uint8_t bitmask = 0;
1236 uint8_t bits_to_shift = 0;
1237 uint8_t bits_shifted = 0;
1238
1239 delay &= 0x07;
1240 if (delay) {
1241 for (uint16_t i = 0; i < delay; i++) {
1242 bitmask |= (0x01 << i);
1243 }
1244 ToSend[ToSendMax++] = 0x00;
1245 for (uint16_t i = 0; i < ToSendMax; i++) {
1246 bits_to_shift = ToSend[i] & bitmask;
1247 ToSend[i] = ToSend[i] >> delay;
1248 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1249 bits_shifted = bits_to_shift;
1250 }
1251 }
1252 }
1253
1254
1255 //-------------------------------------------------------------------------------------
1256 // Transmit the command (to the tag) that was placed in ToSend[].
1257 // Parameter timing:
1258 // if NULL: transfer at next possible time, taking into account
1259 // request guard time and frame delay time
1260 // if == 0: transfer immediately and return time of transfer
1261 // if != 0: delay transfer until time specified
1262 //-------------------------------------------------------------------------------------
1263 static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
1264 {
1265
1266 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1267
1268 uint32_t ThisTransferTime = 0;
1269
1270 if (timing) {
1271 if(*timing == 0) { // Measure time
1272 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1273 } else {
1274 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1275 }
1276 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1277 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1278 LastTimeProxToAirStart = *timing;
1279 } else {
1280 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1281 while(GetCountSspClk() < ThisTransferTime);
1282 LastTimeProxToAirStart = ThisTransferTime;
1283 }
1284
1285 // clear TXRDY
1286 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1287
1288 uint16_t c = 0;
1289 for(;;) {
1290 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1291 AT91C_BASE_SSC->SSC_THR = cmd[c];
1292 c++;
1293 if(c >= len) {
1294 break;
1295 }
1296 }
1297 }
1298
1299 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1300 }
1301
1302
1303 //-----------------------------------------------------------------------------
1304 // Prepare reader command (in bits, support short frames) to send to FPGA
1305 //-----------------------------------------------------------------------------
1306 void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
1307 {
1308 int i, j;
1309 int last;
1310 uint8_t b;
1311
1312 ToSendReset();
1313
1314 // Start of Communication (Seq. Z)
1315 ToSend[++ToSendMax] = SEC_Z;
1316 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1317 last = 0;
1318
1319 size_t bytecount = nbytes(bits);
1320 // Generate send structure for the data bits
1321 for (i = 0; i < bytecount; i++) {
1322 // Get the current byte to send
1323 b = cmd[i];
1324 size_t bitsleft = MIN((bits-(i*8)),8);
1325
1326 for (j = 0; j < bitsleft; j++) {
1327 if (b & 1) {
1328 // Sequence X
1329 ToSend[++ToSendMax] = SEC_X;
1330 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1331 last = 1;
1332 } else {
1333 if (last == 0) {
1334 // Sequence Z
1335 ToSend[++ToSendMax] = SEC_Z;
1336 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1337 } else {
1338 // Sequence Y
1339 ToSend[++ToSendMax] = SEC_Y;
1340 last = 0;
1341 }
1342 }
1343 b >>= 1;
1344 }
1345
1346 // Only transmit parity bit if we transmitted a complete byte
1347 if (j == 8 && parity != NULL) {
1348 // Get the parity bit
1349 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
1350 // Sequence X
1351 ToSend[++ToSendMax] = SEC_X;
1352 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1353 last = 1;
1354 } else {
1355 if (last == 0) {
1356 // Sequence Z
1357 ToSend[++ToSendMax] = SEC_Z;
1358 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1359 } else {
1360 // Sequence Y
1361 ToSend[++ToSendMax] = SEC_Y;
1362 last = 0;
1363 }
1364 }
1365 }
1366 }
1367
1368 // End of Communication: Logic 0 followed by Sequence Y
1369 if (last == 0) {
1370 // Sequence Z
1371 ToSend[++ToSendMax] = SEC_Z;
1372 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1373 } else {
1374 // Sequence Y
1375 ToSend[++ToSendMax] = SEC_Y;
1376 last = 0;
1377 }
1378 ToSend[++ToSendMax] = SEC_Y;
1379
1380 // Convert to length of command:
1381 ToSendMax++;
1382 }
1383
1384 //-----------------------------------------------------------------------------
1385 // Prepare reader command to send to FPGA
1386 //-----------------------------------------------------------------------------
1387 void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
1388 {
1389 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
1390 }
1391
1392
1393 //-----------------------------------------------------------------------------
1394 // Wait for commands from reader
1395 // Stop when button is pressed (return 1) or field was gone (return 2)
1396 // Or return 0 when command is captured
1397 //-----------------------------------------------------------------------------
1398 static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
1399 {
1400 *len = 0;
1401
1402 uint32_t timer = 0, vtime = 0;
1403 int analogCnt = 0;
1404 int analogAVG = 0;
1405
1406 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1407 // only, since we are receiving, not transmitting).
1408 // Signal field is off with the appropriate LED
1409 LED_D_OFF();
1410 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1411
1412 // Set ADC to read field strength
1413 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1414 AT91C_BASE_ADC->ADC_MR =
1415 ADC_MODE_PRESCALE(63) |
1416 ADC_MODE_STARTUP_TIME(1) |
1417 ADC_MODE_SAMPLE_HOLD_TIME(15);
1418 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1419 // start ADC
1420 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1421
1422 // Now run a 'software UART' on the stream of incoming samples.
1423 UartInit(received, parity);
1424
1425 // Clear RXRDY:
1426 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1427
1428 for(;;) {
1429 WDT_HIT();
1430
1431 if (BUTTON_PRESS()) return 1;
1432
1433 // test if the field exists
1434 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1435 analogCnt++;
1436 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1437 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1438 if (analogCnt >= 32) {
1439 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1440 vtime = GetTickCount();
1441 if (!timer) timer = vtime;
1442 // 50ms no field --> card to idle state
1443 if (vtime - timer > 50) return 2;
1444 } else
1445 if (timer) timer = 0;
1446 analogCnt = 0;
1447 analogAVG = 0;
1448 }
1449 }
1450
1451 // receive and test the miller decoding
1452 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1453 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1454 if(MillerDecoding(b, 0)) {
1455 *len = Uart.len;
1456 return 0;
1457 }
1458 }
1459
1460 }
1461 }
1462
1463
1464 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
1465 {
1466 uint8_t b;
1467 uint16_t i = 0;
1468 uint32_t ThisTransferTime;
1469
1470 // Modulate Manchester
1471 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1472
1473 // include correction bit if necessary
1474 if (Uart.parityBits & 0x01) {
1475 correctionNeeded = TRUE;
1476 }
1477 if(correctionNeeded) {
1478 // 1236, so correction bit needed
1479 i = 0;
1480 } else {
1481 i = 1;
1482 }
1483
1484 // clear receiving shift register and holding register
1485 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1486 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1487 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1488 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1489
1490 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1491 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1492 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1493 if (AT91C_BASE_SSC->SSC_RHR) break;
1494 }
1495
1496 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1497
1498 // Clear TXRDY:
1499 AT91C_BASE_SSC->SSC_THR = SEC_F;
1500
1501 // send cycle
1502 for(; i < respLen; ) {
1503 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1504 AT91C_BASE_SSC->SSC_THR = resp[i++];
1505 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1506 }
1507
1508 if(BUTTON_PRESS()) {
1509 break;
1510 }
1511 }
1512
1513 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1514 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
1515 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
1516 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1517 AT91C_BASE_SSC->SSC_THR = SEC_F;
1518 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1519 i++;
1520 }
1521 }
1522
1523 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1524
1525 return 0;
1526 }
1527
1528 int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1529 Code4bitAnswerAsTag(resp);
1530 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1531 // do the tracing for the previous reader request and this tag answer:
1532 uint8_t par[1];
1533 GetParity(&resp, 1, par);
1534 EmLogTrace(Uart.output,
1535 Uart.len,
1536 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1537 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1538 Uart.parity,
1539 &resp,
1540 1,
1541 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1542 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1543 par);
1544 return res;
1545 }
1546
1547 int EmSend4bit(uint8_t resp){
1548 return EmSend4bitEx(resp, false);
1549 }
1550
1551 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
1552 CodeIso14443aAsTagPar(resp, respLen, par);
1553 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1554 // do the tracing for the previous reader request and this tag answer:
1555 EmLogTrace(Uart.output,
1556 Uart.len,
1557 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1558 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1559 Uart.parity,
1560 resp,
1561 respLen,
1562 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1563 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1564 par);
1565 return res;
1566 }
1567
1568 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1569 uint8_t par[MAX_PARITY_SIZE];
1570 GetParity(resp, respLen, par);
1571 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
1572 }
1573
1574 int EmSendCmd(uint8_t *resp, uint16_t respLen){
1575 uint8_t par[MAX_PARITY_SIZE];
1576 GetParity(resp, respLen, par);
1577 return EmSendCmdExPar(resp, respLen, false, par);
1578 }
1579
1580 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
1581 return EmSendCmdExPar(resp, respLen, false, par);
1582 }
1583
1584 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1585 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
1586 {
1587 if (tracing) {
1588 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1589 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1590 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1591 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1592 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1593 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1594 reader_EndTime = tag_StartTime - exact_fdt;
1595 reader_StartTime = reader_EndTime - reader_modlen;
1596 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE)) {
1597 return FALSE;
1598 } else return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1599 } else {
1600 return TRUE;
1601 }
1602 }
1603
1604 //-----------------------------------------------------------------------------
1605 // Wait a certain time for tag response
1606 // If a response is captured return TRUE
1607 // If it takes too long return FALSE
1608 //-----------------------------------------------------------------------------
1609 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
1610 {
1611 uint32_t c;
1612
1613 // Set FPGA mode to "reader listen mode", no modulation (listen
1614 // only, since we are receiving, not transmitting).
1615 // Signal field is on with the appropriate LED
1616 LED_D_ON();
1617 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1618
1619 // Now get the answer from the card
1620 DemodInit(receivedResponse, receivedResponsePar);
1621
1622 // clear RXRDY:
1623 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1624
1625 c = 0;
1626 for(;;) {
1627 WDT_HIT();
1628
1629 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1630 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1631 if(ManchesterDecoding(b, offset, 0)) {
1632 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1633 return TRUE;
1634 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
1635 return FALSE;
1636 }
1637 }
1638 }
1639 }
1640
1641
1642 void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
1643 {
1644 CodeIso14443aBitsAsReaderPar(frame, bits, par);
1645
1646 // Send command to tag
1647 TransmitFor14443a(ToSend, ToSendMax, timing);
1648 if(trigger)
1649 LED_A_ON();
1650
1651 // Log reader command in trace buffer
1652 if (tracing) {
1653 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
1654 }
1655 }
1656
1657
1658 void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
1659 {
1660 ReaderTransmitBitsPar(frame, len*8, par, timing);
1661 }
1662
1663
1664 void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
1665 {
1666 // Generate parity and redirect
1667 uint8_t par[MAX_PARITY_SIZE];
1668 GetParity(frame, len/8, par);
1669 ReaderTransmitBitsPar(frame, len, par, timing);
1670 }
1671
1672
1673 void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
1674 {
1675 // Generate parity and redirect
1676 uint8_t par[MAX_PARITY_SIZE];
1677 GetParity(frame, len, par);
1678 ReaderTransmitBitsPar(frame, len*8, par, timing);
1679 }
1680
1681 int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
1682 {
1683 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return FALSE;
1684 if (tracing) {
1685 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1686 }
1687 return Demod.len;
1688 }
1689
1690 int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
1691 {
1692 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
1693 if (tracing) {
1694 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1695 }
1696 return Demod.len;
1697 }
1698
1699 /* performs iso14443a anticollision procedure
1700 * fills the uid pointer unless NULL
1701 * fills resp_data unless NULL */
1702 int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr) {
1703 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1704 uint8_t sel_all[] = { 0x93,0x20 };
1705 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1706 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1707 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1708 uint8_t resp_par[MAX_PARITY_SIZE];
1709 byte_t uid_resp[4];
1710 size_t uid_resp_len;
1711
1712 uint8_t sak = 0x04; // cascade uid
1713 int cascade_level = 0;
1714 int len;
1715
1716 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1717 ReaderTransmitBitsPar(wupa,7,0, NULL);
1718
1719 // Receive the ATQA
1720 if(!ReaderReceive(resp, resp_par)) return 0;
1721
1722 if(p_hi14a_card) {
1723 memcpy(p_hi14a_card->atqa, resp, 2);
1724 p_hi14a_card->uidlen = 0;
1725 memset(p_hi14a_card->uid,0,10);
1726 }
1727
1728 // clear uid
1729 if (uid_ptr) {
1730 memset(uid_ptr,0,10);
1731 }
1732
1733 // check for proprietary anticollision:
1734 if ((resp[0] & 0x1F) == 0) {
1735 return 3;
1736 }
1737
1738 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1739 // which case we need to make a cascade 2 request and select - this is a long UID
1740 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1741 for(; sak & 0x04; cascade_level++) {
1742 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1743 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1744
1745 // SELECT_ALL
1746 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1747 if (!ReaderReceive(resp, resp_par)) return 0;
1748
1749 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1750 memset(uid_resp, 0, 4);
1751 uint16_t uid_resp_bits = 0;
1752 uint16_t collision_answer_offset = 0;
1753 // anti-collision-loop:
1754 while (Demod.collisionPos) {
1755 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1756 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1757 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1758 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1759 }
1760 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1761 uid_resp_bits++;
1762 // construct anticollosion command:
1763 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1764 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1765 sel_uid[2+i] = uid_resp[i];
1766 }
1767 collision_answer_offset = uid_resp_bits%8;
1768 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1769 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
1770 }
1771 // finally, add the last bits and BCC of the UID
1772 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1773 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1774 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1775 }
1776
1777 } else { // no collision, use the response to SELECT_ALL as current uid
1778 memcpy(uid_resp, resp, 4);
1779 }
1780 uid_resp_len = 4;
1781
1782 // calculate crypto UID. Always use last 4 Bytes.
1783 if(cuid_ptr) {
1784 *cuid_ptr = bytes_to_num(uid_resp, 4);
1785 }
1786
1787 // Construct SELECT UID command
1788 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1789 memcpy(sel_uid+2, uid_resp, 4); // the UID
1790 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1791 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1792 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1793
1794 // Receive the SAK
1795 if (!ReaderReceive(resp, resp_par)) return 0;
1796 sak = resp[0];
1797
1798 // Test if more parts of the uid are coming
1799 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1800 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1801 // http://www.nxp.com/documents/application_note/AN10927.pdf
1802 uid_resp[0] = uid_resp[1];
1803 uid_resp[1] = uid_resp[2];
1804 uid_resp[2] = uid_resp[3];
1805
1806 uid_resp_len = 3;
1807 }
1808
1809 if(uid_ptr) {
1810 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1811 }
1812
1813 if(p_hi14a_card) {
1814 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1815 p_hi14a_card->uidlen += uid_resp_len;
1816 }
1817 }
1818
1819 if(p_hi14a_card) {
1820 p_hi14a_card->sak = sak;
1821 p_hi14a_card->ats_len = 0;
1822 }
1823
1824 // non iso14443a compliant tag
1825 if( (sak & 0x20) == 0) return 2;
1826
1827 // Request for answer to select
1828 AppendCrc14443a(rats, 2);
1829 ReaderTransmit(rats, sizeof(rats), NULL);
1830
1831 if (!(len = ReaderReceive(resp, resp_par))) return 0;
1832
1833
1834 if(p_hi14a_card) {
1835 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1836 p_hi14a_card->ats_len = len;
1837 }
1838
1839 // reset the PCB block number
1840 iso14_pcb_blocknum = 0;
1841
1842 // set default timeout based on ATS
1843 iso14a_set_ATS_timeout(resp);
1844
1845 return 1;
1846 }
1847
1848 void iso14443a_setup(uint8_t fpga_minor_mode) {
1849 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1850 // Set up the synchronous serial port
1851 FpgaSetupSsc();
1852 // connect Demodulated Signal to ADC:
1853 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1854
1855 // Signal field is on with the appropriate LED
1856 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1857 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1858 LED_D_ON();
1859 } else {
1860 LED_D_OFF();
1861 }
1862 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
1863
1864 // Start the timer
1865 StartCountSspClk();
1866
1867 DemodReset();
1868 UartReset();
1869 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1870 iso14a_set_timeout(1050); // 10ms default
1871 }
1872
1873 int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1874 uint8_t parity[MAX_PARITY_SIZE];
1875 uint8_t real_cmd[cmd_len+4];
1876 real_cmd[0] = 0x0a; //I-Block
1877 // put block number into the PCB
1878 real_cmd[0] |= iso14_pcb_blocknum;
1879 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1880 memcpy(real_cmd+2, cmd, cmd_len);
1881 AppendCrc14443a(real_cmd,cmd_len+2);
1882
1883 ReaderTransmit(real_cmd, cmd_len+4, NULL);
1884 size_t len = ReaderReceive(data, parity);
1885 uint8_t *data_bytes = (uint8_t *) data;
1886 if (!len)
1887 return 0; //DATA LINK ERROR
1888 // if we received an I- or R(ACK)-Block with a block number equal to the
1889 // current block number, toggle the current block number
1890 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1891 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1892 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1893 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1894 {
1895 iso14_pcb_blocknum ^= 1;
1896 }
1897
1898 return len;
1899 }
1900
1901 //-----------------------------------------------------------------------------
1902 // Read an ISO 14443a tag. Send out commands and store answers.
1903 //
1904 //-----------------------------------------------------------------------------
1905 void ReaderIso14443a(UsbCommand *c)
1906 {
1907 iso14a_command_t param = c->arg[0];
1908 uint8_t *cmd = c->d.asBytes;
1909 size_t len = c->arg[1] & 0xffff;
1910 size_t lenbits = c->arg[1] >> 16;
1911 uint32_t timeout = c->arg[2];
1912 uint32_t arg0 = 0;
1913 byte_t buf[USB_CMD_DATA_SIZE];
1914 uint8_t par[MAX_PARITY_SIZE];
1915
1916 if(param & ISO14A_CONNECT) {
1917 clear_trace();
1918 }
1919
1920 set_tracing(TRUE);
1921
1922 if(param & ISO14A_REQUEST_TRIGGER) {
1923 iso14a_set_trigger(TRUE);
1924 }
1925
1926 if(param & ISO14A_CONNECT) {
1927 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
1928 if(!(param & ISO14A_NO_SELECT)) {
1929 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1930 arg0 = iso14443a_select_card(NULL,card,NULL);
1931 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1932 }
1933 }
1934
1935 if(param & ISO14A_SET_TIMEOUT) {
1936 iso14a_set_timeout(timeout);
1937 }
1938
1939 if(param & ISO14A_APDU) {
1940 arg0 = iso14_apdu(cmd, len, buf);
1941 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1942 }
1943
1944 if(param & ISO14A_RAW) {
1945 if(param & ISO14A_APPEND_CRC) {
1946 if(param & ISO14A_TOPAZMODE) {
1947 AppendCrc14443b(cmd,len);
1948 } else {
1949 AppendCrc14443a(cmd,len);
1950 }
1951 len += 2;
1952 if (lenbits) lenbits += 16;
1953 }
1954 if(lenbits>0) { // want to send a specific number of bits (e.g. short commands)
1955 if(param & ISO14A_TOPAZMODE) {
1956 int bits_to_send = lenbits;
1957 uint16_t i = 0;
1958 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
1959 bits_to_send -= 7;
1960 while (bits_to_send > 0) {
1961 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
1962 bits_to_send -= 8;
1963 }
1964 } else {
1965 GetParity(cmd, lenbits/8, par);
1966 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
1967 }
1968 } else { // want to send complete bytes only
1969 if(param & ISO14A_TOPAZMODE) {
1970 uint16_t i = 0;
1971 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
1972 while (i < len) {
1973 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
1974 }
1975 } else {
1976 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
1977 }
1978 }
1979 arg0 = ReaderReceive(buf, par);
1980 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1981 }
1982
1983 if(param & ISO14A_REQUEST_TRIGGER) {
1984 iso14a_set_trigger(FALSE);
1985 }
1986
1987 if(param & ISO14A_NO_DISCONNECT) {
1988 return;
1989 }
1990
1991 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1992 LEDsoff();
1993 }
1994
1995
1996 // Determine the distance between two nonces.
1997 // Assume that the difference is small, but we don't know which is first.
1998 // Therefore try in alternating directions.
1999 int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2000
2001 uint16_t i;
2002 uint32_t nttmp1, nttmp2;
2003
2004 if (nt1 == nt2) return 0;
2005
2006 nttmp1 = nt1;
2007 nttmp2 = nt2;
2008
2009 for (i = 1; i < 32768; i++) {
2010 nttmp1 = prng_successor(nttmp1, 1);
2011 if (nttmp1 == nt2) return i;
2012 nttmp2 = prng_successor(nttmp2, 1);
2013 if (nttmp2 == nt1) return -i;
2014 }
2015
2016 return(-99999); // either nt1 or nt2 are invalid nonces
2017 }
2018
2019
2020 //-----------------------------------------------------------------------------
2021 // Recover several bits of the cypher stream. This implements (first stages of)
2022 // the algorithm described in "The Dark Side of Security by Obscurity and
2023 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2024 // (article by Nicolas T. Courtois, 2009)
2025 //-----------------------------------------------------------------------------
2026 void ReaderMifare(bool first_try)
2027 {
2028 // Mifare AUTH
2029 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2030 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2031 static uint8_t mf_nr_ar3;
2032
2033 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE];
2034 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE];
2035
2036 if (first_try) {
2037 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2038 }
2039
2040 // free eventually allocated BigBuf memory. We want all for tracing.
2041 BigBuf_free();
2042
2043 clear_trace();
2044 set_tracing(TRUE);
2045
2046 byte_t nt_diff = 0;
2047 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2048 static byte_t par_low = 0;
2049 bool led_on = TRUE;
2050 uint8_t uid[10] ={0};
2051 uint32_t cuid;
2052
2053 uint32_t nt = 0;
2054 uint32_t previous_nt = 0;
2055 static uint32_t nt_attacked = 0;
2056 byte_t par_list[8] = {0x00};
2057 byte_t ks_list[8] = {0x00};
2058
2059 #define PRNG_SEQUENCE_LENGTH (1 << 16);
2060 static uint32_t sync_time;
2061 static int32_t sync_cycles;
2062 int catch_up_cycles = 0;
2063 int last_catch_up = 0;
2064 uint16_t elapsed_prng_sequences;
2065 uint16_t consecutive_resyncs = 0;
2066 int isOK = 0;
2067
2068 if (first_try) {
2069 mf_nr_ar3 = 0;
2070 sync_time = GetCountSspClk() & 0xfffffff8;
2071 sync_cycles = PRNG_SEQUENCE_LENGTH; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the tag nonces).
2072 nt_attacked = 0;
2073 par[0] = 0;
2074 }
2075 else {
2076 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
2077 mf_nr_ar3++;
2078 mf_nr_ar[3] = mf_nr_ar3;
2079 par[0] = par_low;
2080 }
2081
2082 LED_A_ON();
2083 LED_B_OFF();
2084 LED_C_OFF();
2085
2086
2087 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2088 #define MAX_SYNC_TRIES 32
2089 #define NUM_DEBUG_INFOS 8 // per strategy
2090 #define MAX_STRATEGY 3
2091 uint16_t unexpected_random = 0;
2092 uint16_t sync_tries = 0;
2093 int16_t debug_info_nr = -1;
2094 uint16_t strategy = 0;
2095 int32_t debug_info[MAX_STRATEGY][NUM_DEBUG_INFOS];
2096 uint32_t select_time;
2097 uint32_t halt_time;
2098
2099 for(uint16_t i = 0; TRUE; i++) {
2100
2101 LED_C_ON();
2102 WDT_HIT();
2103
2104 // Test if the action was cancelled
2105 if(BUTTON_PRESS()) {
2106 isOK = -1;
2107 break;
2108 }
2109
2110 if (strategy == 2) {
2111 // test with additional hlt command
2112 halt_time = 0;
2113 int len = mifare_sendcmd_short(NULL, false, 0x50, 0x00, receivedAnswer, receivedAnswerPar, &halt_time);
2114 if (len && MF_DBGLEVEL >= 3) {
2115 Dbprintf("Unexpected response of %d bytes to hlt command (additional debugging).", len);
2116 }
2117 }
2118
2119 if (strategy == 3) {
2120 // test with FPGA power off/on
2121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2122 SpinDelay(200);
2123 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2124 SpinDelay(100);
2125 }
2126
2127 if(!iso14443a_select_card(uid, NULL, &cuid)) {
2128 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
2129 continue;
2130 }
2131 select_time = GetCountSspClk();
2132
2133 elapsed_prng_sequences = 1;
2134 if (debug_info_nr == -1) {
2135 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
2136 catch_up_cycles = 0;
2137
2138 // if we missed the sync time already, advance to the next nonce repeat
2139 while(GetCountSspClk() > sync_time) {
2140 elapsed_prng_sequences++;
2141 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2142 }
2143
2144 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2145 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2146 } else {
2147 // collect some information on tag nonces for debugging:
2148 #define DEBUG_FIXED_SYNC_CYCLES PRNG_SEQUENCE_LENGTH
2149 if (strategy == 0) {
2150 // nonce distances at fixed time after card select:
2151 sync_time = select_time + DEBUG_FIXED_SYNC_CYCLES;
2152 } else if (strategy == 1) {
2153 // nonce distances at fixed time between authentications:
2154 sync_time = sync_time + DEBUG_FIXED_SYNC_CYCLES;
2155 } else if (strategy == 2) {
2156 // nonce distances at fixed time after halt:
2157 sync_time = halt_time + DEBUG_FIXED_SYNC_CYCLES;
2158 } else {
2159 // nonce_distances at fixed time after power on
2160 sync_time = DEBUG_FIXED_SYNC_CYCLES;
2161 }
2162 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2163 }
2164
2165 // Receive the (4 Byte) "random" nonce
2166 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2167 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2168 continue;
2169 }
2170
2171 previous_nt = nt;
2172 nt = bytes_to_num(receivedAnswer, 4);
2173
2174 // Transmit reader nonce with fake par
2175 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2176
2177 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2178 int nt_distance = dist_nt(previous_nt, nt);
2179 if (nt_distance == 0) {
2180 nt_attacked = nt;
2181 } else {
2182 if (nt_distance == -99999) { // invalid nonce received
2183 unexpected_random++;
2184 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
2185 isOK = -3; // Card has an unpredictable PRNG. Give up
2186 break;
2187 } else {
2188 continue; // continue trying...
2189 }
2190 }
2191 if (++sync_tries > MAX_SYNC_TRIES) {
2192 if (strategy > MAX_STRATEGY || MF_DBGLEVEL < 3) {
2193 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2194 break;
2195 } else { // continue for a while, just to collect some debug info
2196 debug_info[strategy][debug_info_nr] = nt_distance;
2197 debug_info_nr++;
2198 if (debug_info_nr == NUM_DEBUG_INFOS) {
2199 strategy++;
2200 debug_info_nr = 0;
2201 }
2202 continue;
2203 }
2204 }
2205 sync_cycles = (sync_cycles - nt_distance/elapsed_prng_sequences);
2206 if (sync_cycles <= 0) {
2207 sync_cycles += PRNG_SEQUENCE_LENGTH;
2208 }
2209 if (MF_DBGLEVEL >= 3) {
2210 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
2211 }
2212 continue;
2213 }
2214 }
2215
2216 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2217 catch_up_cycles = -dist_nt(nt_attacked, nt);
2218 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2219 catch_up_cycles = 0;
2220 continue;
2221 }
2222 catch_up_cycles /= elapsed_prng_sequences;
2223 if (catch_up_cycles == last_catch_up) {
2224 consecutive_resyncs++;
2225 }
2226 else {
2227 last_catch_up = catch_up_cycles;
2228 consecutive_resyncs = 0;
2229 }
2230 if (consecutive_resyncs < 3) {
2231 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
2232 }
2233 else {
2234 sync_cycles = sync_cycles + catch_up_cycles;
2235 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
2236 last_catch_up = 0;
2237 catch_up_cycles = 0;
2238 consecutive_resyncs = 0;
2239 }
2240 continue;
2241 }
2242
2243 consecutive_resyncs = 0;
2244
2245 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2246 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2247 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2248
2249 if (nt_diff == 0) {
2250 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2251 }
2252
2253 led_on = !led_on;
2254 if(led_on) LED_B_ON(); else LED_B_OFF();
2255
2256 par_list[nt_diff] = SwapBits(par[0], 8);
2257 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2258
2259 // Test if the information is complete
2260 if (nt_diff == 0x07) {
2261 isOK = 1;
2262 break;
2263 }
2264
2265 nt_diff = (nt_diff + 1) & 0x07;
2266 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2267 par[0] = par_low;
2268 } else {
2269 if (nt_diff == 0 && first_try)
2270 {
2271 par[0]++;
2272 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
2273 isOK = -2;
2274 break;
2275 }
2276 } else {
2277 par[0] = ((par[0] & 0x1F) + 1) | par_low;
2278 }
2279 }
2280 }
2281
2282
2283 mf_nr_ar[3] &= 0x1F;
2284
2285 if (isOK == -4) {
2286 if (MF_DBGLEVEL >= 3) {
2287 for (uint16_t i = 0; i <= MAX_STRATEGY; i++) {
2288 for(uint16_t j = 0; j < NUM_DEBUG_INFOS; j++) {
2289 Dbprintf("collected debug info[%d][%d] = %d", i, j, debug_info[i][j]);
2290 }
2291 }
2292 }
2293 }
2294
2295 byte_t buf[28];
2296 memcpy(buf + 0, uid, 4);
2297 num_to_bytes(nt, 4, buf + 4);
2298 memcpy(buf + 8, par_list, 8);
2299 memcpy(buf + 16, ks_list, 8);
2300 memcpy(buf + 24, mf_nr_ar, 4);
2301
2302 cmd_send(CMD_ACK, isOK, 0, 0, buf, 28);
2303
2304 // Thats it...
2305 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2306 LEDsoff();
2307
2308 set_tracing(FALSE);
2309 }
2310
2311 typedef struct {
2312 uint32_t cuid;
2313 uint8_t sector;
2314 uint8_t keytype;
2315 uint32_t nonce;
2316 uint32_t ar;
2317 uint32_t nr;
2318 uint32_t nonce2;
2319 uint32_t ar2;
2320 uint32_t nr2;
2321 } nonces_t;
2322
2323 /**
2324 *MIFARE 1K simulate.
2325 *
2326 *@param flags :
2327 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2328 * FLAG_4B_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2329 * FLAG_7B_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2330 * FLAG_10B_UID_IN_DATA - use 10-byte UID in the data-section not finished
2331 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2332 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is infinite ...
2333 * (unless reader attack mode enabled then it runs util it gets enough nonces to recover all keys attmpted)
2334 */
2335 void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
2336 {
2337 int cardSTATE = MFEMUL_NOFIELD;
2338 int _UID_LEN = 0; // 4, 7, 10
2339 int _7BUID = 0;
2340 int vHf = 0; // in mV
2341 int res;
2342 uint32_t selTimer = 0;
2343 uint32_t authTimer = 0;
2344 uint16_t len = 0;
2345 uint8_t cardWRBL = 0;
2346 uint8_t cardAUTHSC = 0;
2347 uint8_t cardAUTHKEY = 0xff; // no authentication
2348 uint32_t cardRr = 0;
2349 uint32_t cuid = 0;
2350 //uint32_t rn_enc = 0;
2351 uint32_t ans = 0;
2352 uint32_t cardINTREG = 0;
2353 uint8_t cardINTBLOCK = 0;
2354 struct Crypto1State mpcs = {0, 0};
2355 struct Crypto1State *pcs;
2356 pcs = &mpcs;
2357 uint32_t numReads = 0;//Counts numer of times reader read a block
2358 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2359 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE];
2360 uint8_t response[MAX_MIFARE_FRAME_SIZE];
2361 uint8_t response_par[MAX_MIFARE_PARITY_SIZE];
2362
2363 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2364 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2365 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2366 uint8_t rUIDBCC3[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2367
2368 uint8_t rSAK[] = {0x08, 0xb6, 0xdd};
2369 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
2370 uint8_t rSAK2[] = {0x04, 0xda, 0x17}; //need to look up
2371
2372 uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};
2373 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
2374
2375 //Here, we collect UID,sector,keytype,NT,AR,NR,NT2,AR2,NR2
2376 // This will be used in the reader-only attack.
2377
2378 //allow collecting up to 8 sets of nonces to allow recovery of 8 keys
2379 #define ATTACK_KEY_COUNT 8
2380 nonces_t ar_nr_resp[ATTACK_KEY_COUNT*2]; //*2 for 2 separate attack types
2381 memset(ar_nr_resp, 0x00, sizeof(ar_nr_resp));
2382
2383 uint8_t ar_nr_collected[ATTACK_KEY_COUNT*2];
2384 memset(ar_nr_collected, 0x00, sizeof(ar_nr_collected));
2385 bool gettingMoebius = false;
2386 uint8_t nonce1_count = 0;
2387 uint8_t nonce2_count = 0;
2388 uint8_t moebius_n_count = 0;
2389 uint8_t mM = 0; //moebius_modifier for collection storage
2390
2391 // Authenticate response - nonce
2392 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
2393
2394 //-- Determine the UID
2395 // Can be set from emulator memory, incoming data
2396 // and can be 7 or 4 bytes long
2397 if (flags & FLAG_4B_UID_IN_DATA)
2398 {
2399 // 4B uid comes from data-portion of packet
2400 memcpy(rUIDBCC1,datain,4);
2401 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2402 _UID_LEN = 4;
2403 } else if (flags & FLAG_7B_UID_IN_DATA) {
2404 // 7B uid comes from data-portion of packet
2405 memcpy(&rUIDBCC1[1],datain,3);
2406 memcpy(rUIDBCC2, datain+3, 4);
2407 _7BUID = true;
2408 _UID_LEN = 7;
2409 } else if (flags & FLAG_10B_UID_IN_DATA) {
2410 memcpy(&rUIDBCC1[1], datain, 3);
2411 memcpy(&rUIDBCC2[1], datain+3, 3);
2412 memcpy( rUIDBCC3, datain+6, 4);
2413 _UID_LEN = 10;
2414 } else {
2415 // get UID from emul memory - guess at length
2416 emlGetMemBt(receivedCmd, 7, 1);
2417 _7BUID = !(receivedCmd[0] == 0x00);
2418 if (!_7BUID) { // ---------- 4BUID
2419 emlGetMemBt(rUIDBCC1, 0, 4);
2420 _UID_LEN = 4;
2421 } else { // ---------- 7BUID
2422 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2423 emlGetMemBt(rUIDBCC2, 3, 4);
2424 _UID_LEN = 7;
2425 }
2426 }
2427
2428 switch (_UID_LEN) {
2429 case 4:
2430 // save CUID
2431 cuid = bytes_to_num(rUIDBCC1, 4);
2432 // BCC
2433 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2434 if (MF_DBGLEVEL >= 2) {
2435 Dbprintf("4B UID: %02x%02x%02x%02x",
2436 rUIDBCC1[0],
2437 rUIDBCC1[1],
2438 rUIDBCC1[2],
2439 rUIDBCC1[3]
2440 );
2441 }
2442 break;
2443 case 7:
2444 rATQA[0] |= 0x40;
2445 // save CUID
2446 cuid = bytes_to_num(rUIDBCC2, 4);
2447 // CascadeTag, CT
2448 rUIDBCC1[0] = 0x88;
2449 // BCC
2450 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2451 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2452 if (MF_DBGLEVEL >= 2) {
2453 Dbprintf("7B UID: %02x %02x %02x %02x %02x %02x %02x",
2454 rUIDBCC1[1],
2455 rUIDBCC1[2],
2456 rUIDBCC1[3],
2457 rUIDBCC2[0],
2458 rUIDBCC2[1],
2459 rUIDBCC2[2],
2460 rUIDBCC2[3]
2461 );
2462 }
2463 break;
2464 case 10:
2465 rATQA[0] |= 0x80;
2466 //sak_10[0] &= 0xFB;
2467 // save CUID
2468 cuid = bytes_to_num(rUIDBCC3, 4);
2469 // CascadeTag, CT
2470 rUIDBCC1[0] = 0x88;
2471 rUIDBCC2[0] = 0x88;
2472 // BCC
2473 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2474 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2475 rUIDBCC3[4] = rUIDBCC3[0] ^ rUIDBCC3[1] ^ rUIDBCC3[2] ^ rUIDBCC3[3];
2476
2477 if (MF_DBGLEVEL >= 2) {
2478 Dbprintf("10B UID: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
2479 rUIDBCC1[1],
2480 rUIDBCC1[2],
2481 rUIDBCC1[3],
2482 rUIDBCC2[1],
2483 rUIDBCC2[2],
2484 rUIDBCC2[3],
2485 rUIDBCC3[0],
2486 rUIDBCC3[1],
2487 rUIDBCC3[2],
2488 rUIDBCC3[3]
2489 );
2490 }
2491 break;
2492 default:
2493 break;
2494 }
2495
2496 // We need to listen to the high-frequency, peak-detected path.
2497 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2498
2499 // free eventually allocated BigBuf memory but keep Emulator Memory
2500 BigBuf_free_keep_EM();
2501
2502 // clear trace
2503 clear_trace();
2504 set_tracing(TRUE);
2505
2506 bool finished = FALSE;
2507 bool button_pushed = BUTTON_PRESS();
2508 while (!button_pushed && !finished && !usb_poll_validate_length()) {
2509 WDT_HIT();
2510
2511 // find reader field
2512 if (cardSTATE == MFEMUL_NOFIELD) {
2513 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
2514 if (vHf > MF_MINFIELDV) {
2515 cardSTATE_TO_IDLE();
2516 LED_A_ON();
2517 }
2518 }
2519 if (cardSTATE == MFEMUL_NOFIELD) continue;
2520
2521 //Now, get data
2522 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
2523 if (res == 2) { //Field is off!
2524 cardSTATE = MFEMUL_NOFIELD;
2525 LEDsoff();
2526 continue;
2527 } else if (res == 1) {
2528 break; //return value 1 means button press
2529 }
2530
2531 // REQ or WUP request in ANY state and WUP in HALTED state
2532 if (len == 1 && ((receivedCmd[0] == ISO14443A_CMD_REQA && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == ISO14443A_CMD_WUPA)) {
2533 selTimer = GetTickCount();
2534 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == ISO14443A_CMD_WUPA));
2535 cardSTATE = MFEMUL_SELECT1;
2536
2537 // init crypto block
2538 LED_B_OFF();
2539 LED_C_OFF();
2540 crypto1_destroy(pcs);
2541 cardAUTHKEY = 0xff;
2542 continue;
2543 }
2544
2545 switch (cardSTATE) {
2546 case MFEMUL_NOFIELD:
2547 case MFEMUL_HALTED:
2548 case MFEMUL_IDLE:{
2549 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2550 break;
2551 }
2552 case MFEMUL_SELECT1:{
2553 // select all
2554 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
2555 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
2556 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
2557 break;
2558 }
2559
2560 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2561 {
2562 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2563 }
2564 // select card
2565 // check correct sak values... (marshmellow)
2566 if (len == 9 &&
2567 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2568 switch(_UID_LEN) {
2569 case 4:
2570 cardSTATE = MFEMUL_WORK;
2571 LED_B_ON();
2572 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2573 EmSendCmd(rSAK, sizeof(rSAK));
2574 break;
2575 case 7:
2576 cardSTATE = MFEMUL_SELECT2;
2577 EmSendCmd(rSAK1, sizeof(rSAK1));
2578 break;
2579 case 10:
2580 cardSTATE = MFEMUL_SELECT2;
2581 EmSendCmd(rSAK2, sizeof(rSAK2));
2582 break;
2583 default:break;
2584 }
2585 } else {
2586 cardSTATE_TO_IDLE();
2587 }
2588 break;
2589 }
2590 case MFEMUL_SELECT3:{
2591 if (!len) {
2592 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2593 break;
2594 }
2595 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 && receivedCmd[1] == 0x20)) {
2596 EmSendCmd(rUIDBCC3, sizeof(rUIDBCC3));
2597 break;
2598 }
2599 if (len == 9 &&
2600 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 &&
2601 receivedCmd[1] == 0x70 &&
2602 memcmp(&receivedCmd[2], rUIDBCC3, 4) == 0) ) {
2603
2604 EmSendCmd(rSAK2, sizeof(rSAK2));
2605 cardSTATE = MFEMUL_WORK;
2606 LED_B_ON();
2607 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol3 time: %d", GetTickCount() - selTimer);
2608 break;
2609 }
2610 cardSTATE_TO_IDLE();
2611 break;
2612 }
2613 case MFEMUL_AUTH1:{
2614 if( len != 8)
2615 {
2616 cardSTATE_TO_IDLE();
2617 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2618 break;
2619 }
2620
2621 uint32_t nr = bytes_to_num(receivedCmd, 4);
2622 uint32_t ar = bytes_to_num(&receivedCmd[4], 4);
2623
2624 //Collect AR/NR per keytype & sector
2625 if(flags & FLAG_NR_AR_ATTACK) {
2626 for (uint8_t i = 0; i < ATTACK_KEY_COUNT; i++) {
2627 if ( ar_nr_collected[i+mM]==0 || ((cardAUTHSC == ar_nr_resp[i+mM].sector) && (cardAUTHKEY == ar_nr_resp[i+mM].keytype) && (ar_nr_collected[i+mM] > 0)) ) {
2628 // if first auth for sector, or matches sector and keytype of previous auth
2629 if (ar_nr_collected[i+mM] < 2) {
2630 // if we haven't already collected 2 nonces for this sector
2631 if (ar_nr_resp[ar_nr_collected[i+mM]].ar != ar) {
2632 // Avoid duplicates... probably not necessary, ar should vary.
2633 if (ar_nr_collected[i+mM]==0) {
2634 // first nonce collect
2635 ar_nr_resp[i+mM].cuid = cuid;
2636 ar_nr_resp[i+mM].sector = cardAUTHSC;
2637 ar_nr_resp[i+mM].keytype = cardAUTHKEY;
2638 ar_nr_resp[i+mM].nonce = nonce;
2639 ar_nr_resp[i+mM].nr = nr;
2640 ar_nr_resp[i+mM].ar = ar;
2641 nonce1_count++;
2642 //add this nonce to first moebius nonce
2643 ar_nr_resp[i+ATTACK_KEY_COUNT].cuid = cuid;
2644 ar_nr_resp[i+ATTACK_KEY_COUNT].sector = cardAUTHSC;
2645 ar_nr_resp[i+ATTACK_KEY_COUNT].keytype = cardAUTHKEY;
2646 ar_nr_resp[i+ATTACK_KEY_COUNT].nonce = nonce;
2647 ar_nr_resp[i+ATTACK_KEY_COUNT].nr = nr;
2648 ar_nr_resp[i+ATTACK_KEY_COUNT].ar = ar;
2649 ar_nr_collected[i+ATTACK_KEY_COUNT]++;
2650 } else { //second nonce collect (std and moebius)
2651 ar_nr_resp[i+mM].nonce2 = nonce;
2652 ar_nr_resp[i+mM].nr2 = nr;
2653 ar_nr_resp[i+mM].ar2 = ar;
2654 if (!gettingMoebius) {
2655 nonce2_count++;
2656 //check if this was the last second nonce we need for std attack
2657 if ( nonce2_count == nonce1_count ) {
2658 //done collecting std test switch to moebius
2659 //finish incrementing last sample
2660 ar_nr_collected[i+mM]++;
2661 //switch to moebius collection
2662 gettingMoebius = true;
2663 mM = ATTACK_KEY_COUNT;
2664 nonce = nonce*7;
2665 break;
2666 }
2667 } else {
2668 moebius_n_count++;
2669 //if we've collected all the nonces we need - finish.
2670 if (nonce1_count == moebius_n_count) finished = true;
2671 }
2672 }
2673 ar_nr_collected[i+mM]++;
2674 }
2675 } else { //already collected 2 nonces for sector - dump out
2676 //finished = true;
2677 }
2678 // we found right spot for this nonce stop looking
2679 break;
2680 }
2681 }
2682 }
2683
2684 // --- crypto
2685 crypto1_word(pcs, nr , 1);
2686 cardRr = ar ^ crypto1_word(pcs, 0, 0);
2687
2688 // test if auth OK
2689 if (cardRr != prng_successor(nonce, 64)){
2690 if (MF_DBGLEVEL >= 2) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2691 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2692 cardRr, prng_successor(nonce, 64));
2693 // Shouldn't we respond anything here?
2694 // Right now, we don't nack or anything, which causes the
2695 // reader to do a WUPA after a while. /Martin
2696 // -- which is the correct response. /piwi
2697 cardSTATE_TO_IDLE();
2698 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2699 break;
2700 }
2701
2702 //auth successful
2703 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2704
2705 num_to_bytes(ans, 4, rAUTH_AT);
2706 // --- crypto
2707 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2708 LED_C_ON();
2709 cardSTATE = MFEMUL_WORK;
2710 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2711 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2712 GetTickCount() - authTimer);
2713 break;
2714 }
2715 case MFEMUL_SELECT2:{
2716 if (!len) {
2717 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2718 break;
2719 }
2720 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
2721 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2722 break;
2723 }
2724
2725 // select 2 card
2726 if (len == 9 &&
2727 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2728 //which sak now? (marshmellow)
2729 EmSendCmd(rSAK, sizeof(rSAK));
2730 switch(_UID_LEN) {
2731 case 7:
2732 cardSTATE = MFEMUL_WORK;
2733 LED_B_ON();
2734 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2735 break;
2736 case 10:
2737 cardSTATE = MFEMUL_SELECT3;
2738 break;
2739 default:break;
2740 }
2741 break;
2742 }
2743
2744 // i guess there is a command). go into the work state.
2745 if (len != 4) {
2746 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2747 break;
2748 }
2749 cardSTATE = MFEMUL_WORK;
2750 //goto lbWORK;
2751 //intentional fall-through to the next case-stmt
2752 }
2753
2754 case MFEMUL_WORK:{
2755 if (len == 0) {
2756 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2757 break;
2758 }
2759
2760 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2761
2762 if(encrypted_data) {
2763 // decrypt seqence
2764 mf_crypto1_decrypt(pcs, receivedCmd, len);
2765 }
2766
2767 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2768
2769 // if authenticating to a block that shouldn't exist - as long as we are not doing the reader attack
2770 if (receivedCmd[1] >= 16 * 4 && !(flags & FLAG_NR_AR_ATTACK)) {
2771 //is this the correct response to an auth on a out of range block? marshmellow
2772 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2773 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02x) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2774 break;
2775 }
2776
2777 authTimer = GetTickCount();
2778 cardAUTHSC = receivedCmd[1] / 4; // received block num
2779 cardAUTHKEY = receivedCmd[0] - 0x60;
2780 crypto1_destroy(pcs);//Added by martin
2781 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
2782 //uint64_t key=emlGetKey(cardAUTHSC, cardAUTHKEY);
2783 //Dbprintf("key: %04x%08x",(uint32_t)(key>>32)&0xFFFF,(uint32_t)(key&0xFFFFFFFF));
2784
2785 if (!encrypted_data) { // first authentication
2786 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2787
2788 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2789 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
2790 } else { // nested authentication
2791 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2792 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
2793 num_to_bytes(ans, 4, rAUTH_AT);
2794 }
2795
2796 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2797 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2798 cardSTATE = MFEMUL_AUTH1;
2799 break;
2800 }
2801
2802 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2803 // BUT... ACK --> NACK
2804 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2805 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2806 break;
2807 }
2808
2809 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2810 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2811 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2812 break;
2813 }
2814
2815 if(len != 4) {
2816 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2817 break;
2818 }
2819
2820 if(receivedCmd[0] == 0x30 // read block
2821 || receivedCmd[0] == 0xA0 // write block
2822 || receivedCmd[0] == 0xC0 // inc
2823 || receivedCmd[0] == 0xC1 // dec
2824 || receivedCmd[0] == 0xC2 // restore
2825 || receivedCmd[0] == 0xB0) { // transfer
2826 if (receivedCmd[1] >= 16 * 4) {
2827 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2828 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02x) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2829 break;
2830 }
2831
2832 if (receivedCmd[1] / 4 != cardAUTHSC) {
2833 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2834 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02x) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
2835 break;
2836 }
2837 }
2838 // read block
2839 if (receivedCmd[0] == 0x30) {
2840 if (MF_DBGLEVEL >= 4) {
2841 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2842 }
2843 emlGetMem(response, receivedCmd[1], 1);
2844 AppendCrc14443a(response, 16);
2845 mf_crypto1_encrypt(pcs, response, 18, response_par);
2846 EmSendCmdPar(response, 18, response_par);
2847 numReads++;
2848 if(exitAfterNReads > 0 && numReads == exitAfterNReads) {
2849 Dbprintf("%d reads done, exiting", numReads);
2850 finished = true;
2851 }
2852 break;
2853 }
2854 // write block
2855 if (receivedCmd[0] == 0xA0) {
2856 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
2857 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2858 cardSTATE = MFEMUL_WRITEBL2;
2859 cardWRBL = receivedCmd[1];
2860 break;
2861 }
2862 // increment, decrement, restore
2863 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
2864 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2865 if (emlCheckValBl(receivedCmd[1])) {
2866 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
2867 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2868 break;
2869 }
2870 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2871 if (receivedCmd[0] == 0xC1)
2872 cardSTATE = MFEMUL_INTREG_INC;
2873 if (receivedCmd[0] == 0xC0)
2874 cardSTATE = MFEMUL_INTREG_DEC;
2875 if (receivedCmd[0] == 0xC2)
2876 cardSTATE = MFEMUL_INTREG_REST;
2877 cardWRBL = receivedCmd[1];
2878 break;
2879 }
2880 // transfer
2881 if (receivedCmd[0] == 0xB0) {
2882 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2883 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2884 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2885 else
2886 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2887 break;
2888 }
2889 // halt
2890 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
2891 LED_B_OFF();
2892 LED_C_OFF();
2893 cardSTATE = MFEMUL_HALTED;
2894 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
2895 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2896 break;
2897 }
2898 // RATS
2899 if (receivedCmd[0] == 0xe0) {//RATS
2900 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2901 break;
2902 }
2903 // command not allowed
2904 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2905 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2906 break;
2907 }
2908 case MFEMUL_WRITEBL2:{
2909 if (len == 18){
2910 mf_crypto1_decrypt(pcs, receivedCmd, len);
2911 emlSetMem(receivedCmd, cardWRBL, 1);
2912 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2913 cardSTATE = MFEMUL_WORK;
2914 } else {
2915 cardSTATE_TO_IDLE();
2916 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2917 }
2918 break;
2919 }
2920
2921 case MFEMUL_INTREG_INC:{
2922 mf_crypto1_decrypt(pcs, receivedCmd, len);
2923 memcpy(&ans, receivedCmd, 4);
2924 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2925 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2926 cardSTATE_TO_IDLE();
2927 break;
2928 }
2929 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2930 cardINTREG = cardINTREG + ans;
2931 cardSTATE = MFEMUL_WORK;
2932 break;
2933 }
2934 case MFEMUL_INTREG_DEC:{
2935 mf_crypto1_decrypt(pcs, receivedCmd, len);
2936 memcpy(&ans, receivedCmd, 4);
2937 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2938 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2939 cardSTATE_TO_IDLE();
2940 break;
2941 }
2942 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2943 cardINTREG = cardINTREG - ans;
2944 cardSTATE = MFEMUL_WORK;
2945 break;
2946 }
2947 case MFEMUL_INTREG_REST:{
2948 mf_crypto1_decrypt(pcs, receivedCmd, len);
2949 memcpy(&ans, receivedCmd, 4);
2950 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2951 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2952 cardSTATE_TO_IDLE();
2953 break;
2954 }
2955 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2956 cardSTATE = MFEMUL_WORK;
2957 break;
2958 }
2959 }
2960 button_pushed = BUTTON_PRESS();
2961 }
2962
2963 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2964 LEDsoff();
2965
2966 if(flags & FLAG_NR_AR_ATTACK && MF_DBGLEVEL >= 1)
2967 {
2968 for ( uint8_t i = 0; i < ATTACK_KEY_COUNT; i++) {
2969 if (ar_nr_collected[i] == 2) {
2970 Dbprintf("Collected two pairs of AR/NR which can be used to extract %s from reader for sector %d:", (i<ATTACK_KEY_COUNT/2) ? "keyA" : "keyB", ar_nr_resp[i].sector);
2971 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
2972 ar_nr_resp[i].cuid, //UID
2973 ar_nr_resp[i].nonce, //NT
2974 ar_nr_resp[i].nr, //NR1
2975 ar_nr_resp[i].ar, //AR1
2976 ar_nr_resp[i].nr2, //NR2
2977 ar_nr_resp[i].ar2 //AR2
2978 );
2979 }
2980 }
2981 for ( uint8_t i = ATTACK_KEY_COUNT; i < ATTACK_KEY_COUNT*2; i++) {
2982 if (ar_nr_collected[i] == 2) {
2983 Dbprintf("Collected two pairs of AR/NR which can be used to extract %s from reader for sector %d:", (i<ATTACK_KEY_COUNT/2) ? "keyA" : "keyB", ar_nr_resp[i].sector);
2984 Dbprintf("../tools/mfkey/mfkey32v2 %08x %08x %08x %08x %08x %08x %08x",
2985 ar_nr_resp[i].cuid, //UID
2986 ar_nr_resp[i].nonce, //NT
2987 ar_nr_resp[i].nr, //NR1
2988 ar_nr_resp[i].ar, //AR1
2989 ar_nr_resp[i].nonce2,//NT2
2990 ar_nr_resp[i].nr2, //NR2
2991 ar_nr_resp[i].ar2 //AR2
2992 );
2993 }
2994 }
2995 }
2996 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
2997
2998 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2999 {
3000 //Send the collected ar_nr in the response
3001 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,button_pushed,0,&ar_nr_resp,sizeof(ar_nr_resp));
3002 }
3003
3004 }
3005
3006
3007
3008 //-----------------------------------------------------------------------------
3009 // MIFARE sniffer.
3010 //
3011 //-----------------------------------------------------------------------------
3012 void RAMFUNC SniffMifare(uint8_t param) {
3013 // param:
3014 // bit 0 - trigger from first card answer
3015 // bit 1 - trigger from first reader 7-bit request
3016
3017 // C(red) A(yellow) B(green)
3018 LEDsoff();
3019 // init trace buffer
3020 clear_trace();
3021 set_tracing(TRUE);
3022
3023 // The command (reader -> tag) that we're receiving.
3024 // The length of a received command will in most cases be no more than 18 bytes.
3025 // So 32 should be enough!
3026 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
3027 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
3028 // The response (tag -> reader) that we're receiving.
3029 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
3030 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
3031
3032 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
3033
3034 // free eventually allocated BigBuf memory
3035 BigBuf_free();
3036 // allocate the DMA buffer, used to stream samples from the FPGA
3037 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
3038 uint8_t *data = dmaBuf;
3039 uint8_t previous_data = 0;
3040 int maxDataLen = 0;
3041 int dataLen = 0;
3042 bool ReaderIsActive = FALSE;
3043 bool TagIsActive = FALSE;
3044
3045 // Set up the demodulator for tag -> reader responses.
3046 DemodInit(receivedResponse, receivedResponsePar);
3047
3048 // Set up the demodulator for the reader -> tag commands
3049 UartInit(receivedCmd, receivedCmdPar);
3050
3051 // Setup for the DMA.
3052 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
3053
3054 LED_D_OFF();
3055
3056 // init sniffer
3057 MfSniffInit();
3058
3059 // And now we loop, receiving samples.
3060 for(uint32_t sniffCounter = 0; TRUE; ) {
3061
3062 if(BUTTON_PRESS()) {
3063 DbpString("cancelled by button");
3064 break;
3065 }
3066
3067 LED_A_ON();
3068 WDT_HIT();
3069
3070 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
3071 // check if a transaction is completed (timeout after 2000ms).
3072 // if yes, stop the DMA transfer and send what we have so far to the client
3073 if (MfSniffSend(2000)) {
3074 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
3075 sniffCounter = 0;
3076 data = dmaBuf;
3077 maxDataLen = 0;
3078 ReaderIsActive = FALSE;
3079 TagIsActive = FALSE;
3080 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
3081 }
3082 }
3083
3084 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
3085 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
3086 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
3087 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
3088 } else {
3089 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
3090 }
3091 // test for length of buffer
3092 if(dataLen > maxDataLen) { // we are more behind than ever...
3093 maxDataLen = dataLen;
3094 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
3095 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
3096 break;
3097 }
3098 }
3099 if(dataLen < 1) continue;
3100
3101 // primary buffer was stopped ( <-- we lost data!
3102 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
3103 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
3104 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
3105 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
3106 }
3107 // secondary buffer sets as primary, secondary buffer was stopped
3108 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
3109 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
3110 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
3111 }
3112
3113 LED_A_OFF();
3114
3115 if (sniffCounter & 0x01) {
3116
3117 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
3118 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
3119 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
3120 LED_C_INV();
3121 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
3122
3123 /* And ready to receive another command. */
3124 UartInit(receivedCmd, receivedCmdPar);
3125
3126 /* And also reset the demod code */
3127 DemodReset();
3128 }
3129 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
3130 }
3131
3132 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
3133 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
3134 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
3135 LED_C_INV();
3136
3137 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
3138
3139 // And ready to receive another response.
3140 DemodReset();
3141 // And reset the Miller decoder including its (now outdated) input buffer
3142 UartInit(receivedCmd, receivedCmdPar);
3143 }
3144 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
3145 }
3146 }
3147
3148 previous_data = *data;
3149 sniffCounter++;
3150 data++;
3151 if(data == dmaBuf + DMA_BUFFER_SIZE) {
3152 data = dmaBuf;
3153 }
3154
3155 } // main cycle
3156
3157 DbpString("COMMAND FINISHED");
3158
3159 FpgaDisableSscDma();
3160 MfSniffEnd();
3161
3162 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
3163 LEDsoff();
3164 }
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