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[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "usb_cdc.h"
20
21
22 /**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
30 {
31
32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
34
35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
71
72 // now do the read
73 DoAcquisition_config(false);
74 }
75
76
77
78 /* blank r/w tag data stream
79 ...0000000000000000 01111111
80 1010101010101010101010101010101010101010101010101010101010101010
81 0011010010100001
82 01111111
83 101010101010101[0]000...
84
85 [5555fe852c5555555555555555fe0000]
86 */
87 void ReadTItag(void)
88 {
89 // some hardcoded initial params
90 // when we read a TI tag we sample the zerocross line at 2Mhz
91 // TI tags modulate a 1 as 16 cycles of 123.2Khz
92 // TI tags modulate a 0 as 16 cycles of 134.2Khz
93 #define FSAMPLE 2000000
94 #define FREQLO 123200
95 #define FREQHI 134200
96
97 signed char *dest = (signed char *)BigBuf_get_addr();
98 uint16_t n = BigBuf_max_traceLen();
99 // 128 bit shift register [shift3:shift2:shift1:shift0]
100 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
101
102 int i, cycles=0, samples=0;
103 // how many sample points fit in 16 cycles of each frequency
104 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
105 // when to tell if we're close enough to one freq or another
106 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
107
108 // TI tags charge at 134.2Khz
109 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
110 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
111
112 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
113 // connects to SSP_DIN and the SSP_DOUT logic level controls
114 // whether we're modulating the antenna (high)
115 // or listening to the antenna (low)
116 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
117
118 // get TI tag data into the buffer
119 AcquireTiType();
120
121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
122
123 for (i=0; i<n-1; i++) {
124 // count cycles by looking for lo to hi zero crossings
125 if ( (dest[i]<0) && (dest[i+1]>0) ) {
126 cycles++;
127 // after 16 cycles, measure the frequency
128 if (cycles>15) {
129 cycles=0;
130 samples=i-samples; // number of samples in these 16 cycles
131
132 // TI bits are coming to us lsb first so shift them
133 // right through our 128 bit right shift register
134 shift0 = (shift0>>1) | (shift1 << 31);
135 shift1 = (shift1>>1) | (shift2 << 31);
136 shift2 = (shift2>>1) | (shift3 << 31);
137 shift3 >>= 1;
138
139 // check if the cycles fall close to the number
140 // expected for either the low or high frequency
141 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
142 // low frequency represents a 1
143 shift3 |= (1<<31);
144 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
145 // high frequency represents a 0
146 } else {
147 // probably detected a gay waveform or noise
148 // use this as gaydar or discard shift register and start again
149 shift3 = shift2 = shift1 = shift0 = 0;
150 }
151 samples = i;
152
153 // for each bit we receive, test if we've detected a valid tag
154
155 // if we see 17 zeroes followed by 6 ones, we might have a tag
156 // remember the bits are backwards
157 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
158 // if start and end bytes match, we have a tag so break out of the loop
159 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
160 cycles = 0xF0B; //use this as a flag (ugly but whatever)
161 break;
162 }
163 }
164 }
165 }
166 }
167
168 // if flag is set we have a tag
169 if (cycles!=0xF0B) {
170 DbpString("Info: No valid tag detected.");
171 } else {
172 // put 64 bit data into shift1 and shift0
173 shift0 = (shift0>>24) | (shift1 << 8);
174 shift1 = (shift1>>24) | (shift2 << 8);
175
176 // align 16 bit crc into lower half of shift2
177 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
178
179 // if r/w tag, check ident match
180 if (shift3 & (1<<15) ) {
181 DbpString("Info: TI tag is rewriteable");
182 // only 15 bits compare, last bit of ident is not valid
183 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
184 DbpString("Error: Ident mismatch!");
185 } else {
186 DbpString("Info: TI tag ident is valid");
187 }
188 } else {
189 DbpString("Info: TI tag is readonly");
190 }
191
192 // WARNING the order of the bytes in which we calc crc below needs checking
193 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
194 // bytes in reverse or something
195 // calculate CRC
196 uint32_t crc=0;
197
198 crc = update_crc16(crc, (shift0)&0xff);
199 crc = update_crc16(crc, (shift0>>8)&0xff);
200 crc = update_crc16(crc, (shift0>>16)&0xff);
201 crc = update_crc16(crc, (shift0>>24)&0xff);
202 crc = update_crc16(crc, (shift1)&0xff);
203 crc = update_crc16(crc, (shift1>>8)&0xff);
204 crc = update_crc16(crc, (shift1>>16)&0xff);
205 crc = update_crc16(crc, (shift1>>24)&0xff);
206
207 Dbprintf("Info: Tag data: %x%08x, crc=%x",
208 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
209 if (crc != (shift2&0xffff)) {
210 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
211 } else {
212 DbpString("Info: CRC is good");
213 }
214 }
215 }
216
217 void WriteTIbyte(uint8_t b)
218 {
219 int i = 0;
220
221 // modulate 8 bits out to the antenna
222 for (i=0; i<8; i++)
223 {
224 if (b&(1<<i)) {
225 // stop modulating antenna
226 LOW(GPIO_SSC_DOUT);
227 SpinDelayUs(1000);
228 // modulate antenna
229 HIGH(GPIO_SSC_DOUT);
230 SpinDelayUs(1000);
231 } else {
232 // stop modulating antenna
233 LOW(GPIO_SSC_DOUT);
234 SpinDelayUs(300);
235 // modulate antenna
236 HIGH(GPIO_SSC_DOUT);
237 SpinDelayUs(1700);
238 }
239 }
240 }
241
242 void AcquireTiType(void)
243 {
244 int i, j, n;
245 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
246 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
247 #define TIBUFLEN 1250
248
249 // clear buffer
250 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
251 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
252
253 // Set up the synchronous serial port
254 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
255 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
256
257 // steal this pin from the SSP and use it to control the modulation
258 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
259 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
260
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
262 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
263
264 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
265 // 48/2 = 24 MHz clock must be divided by 12
266 AT91C_BASE_SSC->SSC_CMR = 12;
267
268 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
269 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
270 AT91C_BASE_SSC->SSC_TCMR = 0;
271 AT91C_BASE_SSC->SSC_TFMR = 0;
272
273 LED_D_ON();
274
275 // modulate antenna
276 HIGH(GPIO_SSC_DOUT);
277
278 // Charge TI tag for 50ms.
279 SpinDelay(50);
280
281 // stop modulating antenna and listen
282 LOW(GPIO_SSC_DOUT);
283
284 LED_D_OFF();
285
286 i = 0;
287 for(;;) {
288 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
289 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
290 i++; if(i >= TIBUFLEN) break;
291 }
292 WDT_HIT();
293 }
294
295 // return stolen pin to SSP
296 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
297 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
298
299 char *dest = (char *)BigBuf_get_addr();
300 n = TIBUFLEN*32;
301 // unpack buffer
302 for (i=TIBUFLEN-1; i>=0; i--) {
303 for (j=0; j<32; j++) {
304 if(BigBuf[i] & (1 << j)) {
305 dest[--n] = 1;
306 } else {
307 dest[--n] = -1;
308 }
309 }
310 }
311 }
312
313 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
314 // if crc provided, it will be written with the data verbatim (even if bogus)
315 // if not provided a valid crc will be computed from the data and written.
316 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
317 {
318 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
319 if(crc == 0) {
320 crc = update_crc16(crc, (idlo)&0xff);
321 crc = update_crc16(crc, (idlo>>8)&0xff);
322 crc = update_crc16(crc, (idlo>>16)&0xff);
323 crc = update_crc16(crc, (idlo>>24)&0xff);
324 crc = update_crc16(crc, (idhi)&0xff);
325 crc = update_crc16(crc, (idhi>>8)&0xff);
326 crc = update_crc16(crc, (idhi>>16)&0xff);
327 crc = update_crc16(crc, (idhi>>24)&0xff);
328 }
329 Dbprintf("Writing to tag: %x%08x, crc=%x",
330 (unsigned int) idhi, (unsigned int) idlo, crc);
331
332 // TI tags charge at 134.2Khz
333 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
334 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
335 // connects to SSP_DIN and the SSP_DOUT logic level controls
336 // whether we're modulating the antenna (high)
337 // or listening to the antenna (low)
338 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
339 LED_A_ON();
340
341 // steal this pin from the SSP and use it to control the modulation
342 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
343 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
344
345 // writing algorithm:
346 // a high bit consists of a field off for 1ms and field on for 1ms
347 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
348 // initiate a charge time of 50ms (field on) then immediately start writing bits
349 // start by writing 0xBB (keyword) and 0xEB (password)
350 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
351 // finally end with 0x0300 (write frame)
352 // all data is sent lsb firts
353 // finish with 15ms programming time
354
355 // modulate antenna
356 HIGH(GPIO_SSC_DOUT);
357 SpinDelay(50); // charge time
358
359 WriteTIbyte(0xbb); // keyword
360 WriteTIbyte(0xeb); // password
361 WriteTIbyte( (idlo )&0xff );
362 WriteTIbyte( (idlo>>8 )&0xff );
363 WriteTIbyte( (idlo>>16)&0xff );
364 WriteTIbyte( (idlo>>24)&0xff );
365 WriteTIbyte( (idhi )&0xff );
366 WriteTIbyte( (idhi>>8 )&0xff );
367 WriteTIbyte( (idhi>>16)&0xff );
368 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
369 WriteTIbyte( (crc )&0xff ); // crc lo
370 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
371 WriteTIbyte(0x00); // write frame lo
372 WriteTIbyte(0x03); // write frame hi
373 HIGH(GPIO_SSC_DOUT);
374 SpinDelay(50); // programming time
375
376 LED_A_OFF();
377
378 // get TI tag data into the buffer
379 AcquireTiType();
380
381 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
382 DbpString("Now use 'lf ti read' to check");
383 }
384
385 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
386 {
387 int i;
388 uint8_t *tab = BigBuf_get_addr();
389
390 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
391 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
392
393 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
394
395 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
396 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
397
398 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
399 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
400
401 i = 0;
402 for(;;) {
403 //wait until SSC_CLK goes HIGH
404 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
405 if(BUTTON_PRESS() || (usb_poll_validate_length() )) {
406 DbpString("Stopped");
407 return;
408 }
409 WDT_HIT();
410 }
411 if (ledcontrol)
412 LED_D_ON();
413
414 if(tab[i])
415 OPEN_COIL();
416 else
417 SHORT_COIL();
418
419 if (ledcontrol)
420 LED_D_OFF();
421 //wait until SSC_CLK goes LOW
422 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
423 if(BUTTON_PRESS()) {
424 DbpString("Stopped");
425 return;
426 }
427 WDT_HIT();
428 }
429
430 i++;
431 if(i == period) {
432
433 i = 0;
434 if (gap) {
435 SHORT_COIL();
436 SpinDelayUs(gap);
437 }
438 }
439 }
440 }
441
442 #define DEBUG_FRAME_CONTENTS 1
443 void SimulateTagLowFrequencyBidir(int divisor, int t0)
444 {
445 }
446
447 // compose fc/8 fc/10 waveform (FSK2)
448 static void fc(int c, int *n)
449 {
450 uint8_t *dest = BigBuf_get_addr();
451 int idx;
452
453 // for when we want an fc8 pattern every 4 logical bits
454 if(c==0) {
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=1;
458 dest[((*n)++)]=1;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 dest[((*n)++)]=0;
462 dest[((*n)++)]=0;
463 }
464
465 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
466 if(c==8) {
467 for (idx=0; idx<6; idx++) {
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=1;
471 dest[((*n)++)]=1;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 dest[((*n)++)]=0;
475 dest[((*n)++)]=0;
476 }
477 }
478
479 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
480 if(c==10) {
481 for (idx=0; idx<5; idx++) {
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=1;
486 dest[((*n)++)]=1;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 dest[((*n)++)]=0;
491 dest[((*n)++)]=0;
492 }
493 }
494 }
495 // compose fc/X fc/Y waveform (FSKx)
496 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
497 {
498 uint8_t *dest = BigBuf_get_addr();
499 uint8_t halfFC = fc/2;
500 uint8_t wavesPerClock = clock/fc;
501 uint8_t mod = clock % fc; //modifier
502 uint8_t modAdj = fc/mod; //how often to apply modifier
503 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
504 // loop through clock - step field clock
505 for (uint8_t idx=0; idx < wavesPerClock; idx++){
506 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
507 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
508 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
509 *n += fc;
510 }
511 if (mod>0) (*modCnt)++;
512 if ((mod>0) && modAdjOk){ //fsk2
513 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
514 memset(dest+(*n), 0, fc-halfFC);
515 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
516 *n += fc;
517 }
518 }
519 if (mod>0 && !modAdjOk){ //fsk1
520 memset(dest+(*n), 0, mod-(mod/2));
521 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
522 *n += mod;
523 }
524 }
525
526 // prepare a waveform pattern in the buffer based on the ID given then
527 // simulate a HID tag until the button is pressed
528 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
529 {
530 int n=0, i=0;
531 /*
532 HID tag bitstream format
533 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
534 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
535 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
536 A fc8 is inserted before every 4 bits
537 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
538 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
539 */
540
541 if (hi>0xFFF) {
542 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
543 return;
544 }
545 fc(0,&n);
546 // special start of frame marker containing invalid bit sequences
547 fc(8, &n); fc(8, &n); // invalid
548 fc(8, &n); fc(10, &n); // logical 0
549 fc(10, &n); fc(10, &n); // invalid
550 fc(8, &n); fc(10, &n); // logical 0
551
552 WDT_HIT();
553 // manchester encode bits 43 to 32
554 for (i=11; i>=0; i--) {
555 if ((i%4)==3) fc(0,&n);
556 if ((hi>>i)&1) {
557 fc(10, &n); fc(8, &n); // low-high transition
558 } else {
559 fc(8, &n); fc(10, &n); // high-low transition
560 }
561 }
562
563 WDT_HIT();
564 // manchester encode bits 31 to 0
565 for (i=31; i>=0; i--) {
566 if ((i%4)==3) fc(0,&n);
567 if ((lo>>i)&1) {
568 fc(10, &n); fc(8, &n); // low-high transition
569 } else {
570 fc(8, &n); fc(10, &n); // high-low transition
571 }
572 }
573
574 if (ledcontrol)
575 LED_A_ON();
576 SimulateTagLowFrequency(n, 0, ledcontrol);
577
578 if (ledcontrol)
579 LED_A_OFF();
580 }
581
582 // prepare a waveform pattern in the buffer based on the ID given then
583 // simulate a FSK tag until the button is pressed
584 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
585 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
586 {
587 int ledcontrol=1;
588 int n=0, i=0;
589 uint8_t fcHigh = arg1 >> 8;
590 uint8_t fcLow = arg1 & 0xFF;
591 uint16_t modCnt = 0;
592 uint8_t clk = arg2 & 0xFF;
593 uint8_t invert = (arg2 >> 8) & 1;
594
595 for (i=0; i<size; i++){
596 if (BitStream[i] == invert){
597 fcAll(fcLow, &n, clk, &modCnt);
598 } else {
599 fcAll(fcHigh, &n, clk, &modCnt);
600 }
601 }
602 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
603 /*Dbprintf("DEBUG: First 32:");
604 uint8_t *dest = BigBuf_get_addr();
605 i=0;
606 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
607 i+=16;
608 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
609 */
610 if (ledcontrol)
611 LED_A_ON();
612
613 SimulateTagLowFrequency(n, 0, ledcontrol);
614
615 if (ledcontrol)
616 LED_A_OFF();
617 }
618
619 // compose ask waveform for one bit(ASK)
620 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
621 {
622 uint8_t *dest = BigBuf_get_addr();
623 uint8_t halfClk = clock/2;
624 // c = current bit 1 or 0
625 if (manchester==1){
626 memset(dest+(*n), c, halfClk);
627 memset(dest+(*n) + halfClk, c^1, halfClk);
628 } else {
629 memset(dest+(*n), c, clock);
630 }
631 *n += clock;
632 }
633
634 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
635 {
636 uint8_t *dest = BigBuf_get_addr();
637 uint8_t halfClk = clock/2;
638 if (c){
639 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
640 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
641 } else {
642 memset(dest+(*n), c ^ *phase, clock);
643 *phase ^= 1;
644 }
645
646 }
647
648 // args clock, ask/man or askraw, invert, transmission separator
649 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
650 {
651 int ledcontrol = 1;
652 int n=0, i=0;
653 uint8_t clk = (arg1 >> 8) & 0xFF;
654 uint8_t encoding = arg1 & 0xFF;
655 uint8_t separator = arg2 & 1;
656 uint8_t invert = (arg2 >> 8) & 1;
657
658 if (encoding==2){ //biphase
659 uint8_t phase=0;
660 for (i=0; i<size; i++){
661 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
662 }
663 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
664 for (i=0; i<size; i++){
665 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
666 }
667 }
668 } else { // ask/manchester || ask/raw
669 for (i=0; i<size; i++){
670 askSimBit(BitStream[i]^invert, &n, clk, encoding);
671 }
672 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
673 for (i=0; i<size; i++){
674 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
675 }
676 }
677 }
678
679 if (separator==1) Dbprintf("sorry but separator option not yet available");
680
681 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
682 //DEBUG
683 //Dbprintf("First 32:");
684 //uint8_t *dest = BigBuf_get_addr();
685 //i=0;
686 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
687 //i+=16;
688 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
689
690 if (ledcontrol)
691 LED_A_ON();
692
693 SimulateTagLowFrequency(n, 0, ledcontrol);
694
695 if (ledcontrol)
696 LED_A_OFF();
697 }
698
699 //carrier can be 2,4 or 8
700 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
701 {
702 uint8_t *dest = BigBuf_get_addr();
703 uint8_t halfWave = waveLen/2;
704 //uint8_t idx;
705 int i = 0;
706 if (phaseChg){
707 // write phase change
708 memset(dest+(*n), *curPhase^1, halfWave);
709 memset(dest+(*n) + halfWave, *curPhase, halfWave);
710 *n += waveLen;
711 *curPhase ^= 1;
712 i += waveLen;
713 }
714 //write each normal clock wave for the clock duration
715 for (; i < clk; i+=waveLen){
716 memset(dest+(*n), *curPhase, halfWave);
717 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
718 *n += waveLen;
719 }
720 }
721
722 // args clock, carrier, invert,
723 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
724 {
725 int ledcontrol=1;
726 int n=0, i=0;
727 uint8_t clk = arg1 >> 8;
728 uint8_t carrier = arg1 & 0xFF;
729 uint8_t invert = arg2 & 0xFF;
730 uint8_t curPhase = 0;
731 for (i=0; i<size; i++){
732 if (BitStream[i] == curPhase){
733 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
734 } else {
735 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
736 }
737 }
738 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
739 //Dbprintf("DEBUG: First 32:");
740 //uint8_t *dest = BigBuf_get_addr();
741 //i=0;
742 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
743 //i+=16;
744 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
745
746 if (ledcontrol)
747 LED_A_ON();
748 SimulateTagLowFrequency(n, 0, ledcontrol);
749
750 if (ledcontrol)
751 LED_A_OFF();
752 }
753
754 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
755 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
756 {
757 uint8_t *dest = BigBuf_get_addr();
758 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
759 size_t size = 0;
760 uint32_t hi2=0, hi=0, lo=0;
761 int idx=0;
762 // Configure to go in 125Khz listen mode
763 LFSetupFPGAForADC(95, true);
764
765 while(!BUTTON_PRESS()) {
766
767 WDT_HIT();
768 if (ledcontrol) LED_A_ON();
769
770 DoAcquisition_default(-1,true);
771 // FSK demodulator
772 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
773 size = 50*128*2; //big enough to catch 2 sequences of largest format
774 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
775
776 if (idx>0 && lo>0 && (size==96 || size==192)){
777 // go over previously decoded manchester data and decode into usable tag ID
778 if (hi2 != 0){ //extra large HID tags 88/192 bits
779 Dbprintf("TAG ID: %x%08x%08x (%d)",
780 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
781 }else { //standard HID tags 44/96 bits
782 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
783 uint8_t bitlen = 0;
784 uint32_t fc = 0;
785 uint32_t cardnum = 0;
786 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
787 uint32_t lo2=0;
788 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
789 uint8_t idx3 = 1;
790 while(lo2 > 1){ //find last bit set to 1 (format len bit)
791 lo2=lo2 >> 1;
792 idx3++;
793 }
794 bitlen = idx3+19;
795 fc =0;
796 cardnum=0;
797 if(bitlen == 26){
798 cardnum = (lo>>1)&0xFFFF;
799 fc = (lo>>17)&0xFF;
800 }
801 if(bitlen == 37){
802 cardnum = (lo>>1)&0x7FFFF;
803 fc = ((hi&0xF)<<12)|(lo>>20);
804 }
805 if(bitlen == 34){
806 cardnum = (lo>>1)&0xFFFF;
807 fc= ((hi&1)<<15)|(lo>>17);
808 }
809 if(bitlen == 35){
810 cardnum = (lo>>1)&0xFFFFF;
811 fc = ((hi&1)<<11)|(lo>>21);
812 }
813 }
814 else { //if bit 38 is not set then 37 bit format is used
815 bitlen= 37;
816 fc =0;
817 cardnum=0;
818 if(bitlen==37){
819 cardnum = (lo>>1)&0x7FFFF;
820 fc = ((hi&0xF)<<12)|(lo>>20);
821 }
822 }
823 //Dbprintf("TAG ID: %x%08x (%d)",
824 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
825 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
826 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
827 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
828 }
829 if (findone){
830 if (ledcontrol) LED_A_OFF();
831 *high = hi;
832 *low = lo;
833 return;
834 }
835 // reset
836 }
837 hi2 = hi = lo = idx = 0;
838 WDT_HIT();
839 }
840 DbpString("Stopped");
841 if (ledcontrol) LED_A_OFF();
842 }
843
844 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
845 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
846 {
847 uint8_t *dest = BigBuf_get_addr();
848 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
849 size_t size;
850 int idx=0;
851 // Configure to go in 125Khz listen mode
852 LFSetupFPGAForADC(95, true);
853
854 while(!BUTTON_PRESS()) {
855
856 WDT_HIT();
857 if (ledcontrol) LED_A_ON();
858
859 DoAcquisition_default(-1,true);
860 // FSK demodulator
861 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
862 size = 50*128*2; //big enough to catch 2 sequences of largest format
863 idx = AWIDdemodFSK(dest, &size);
864
865 if (idx>0 && size==96){
866 // Index map
867 // 0 10 20 30 40 50 60
868 // | | | | | | |
869 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
870 // -----------------------------------------------------------------------------
871 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
872 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
873 // |---26 bit---| |-----117----||-------------142-------------|
874 // b = format bit len, o = odd parity of last 3 bits
875 // f = facility code, c = card number
876 // w = wiegand parity
877 // (26 bit format shown)
878
879 //get raw ID before removing parities
880 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
881 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
882 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
883
884 size = removeParity(dest, idx+8, 4, 1, 88);
885 // ok valid card found!
886
887 // Index map
888 // 0 10 20 30 40 50 60
889 // | | | | | | |
890 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
891 // -----------------------------------------------------------------------------
892 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
893 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
894 // |26 bit| |-117--| |-----142------|
895 // b = format bit len, o = odd parity of last 3 bits
896 // f = facility code, c = card number
897 // w = wiegand parity
898 // (26 bit format shown)
899
900 uint32_t fc = 0;
901 uint32_t cardnum = 0;
902 uint32_t code1 = 0;
903 uint32_t code2 = 0;
904 uint8_t fmtLen = bytebits_to_byte(dest,8);
905 if (fmtLen==26){
906 fc = bytebits_to_byte(dest+9, 8);
907 cardnum = bytebits_to_byte(dest+17, 16);
908 code1 = bytebits_to_byte(dest+8,fmtLen);
909 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
910 } else {
911 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
912 if (fmtLen>32){
913 code1 = bytebits_to_byte(dest+8,fmtLen-32);
914 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
915 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
916 } else{
917 code1 = bytebits_to_byte(dest+8,fmtLen);
918 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
919 }
920 }
921 if (findone){
922 if (ledcontrol) LED_A_OFF();
923 return;
924 }
925 // reset
926 }
927 idx = 0;
928 WDT_HIT();
929 }
930 DbpString("Stopped");
931 if (ledcontrol) LED_A_OFF();
932 }
933
934 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
935 {
936 uint8_t *dest = BigBuf_get_addr();
937
938 size_t size=0, idx=0;
939 int clk=0, invert=0, errCnt=0, maxErr=20;
940 uint32_t hi=0;
941 uint64_t lo=0;
942 // Configure to go in 125Khz listen mode
943 LFSetupFPGAForADC(95, true);
944
945 while(!BUTTON_PRESS()) {
946
947 WDT_HIT();
948 if (ledcontrol) LED_A_ON();
949
950 DoAcquisition_default(-1,true);
951 size = BigBuf_max_traceLen();
952 //askdemod and manchester decode
953 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
954 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
955 WDT_HIT();
956
957 if (errCnt<0) continue;
958
959 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
960 if (errCnt){
961 if (size>64){
962 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
963 hi,
964 (uint32_t)(lo>>32),
965 (uint32_t)lo,
966 (uint32_t)(lo&0xFFFF),
967 (uint32_t)((lo>>16LL) & 0xFF),
968 (uint32_t)(lo & 0xFFFFFF));
969 } else {
970 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
971 (uint32_t)(lo>>32),
972 (uint32_t)lo,
973 (uint32_t)(lo&0xFFFF),
974 (uint32_t)((lo>>16LL) & 0xFF),
975 (uint32_t)(lo & 0xFFFFFF));
976 }
977
978 if (findone){
979 if (ledcontrol) LED_A_OFF();
980 *high=lo>>32;
981 *low=lo & 0xFFFFFFFF;
982 return;
983 }
984 }
985 WDT_HIT();
986 hi = lo = size = idx = 0;
987 clk = invert = errCnt = 0;
988 }
989 DbpString("Stopped");
990 if (ledcontrol) LED_A_OFF();
991 }
992
993 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
994 {
995 uint8_t *dest = BigBuf_get_addr();
996 int idx=0;
997 uint32_t code=0, code2=0;
998 uint8_t version=0;
999 uint8_t facilitycode=0;
1000 uint16_t number=0;
1001 uint8_t crc = 0;
1002 uint16_t calccrc = 0;
1003 // Configure to go in 125Khz listen mode
1004 LFSetupFPGAForADC(95, true);
1005
1006 while(!BUTTON_PRESS()) {
1007 WDT_HIT();
1008 if (ledcontrol) LED_A_ON();
1009 DoAcquisition_default(-1,true);
1010 //fskdemod and get start index
1011 WDT_HIT();
1012 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
1013 if (idx<0) continue;
1014 //valid tag found
1015
1016 //Index map
1017 //0 10 20 30 40 50 60
1018 //| | | | | | |
1019 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1020 //-----------------------------------------------------------------------------
1021 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
1022 //
1023 //Checksum:
1024 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
1025 //preamble F0 E0 01 03 B6 75
1026 // How to calc checksum,
1027 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
1028 // F0 + E0 + 01 + 03 + B6 = 28A
1029 // 28A & FF = 8A
1030 // FF - 8A = 75
1031 // Checksum: 0x75
1032 //XSF(version)facility:codeone+codetwo
1033 //Handle the data
1034 if(findone){ //only print binary if we are doing one
1035 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1036 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1037 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1038 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1039 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1040 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1041 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1042 }
1043 code = bytebits_to_byte(dest+idx,32);
1044 code2 = bytebits_to_byte(dest+idx+32,32);
1045 version = bytebits_to_byte(dest+idx+27,8); //14,4
1046 facilitycode = bytebits_to_byte(dest+idx+18,8);
1047 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1048
1049 crc = bytebits_to_byte(dest+idx+54,8);
1050 for (uint8_t i=1; i<6; ++i)
1051 calccrc += bytebits_to_byte(dest+idx+9*i,8);
1052 calccrc &= 0xff;
1053 calccrc = 0xff - calccrc;
1054
1055 char *crcStr = (crc == calccrc) ? "ok":"!crc";
1056
1057 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
1058 // if we're only looking for one tag
1059 if (findone){
1060 if (ledcontrol) LED_A_OFF();
1061 //LED_A_OFF();
1062 *high=code;
1063 *low=code2;
1064 return;
1065 }
1066 code=code2=0;
1067 version=facilitycode=0;
1068 number=0;
1069 idx=0;
1070
1071 WDT_HIT();
1072 }
1073 DbpString("Stopped");
1074 if (ledcontrol) LED_A_OFF();
1075 }
1076
1077 /*------------------------------
1078 * T5555/T5557/T5567 routines
1079 *------------------------------
1080 */
1081
1082 /* T55x7 configuration register definitions */
1083 #define T55x7_POR_DELAY 0x00000001
1084 #define T55x7_ST_TERMINATOR 0x00000008
1085 #define T55x7_PWD 0x00000010
1086 #define T55x7_MAXBLOCK_SHIFT 5
1087 #define T55x7_AOR 0x00000200
1088 #define T55x7_PSKCF_RF_2 0
1089 #define T55x7_PSKCF_RF_4 0x00000400
1090 #define T55x7_PSKCF_RF_8 0x00000800
1091 #define T55x7_MODULATION_DIRECT 0
1092 #define T55x7_MODULATION_PSK1 0x00001000
1093 #define T55x7_MODULATION_PSK2 0x00002000
1094 #define T55x7_MODULATION_PSK3 0x00003000
1095 #define T55x7_MODULATION_FSK1 0x00004000
1096 #define T55x7_MODULATION_FSK2 0x00005000
1097 #define T55x7_MODULATION_FSK1a 0x00006000
1098 #define T55x7_MODULATION_FSK2a 0x00007000
1099 #define T55x7_MODULATION_MANCHESTER 0x00008000
1100 #define T55x7_MODULATION_BIPHASE 0x00010000
1101 #define T55x7_BITRATE_RF_8 0
1102 #define T55x7_BITRATE_RF_16 0x00040000
1103 #define T55x7_BITRATE_RF_32 0x00080000
1104 #define T55x7_BITRATE_RF_40 0x000C0000
1105 #define T55x7_BITRATE_RF_50 0x00100000
1106 #define T55x7_BITRATE_RF_64 0x00140000
1107 #define T55x7_BITRATE_RF_100 0x00180000
1108 #define T55x7_BITRATE_RF_128 0x001C0000
1109
1110 /* T5555 (Q5) configuration register definitions */
1111 #define T5555_ST_TERMINATOR 0x00000001
1112 #define T5555_MAXBLOCK_SHIFT 0x00000001
1113 #define T5555_MODULATION_MANCHESTER 0
1114 #define T5555_MODULATION_PSK1 0x00000010
1115 #define T5555_MODULATION_PSK2 0x00000020
1116 #define T5555_MODULATION_PSK3 0x00000030
1117 #define T5555_MODULATION_FSK1 0x00000040
1118 #define T5555_MODULATION_FSK2 0x00000050
1119 #define T5555_MODULATION_BIPHASE 0x00000060
1120 #define T5555_MODULATION_DIRECT 0x00000070
1121 #define T5555_INVERT_OUTPUT 0x00000080
1122 #define T5555_PSK_RF_2 0
1123 #define T5555_PSK_RF_4 0x00000100
1124 #define T5555_PSK_RF_8 0x00000200
1125 #define T5555_USE_PWD 0x00000400
1126 #define T5555_USE_AOR 0x00000800
1127 #define T5555_BITRATE_SHIFT 12
1128 #define T5555_FAST_WRITE 0x00004000
1129 #define T5555_PAGE_SELECT 0x00008000
1130
1131 /*
1132 * Relevant times in microsecond
1133 * To compensate antenna falling times shorten the write times
1134 * and enlarge the gap ones.
1135 */
1136 #define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
1137 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
1138 #define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
1139 #define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
1140
1141 // VALUES TAKEN FROM EM4x function: SendForward
1142 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1143 // WRITE_GAP = 128; (16*8)
1144 // WRITE_1 = 256 32*8; (32*8)
1145
1146 // These timings work for 4469/4269/4305 (with the 55*8 above)
1147 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1148
1149 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1150 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1151 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1152 // T0 = TIMER_CLOCK1 / 125000 = 192
1153 // 1 Cycle = 8 microseconds(us)
1154
1155 #define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
1156
1157 // Write one bit to card
1158 void T55xxWriteBit(int bit)
1159 {
1160 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1161 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1162 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1163 if (!bit)
1164 SpinDelayUs(WRITE_0);
1165 else
1166 SpinDelayUs(WRITE_1);
1167 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1168 SpinDelayUs(WRITE_GAP);
1169 }
1170
1171 // Write one card block in page 0, no lock
1172 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1173 {
1174 uint32_t i = 0;
1175
1176 // Set up FPGA, 125kHz
1177 // Wait for config.. (192+8190xPOW)x8 == 67ms
1178 LFSetupFPGAForADC(0, true);
1179
1180 // Now start writting
1181 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1182 SpinDelayUs(START_GAP);
1183
1184 // Opcode
1185 T55xxWriteBit(1);
1186 T55xxWriteBit(0); //Page 0
1187 if (PwdMode == 1){
1188 // Pwd
1189 for (i = 0x80000000; i != 0; i >>= 1)
1190 T55xxWriteBit(Pwd & i);
1191 }
1192 // Lock bit
1193 T55xxWriteBit(0);
1194
1195 // Data
1196 for (i = 0x80000000; i != 0; i >>= 1)
1197 T55xxWriteBit(Data & i);
1198
1199 // Block
1200 for (i = 0x04; i != 0; i >>= 1)
1201 T55xxWriteBit(Block & i);
1202
1203 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1204 // so wait a little more)
1205 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1206 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1207 SpinDelay(20);
1208 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1209 }
1210
1211 void TurnReadLFOn(){
1212 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1213 // Give it a bit of time for the resonant antenna to settle.
1214 SpinDelayUs(8*150);
1215 }
1216
1217
1218 // Read one card block in page 0
1219 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1220 {
1221 uint32_t i = 0;
1222 uint8_t *dest = BigBuf_get_addr();
1223 uint16_t bufferlength = BigBuf_max_traceLen();
1224 if ( bufferlength > T55xx_SAMPLES_SIZE )
1225 bufferlength = T55xx_SAMPLES_SIZE;
1226
1227 // Clear destination buffer before sending the command
1228 memset(dest, 0x80, bufferlength);
1229
1230 // Set up FPGA, 125kHz
1231 // Wait for config.. (192+8190xPOW)x8 == 67ms
1232 LFSetupFPGAForADC(0, true);
1233 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1234 SpinDelayUs(START_GAP);
1235
1236 // Opcode
1237 T55xxWriteBit(1);
1238 T55xxWriteBit(0); //Page 0
1239 if (PwdMode == 1){
1240 // Pwd
1241 for (i = 0x80000000; i != 0; i >>= 1)
1242 T55xxWriteBit(Pwd & i);
1243 }
1244 // Lock bit
1245 T55xxWriteBit(0);
1246 // Block
1247 for (i = 0x04; i != 0; i >>= 1)
1248 T55xxWriteBit(Block & i);
1249
1250 // Turn field on to read the response
1251 TurnReadLFOn();
1252 // Now do the acquisition
1253 i = 0;
1254 for(;;) {
1255 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1256 AT91C_BASE_SSC->SSC_THR = 0x43;
1257 LED_D_ON();
1258 }
1259 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1260 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1261 i++;
1262 LED_D_OFF();
1263 if (i >= bufferlength) break;
1264 }
1265 }
1266
1267 cmd_send(CMD_ACK,0,0,0,0,0);
1268 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1269 LED_D_OFF();
1270 }
1271
1272 // Read card traceability data (page 1)
1273 void T55xxReadTrace(void){
1274
1275 uint32_t i = 0;
1276 uint8_t *dest = BigBuf_get_addr();
1277 uint16_t bufferlength = BigBuf_max_traceLen();
1278 if ( bufferlength > T55xx_SAMPLES_SIZE )
1279 bufferlength= T55xx_SAMPLES_SIZE;
1280
1281 // Clear destination buffer before sending the command
1282 memset(dest, 0x80, bufferlength);
1283
1284 LFSetupFPGAForADC(0, true);
1285 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1286 SpinDelayUs(START_GAP);
1287
1288 // Opcode
1289 T55xxWriteBit(1);
1290 T55xxWriteBit(1); //Page 1
1291
1292 // Turn field on to read the response
1293 TurnReadLFOn();
1294
1295 // Now do the acquisition
1296 for(;;) {
1297 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1298 AT91C_BASE_SSC->SSC_THR = 0x43;
1299 LED_D_ON();
1300 }
1301 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1302 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1303 i++;
1304 LED_D_OFF();
1305
1306 if (i >= bufferlength) break;
1307 }
1308 }
1309
1310 cmd_send(CMD_ACK,0,0,0,0,0);
1311 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1312 LED_D_OFF();
1313 }
1314
1315 /*-------------- Cloning routines -----------*/
1316 // Copy HID id to card and setup block 0 config
1317 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1318 {
1319 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1320 int last_block = 0;
1321
1322 if (longFMT){
1323 // Ensure no more than 84 bits supplied
1324 if (hi2>0xFFFFF) {
1325 DbpString("Tags can only have 84 bits.");
1326 return;
1327 }
1328 // Build the 6 data blocks for supplied 84bit ID
1329 last_block = 6;
1330 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1331 for (int i=0;i<4;i++) {
1332 if (hi2 & (1<<(19-i)))
1333 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1334 else
1335 data1 |= (1<<((3-i)*2)); // 0 -> 01
1336 }
1337
1338 data2 = 0;
1339 for (int i=0;i<16;i++) {
1340 if (hi2 & (1<<(15-i)))
1341 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1342 else
1343 data2 |= (1<<((15-i)*2)); // 0 -> 01
1344 }
1345
1346 data3 = 0;
1347 for (int i=0;i<16;i++) {
1348 if (hi & (1<<(31-i)))
1349 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1350 else
1351 data3 |= (1<<((15-i)*2)); // 0 -> 01
1352 }
1353
1354 data4 = 0;
1355 for (int i=0;i<16;i++) {
1356 if (hi & (1<<(15-i)))
1357 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1358 else
1359 data4 |= (1<<((15-i)*2)); // 0 -> 01
1360 }
1361
1362 data5 = 0;
1363 for (int i=0;i<16;i++) {
1364 if (lo & (1<<(31-i)))
1365 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1366 else
1367 data5 |= (1<<((15-i)*2)); // 0 -> 01
1368 }
1369
1370 data6 = 0;
1371 for (int i=0;i<16;i++) {
1372 if (lo & (1<<(15-i)))
1373 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1374 else
1375 data6 |= (1<<((15-i)*2)); // 0 -> 01
1376 }
1377 }
1378 else {
1379 // Ensure no more than 44 bits supplied
1380 if (hi>0xFFF) {
1381 DbpString("Tags can only have 44 bits.");
1382 return;
1383 }
1384
1385 // Build the 3 data blocks for supplied 44bit ID
1386 last_block = 3;
1387
1388 data1 = 0x1D000000; // load preamble
1389
1390 for (int i=0;i<12;i++) {
1391 if (hi & (1<<(11-i)))
1392 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1393 else
1394 data1 |= (1<<((11-i)*2)); // 0 -> 01
1395 }
1396
1397 data2 = 0;
1398 for (int i=0;i<16;i++) {
1399 if (lo & (1<<(31-i)))
1400 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1401 else
1402 data2 |= (1<<((15-i)*2)); // 0 -> 01
1403 }
1404
1405 data3 = 0;
1406 for (int i=0;i<16;i++) {
1407 if (lo & (1<<(15-i)))
1408 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1409 else
1410 data3 |= (1<<((15-i)*2)); // 0 -> 01
1411 }
1412 }
1413
1414 LED_D_ON();
1415 // Program the data blocks for supplied ID
1416 // and the block 0 for HID format
1417 T55xxWriteBlock(data1,1,0,0);
1418 T55xxWriteBlock(data2,2,0,0);
1419 T55xxWriteBlock(data3,3,0,0);
1420
1421 if (longFMT) { // if long format there are 6 blocks
1422 T55xxWriteBlock(data4,4,0,0);
1423 T55xxWriteBlock(data5,5,0,0);
1424 T55xxWriteBlock(data6,6,0,0);
1425 }
1426
1427 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1428 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1429 T55x7_MODULATION_FSK2a |
1430 last_block << T55x7_MAXBLOCK_SHIFT,
1431 0,0,0);
1432
1433 LED_D_OFF();
1434
1435 DbpString("DONE!");
1436 }
1437
1438 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1439 {
1440 int data1=0, data2=0; //up to six blocks for long format
1441
1442 data1 = hi; // load preamble
1443 data2 = lo;
1444
1445 LED_D_ON();
1446 // Program the data blocks for supplied ID
1447 // and the block 0 for HID format
1448 T55xxWriteBlock(data1,1,0,0);
1449 T55xxWriteBlock(data2,2,0,0);
1450
1451 //Config Block
1452 T55xxWriteBlock(0x00147040,0,0,0);
1453 LED_D_OFF();
1454
1455 DbpString("DONE!");
1456 }
1457
1458 // Define 9bit header for EM410x tags
1459 #define EM410X_HEADER 0x1FF
1460 #define EM410X_ID_LENGTH 40
1461
1462 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1463 {
1464 int i, id_bit;
1465 uint64_t id = EM410X_HEADER;
1466 uint64_t rev_id = 0; // reversed ID
1467 int c_parity[4]; // column parity
1468 int r_parity = 0; // row parity
1469 uint32_t clock = 0;
1470
1471 // Reverse ID bits given as parameter (for simpler operations)
1472 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1473 if (i < 32) {
1474 rev_id = (rev_id << 1) | (id_lo & 1);
1475 id_lo >>= 1;
1476 } else {
1477 rev_id = (rev_id << 1) | (id_hi & 1);
1478 id_hi >>= 1;
1479 }
1480 }
1481
1482 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1483 id_bit = rev_id & 1;
1484
1485 if (i % 4 == 0) {
1486 // Don't write row parity bit at start of parsing
1487 if (i)
1488 id = (id << 1) | r_parity;
1489 // Start counting parity for new row
1490 r_parity = id_bit;
1491 } else {
1492 // Count row parity
1493 r_parity ^= id_bit;
1494 }
1495
1496 // First elements in column?
1497 if (i < 4)
1498 // Fill out first elements
1499 c_parity[i] = id_bit;
1500 else
1501 // Count column parity
1502 c_parity[i % 4] ^= id_bit;
1503
1504 // Insert ID bit
1505 id = (id << 1) | id_bit;
1506 rev_id >>= 1;
1507 }
1508
1509 // Insert parity bit of last row
1510 id = (id << 1) | r_parity;
1511
1512 // Fill out column parity at the end of tag
1513 for (i = 0; i < 4; ++i)
1514 id = (id << 1) | c_parity[i];
1515
1516 // Add stop bit
1517 id <<= 1;
1518
1519 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1520 LED_D_ON();
1521
1522 // Write EM410x ID
1523 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1524 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1525
1526 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1527 if (card) {
1528 // Clock rate is stored in bits 8-15 of the card value
1529 clock = (card & 0xFF00) >> 8;
1530 Dbprintf("Clock rate: %d", clock);
1531 switch (clock)
1532 {
1533 case 32:
1534 clock = T55x7_BITRATE_RF_32;
1535 break;
1536 case 16:
1537 clock = T55x7_BITRATE_RF_16;
1538 break;
1539 case 0:
1540 // A value of 0 is assumed to be 64 for backwards-compatibility
1541 // Fall through...
1542 case 64:
1543 clock = T55x7_BITRATE_RF_64;
1544 break;
1545 default:
1546 Dbprintf("Invalid clock rate: %d", clock);
1547 return;
1548 }
1549
1550 // Writing configuration for T55x7 tag
1551 T55xxWriteBlock(clock |
1552 T55x7_MODULATION_MANCHESTER |
1553 2 << T55x7_MAXBLOCK_SHIFT,
1554 0, 0, 0);
1555 }
1556 else
1557 // Writing configuration for T5555(Q5) tag
1558 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1559 T5555_MODULATION_MANCHESTER |
1560 2 << T5555_MAXBLOCK_SHIFT,
1561 0, 0, 0);
1562
1563 LED_D_OFF();
1564 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1565 (uint32_t)(id >> 32), (uint32_t)id);
1566 }
1567
1568 // Clone Indala 64-bit tag by UID to T55x7
1569 void CopyIndala64toT55x7(int hi, int lo)
1570 {
1571
1572 //Program the 2 data blocks for supplied 64bit UID
1573 // and the block 0 for Indala64 format
1574 T55xxWriteBlock(hi,1,0,0);
1575 T55xxWriteBlock(lo,2,0,0);
1576 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1577 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1578 T55x7_MODULATION_PSK1 |
1579 2 << T55x7_MAXBLOCK_SHIFT,
1580 0, 0, 0);
1581 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1582 // T5567WriteBlock(0x603E1042,0);
1583
1584 DbpString("DONE!");
1585
1586 }
1587
1588 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1589 {
1590
1591 //Program the 7 data blocks for supplied 224bit UID
1592 // and the block 0 for Indala224 format
1593 T55xxWriteBlock(uid1,1,0,0);
1594 T55xxWriteBlock(uid2,2,0,0);
1595 T55xxWriteBlock(uid3,3,0,0);
1596 T55xxWriteBlock(uid4,4,0,0);
1597 T55xxWriteBlock(uid5,5,0,0);
1598 T55xxWriteBlock(uid6,6,0,0);
1599 T55xxWriteBlock(uid7,7,0,0);
1600 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1601 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1602 T55x7_MODULATION_PSK1 |
1603 7 << T55x7_MAXBLOCK_SHIFT,
1604 0,0,0);
1605 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1606 // T5567WriteBlock(0x603E10E2,0);
1607
1608 DbpString("DONE!");
1609
1610 }
1611
1612
1613 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1614 #define max(x,y) ( x<y ? y:x)
1615
1616 int DemodPCF7931(uint8_t **outBlocks) {
1617
1618 uint8_t bits[256] = {0x00};
1619 uint8_t blocks[8][16];
1620 uint8_t *dest = BigBuf_get_addr();
1621
1622 int GraphTraceLen = BigBuf_max_traceLen();
1623 if ( GraphTraceLen > 18000 )
1624 GraphTraceLen = 18000;
1625
1626
1627 int i, j, lastval, bitidx, half_switch;
1628 int clock = 64;
1629 int tolerance = clock / 8;
1630 int pmc, block_done;
1631 int lc, warnings = 0;
1632 int num_blocks = 0;
1633 int lmin=128, lmax=128;
1634 uint8_t dir;
1635
1636 LFSetupFPGAForADC(95, true);
1637 DoAcquisition_default(0, true);
1638
1639 lmin = 64;
1640 lmax = 192;
1641
1642 i = 2;
1643
1644 /* Find first local max/min */
1645 if(dest[1] > dest[0]) {
1646 while(i < GraphTraceLen) {
1647 if( !(dest[i] > dest[i-1]) && dest[i] > lmax)
1648 break;
1649 i++;
1650 }
1651 dir = 0;
1652 }
1653 else {
1654 while(i < GraphTraceLen) {
1655 if( !(dest[i] < dest[i-1]) && dest[i] < lmin)
1656 break;
1657 i++;
1658 }
1659 dir = 1;
1660 }
1661
1662 lastval = i++;
1663 half_switch = 0;
1664 pmc = 0;
1665 block_done = 0;
1666
1667 for (bitidx = 0; i < GraphTraceLen; i++)
1668 {
1669 if ( (dest[i-1] > dest[i] && dir == 1 && dest[i] > lmax) || (dest[i-1] < dest[i] && dir == 0 && dest[i] < lmin))
1670 {
1671 lc = i - lastval;
1672 lastval = i;
1673
1674 // Switch depending on lc length:
1675 // Tolerance is 1/8 of clock rate (arbitrary)
1676 if (abs(lc-clock/4) < tolerance) {
1677 // 16T0
1678 if((i - pmc) == lc) { /* 16T0 was previous one */
1679 /* It's a PMC ! */
1680 i += (128+127+16+32+33+16)-1;
1681 lastval = i;
1682 pmc = 0;
1683 block_done = 1;
1684 }
1685 else {
1686 pmc = i;
1687 }
1688 } else if (abs(lc-clock/2) < tolerance) {
1689 // 32TO
1690 if((i - pmc) == lc) { /* 16T0 was previous one */
1691 /* It's a PMC ! */
1692 i += (128+127+16+32+33)-1;
1693 lastval = i;
1694 pmc = 0;
1695 block_done = 1;
1696 }
1697 else if(half_switch == 1) {
1698 bits[bitidx++] = 0;
1699 half_switch = 0;
1700 }
1701 else
1702 half_switch++;
1703 } else if (abs(lc-clock) < tolerance) {
1704 // 64TO
1705 bits[bitidx++] = 1;
1706 } else {
1707 // Error
1708 warnings++;
1709 if (warnings > 10)
1710 {
1711 Dbprintf("Error: too many detection errors, aborting.");
1712 return 0;
1713 }
1714 }
1715
1716 if(block_done == 1) {
1717 if(bitidx == 128) {
1718 for(j=0; j<16; j++) {
1719 blocks[num_blocks][j] = 128*bits[j*8+7]+
1720 64*bits[j*8+6]+
1721 32*bits[j*8+5]+
1722 16*bits[j*8+4]+
1723 8*bits[j*8+3]+
1724 4*bits[j*8+2]+
1725 2*bits[j*8+1]+
1726 bits[j*8];
1727
1728 }
1729 num_blocks++;
1730 }
1731 bitidx = 0;
1732 block_done = 0;
1733 half_switch = 0;
1734 }
1735 if(i < GraphTraceLen)
1736 dir =(dest[i-1] > dest[i]) ? 0 : 1;
1737 }
1738 if(bitidx==255)
1739 bitidx=0;
1740 warnings = 0;
1741 if(num_blocks == 4) break;
1742 }
1743 memcpy(outBlocks, blocks, 16*num_blocks);
1744 return num_blocks;
1745 }
1746
1747 int IsBlock0PCF7931(uint8_t *Block) {
1748 // Assume RFU means 0 :)
1749 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1750 return 1;
1751 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1752 return 1;
1753 return 0;
1754 }
1755
1756 int IsBlock1PCF7931(uint8_t *Block) {
1757 // Assume RFU means 0 :)
1758 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1759 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1760 return 1;
1761
1762 return 0;
1763 }
1764
1765 #define ALLOC 16
1766
1767 void ReadPCF7931() {
1768 uint8_t Blocks[8][17];
1769 uint8_t tmpBlocks[4][16];
1770 int i, j, ind, ind2, n;
1771 int num_blocks = 0;
1772 int max_blocks = 8;
1773 int ident = 0;
1774 int error = 0;
1775 int tries = 0;
1776
1777 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1778
1779 do {
1780 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1781 n = DemodPCF7931((uint8_t**)tmpBlocks);
1782 if(!n)
1783 error++;
1784 if(error==10 && num_blocks == 0) {
1785 Dbprintf("Error, no tag or bad tag");
1786 return;
1787 }
1788 else if (tries==20 || error==10) {
1789 Dbprintf("Error reading the tag");
1790 Dbprintf("Here is the partial content");
1791 goto end;
1792 }
1793
1794 for(i=0; i<n; i++)
1795 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1796 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1797 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1798 if(!ident) {
1799 for(i=0; i<n; i++) {
1800 if(IsBlock0PCF7931(tmpBlocks[i])) {
1801 // Found block 0 ?
1802 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1803 // Found block 1!
1804 // \o/
1805 ident = 1;
1806 memcpy(Blocks[0], tmpBlocks[i], 16);
1807 Blocks[0][ALLOC] = 1;
1808 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1809 Blocks[1][ALLOC] = 1;
1810 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1811 // Debug print
1812 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1813 num_blocks = 2;
1814 // Handle following blocks
1815 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1816 if(j==n) j=0;
1817 if(j==i) break;
1818 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1819 Blocks[ind2][ALLOC] = 1;
1820 }
1821 break;
1822 }
1823 }
1824 }
1825 }
1826 else {
1827 for(i=0; i<n; i++) { // Look for identical block in known blocks
1828 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1829 for(j=0; j<max_blocks; j++) {
1830 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1831 // Found an identical block
1832 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1833 if(ind2 < 0)
1834 ind2 = max_blocks;
1835 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1836 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1837 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1838 Blocks[ind2][ALLOC] = 1;
1839 num_blocks++;
1840 if(num_blocks == max_blocks) goto end;
1841 }
1842 }
1843 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1844 if(ind2 > max_blocks)
1845 ind2 = 0;
1846 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1847 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1848 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1849 Blocks[ind2][ALLOC] = 1;
1850 num_blocks++;
1851 if(num_blocks == max_blocks) goto end;
1852 }
1853 }
1854 }
1855 }
1856 }
1857 }
1858 }
1859 tries++;
1860 if (BUTTON_PRESS()) return;
1861 } while (num_blocks != max_blocks);
1862 end:
1863 Dbprintf("-----------------------------------------");
1864 Dbprintf("Memory content:");
1865 Dbprintf("-----------------------------------------");
1866 for(i=0; i<max_blocks; i++) {
1867 if(Blocks[i][ALLOC]==1)
1868 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1869 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1870 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1871 else
1872 Dbprintf("<missing block %d>", i);
1873 }
1874 Dbprintf("-----------------------------------------");
1875
1876 return ;
1877 }
1878
1879
1880 //-----------------------------------
1881 // EM4469 / EM4305 routines
1882 //-----------------------------------
1883 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1884 #define FWD_CMD_WRITE 0xA
1885 #define FWD_CMD_READ 0x9
1886 #define FWD_CMD_DISABLE 0x5
1887
1888
1889 uint8_t forwardLink_data[64]; //array of forwarded bits
1890 uint8_t * forward_ptr; //ptr for forward message preparation
1891 uint8_t fwd_bit_sz; //forwardlink bit counter
1892 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1893
1894 //====================================================================
1895 // prepares command bits
1896 // see EM4469 spec
1897 //====================================================================
1898 //--------------------------------------------------------------------
1899 uint8_t Prepare_Cmd( uint8_t cmd ) {
1900 //--------------------------------------------------------------------
1901
1902 *forward_ptr++ = 0; //start bit
1903 *forward_ptr++ = 0; //second pause for 4050 code
1904
1905 *forward_ptr++ = cmd;
1906 cmd >>= 1;
1907 *forward_ptr++ = cmd;
1908 cmd >>= 1;
1909 *forward_ptr++ = cmd;
1910 cmd >>= 1;
1911 *forward_ptr++ = cmd;
1912
1913 return 6; //return number of emited bits
1914 }
1915
1916 //====================================================================
1917 // prepares address bits
1918 // see EM4469 spec
1919 //====================================================================
1920
1921 //--------------------------------------------------------------------
1922 uint8_t Prepare_Addr( uint8_t addr ) {
1923 //--------------------------------------------------------------------
1924
1925 register uint8_t line_parity;
1926
1927 uint8_t i;
1928 line_parity = 0;
1929 for(i=0;i<6;i++) {
1930 *forward_ptr++ = addr;
1931 line_parity ^= addr;
1932 addr >>= 1;
1933 }
1934
1935 *forward_ptr++ = (line_parity & 1);
1936
1937 return 7; //return number of emited bits
1938 }
1939
1940 //====================================================================
1941 // prepares data bits intreleaved with parity bits
1942 // see EM4469 spec
1943 //====================================================================
1944
1945 //--------------------------------------------------------------------
1946 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1947 //--------------------------------------------------------------------
1948
1949 register uint8_t line_parity;
1950 register uint8_t column_parity;
1951 register uint8_t i, j;
1952 register uint16_t data;
1953
1954 data = data_low;
1955 column_parity = 0;
1956
1957 for(i=0; i<4; i++) {
1958 line_parity = 0;
1959 for(j=0; j<8; j++) {
1960 line_parity ^= data;
1961 column_parity ^= (data & 1) << j;
1962 *forward_ptr++ = data;
1963 data >>= 1;
1964 }
1965 *forward_ptr++ = line_parity;
1966 if(i == 1)
1967 data = data_hi;
1968 }
1969
1970 for(j=0; j<8; j++) {
1971 *forward_ptr++ = column_parity;
1972 column_parity >>= 1;
1973 }
1974 *forward_ptr = 0;
1975
1976 return 45; //return number of emited bits
1977 }
1978
1979 //====================================================================
1980 // Forward Link send function
1981 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1982 // fwd_bit_count set with number of bits to be sent
1983 //====================================================================
1984 void SendForward(uint8_t fwd_bit_count) {
1985
1986 fwd_write_ptr = forwardLink_data;
1987 fwd_bit_sz = fwd_bit_count;
1988
1989 LED_D_ON();
1990
1991 //Field on
1992 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1993 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1994 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1995
1996 // Give it a bit of time for the resonant antenna to settle.
1997 // And for the tag to fully power up
1998 SpinDelay(150);
1999
2000 // force 1st mod pulse (start gap must be longer for 4305)
2001 fwd_bit_sz--; //prepare next bit modulation
2002 fwd_write_ptr++;
2003 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2004 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
2005 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
2006 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
2007 SpinDelayUs(16*8); //16 cycles on (8us each)
2008
2009 // now start writting
2010 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
2011 if(((*fwd_write_ptr++) & 1) == 1)
2012 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
2013 else {
2014 //These timings work for 4469/4269/4305 (with the 55*8 above)
2015 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2016 SpinDelayUs(23*8); //16-4 cycles off (8us each)
2017 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
2018 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
2019 SpinDelayUs(9*8); //16 cycles on (8us each)
2020 }
2021 }
2022 }
2023
2024 void EM4xLogin(uint32_t Password) {
2025
2026 uint8_t fwd_bit_count;
2027
2028 forward_ptr = forwardLink_data;
2029 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
2030 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
2031
2032 SendForward(fwd_bit_count);
2033
2034 //Wait for command to complete
2035 SpinDelay(20);
2036
2037 }
2038
2039 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
2040
2041 uint8_t *dest = BigBuf_get_addr();
2042 uint16_t bufferlength = BigBuf_max_traceLen();
2043 uint32_t i = 0;
2044
2045 // Clear destination buffer before sending the command 0x80 = average.
2046 memset(dest, 0x80, bufferlength);
2047
2048 uint8_t fwd_bit_count;
2049
2050 //If password mode do login
2051 if (PwdMode == 1) EM4xLogin(Pwd);
2052
2053 forward_ptr = forwardLink_data;
2054 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
2055 fwd_bit_count += Prepare_Addr( Address );
2056
2057 // Connect the A/D to the peak-detected low-frequency path.
2058 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
2059 // Now set up the SSC to get the ADC samples that are now streaming at us.
2060 FpgaSetupSsc();
2061
2062 SendForward(fwd_bit_count);
2063
2064 // Now do the acquisition
2065 i = 0;
2066 for(;;) {
2067 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
2068 AT91C_BASE_SSC->SSC_THR = 0x43;
2069 }
2070 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
2071 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
2072 ++i;
2073 if (i >= bufferlength) break;
2074 }
2075 }
2076
2077 cmd_send(CMD_ACK,0,0,0,0,0);
2078 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2079 LED_D_OFF();
2080 }
2081
2082 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
2083
2084 uint8_t fwd_bit_count;
2085
2086 //If password mode do login
2087 if (PwdMode == 1) EM4xLogin(Pwd);
2088
2089 forward_ptr = forwardLink_data;
2090 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
2091 fwd_bit_count += Prepare_Addr( Address );
2092 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
2093
2094 SendForward(fwd_bit_count);
2095
2096 //Wait for write to complete
2097 SpinDelay(20);
2098 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2099 LED_D_OFF();
2100 }
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