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FIX: Another try to see if the "lf em4x 410xsim" becomes better, added the clock...
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "../include/proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "../include/hitag2.h"
15 #include "../common/crc16.h"
16 #include "string.h"
17 #include "crapto1.h"
18 #include "mifareutil.h"
19
20 void LFSetupFPGAForADC(int divisor, bool lf_field)
21 {
22 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
23 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
24 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
25 else if (divisor == 0)
26 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
27 else
28 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
29
30 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
31
32 // Connect the A/D to the peak-detected low-frequency path.
33 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
34
35 // Give it a bit of time for the resonant antenna to settle.
36 SpinDelay(150);
37
38 // Now set up the SSC to get the ADC samples that are now streaming at us.
39 FpgaSetupSsc();
40 }
41
42 void AcquireRawAdcSamples125k(int divisor)
43 {
44 LFSetupFPGAForADC(divisor, true);
45 DoAcquisition125k();
46 }
47
48 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
49 {
50 LFSetupFPGAForADC(divisor, false);
51 DoAcquisition125k_threshold(trigger_threshold);
52 }
53
54 // split into two routines so we can avoid timing issues after sending commands //
55 void DoAcquisition125k_internal(int trigger_threshold, bool silent)
56 {
57 uint8_t *dest = mifare_get_bigbufptr();
58 int n = 24000;
59 int i;
60
61 memset(dest, 0x00, n);
62 i = 0;
63 for(;;) {
64 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
65 AT91C_BASE_SSC->SSC_THR = 0x43;
66 LED_D_ON();
67 }
68 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
69 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
70 LED_D_OFF();
71 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
72 continue;
73 else
74 trigger_threshold = -1;
75 if (++i >= n) break;
76 }
77 }
78 if (!silent){
79 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
80 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
81 }
82 }
83 void DoAcquisition125k_threshold(int trigger_threshold) {
84 DoAcquisition125k_internal(trigger_threshold, true);
85 }
86 void DoAcquisition125k() {
87 DoAcquisition125k_internal(-1, true);
88 }
89
90 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
91 {
92
93 /* Make sure the tag is reset */
94 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
95 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
96 SpinDelay(2500);
97
98 int divisor_used = 95; // 125 KHz
99 // see if 'h' was specified
100
101 if (command[strlen((char *) command) - 1] == 'h')
102 divisor_used = 88; // 134.8 KHz
103
104 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
105 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
106 // Give it a bit of time for the resonant antenna to settle.
107 SpinDelay(50);
108
109
110 // And a little more time for the tag to fully power up
111 SpinDelay(2000);
112
113 // Now set up the SSC to get the ADC samples that are now streaming at us.
114 FpgaSetupSsc();
115
116 // now modulate the reader field
117 while(*command != '\0' && *command != ' ') {
118 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
119 LED_D_OFF();
120 SpinDelayUs(delay_off);
121 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
122
123 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
124 LED_D_ON();
125 if(*(command++) == '0')
126 SpinDelayUs(period_0);
127 else
128 SpinDelayUs(period_1);
129 }
130 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
131 LED_D_OFF();
132 SpinDelayUs(delay_off);
133 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
134
135 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
136
137 // now do the read
138 DoAcquisition125k(-1);
139 }
140
141 /* blank r/w tag data stream
142 ...0000000000000000 01111111
143 1010101010101010101010101010101010101010101010101010101010101010
144 0011010010100001
145 01111111
146 101010101010101[0]000...
147
148 [5555fe852c5555555555555555fe0000]
149 */
150 void ReadTItag(void)
151 {
152 // some hardcoded initial params
153 // when we read a TI tag we sample the zerocross line at 2Mhz
154 // TI tags modulate a 1 as 16 cycles of 123.2Khz
155 // TI tags modulate a 0 as 16 cycles of 134.2Khz
156 #define FSAMPLE 2000000
157 #define FREQLO 123200
158 #define FREQHI 134200
159
160 signed char *dest = (signed char *)BigBuf;
161 int n = sizeof(BigBuf);
162 // int *dest = GraphBuffer;
163 // int n = GraphTraceLen;
164
165 // 128 bit shift register [shift3:shift2:shift1:shift0]
166 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
167
168 int i, cycles=0, samples=0;
169 // how many sample points fit in 16 cycles of each frequency
170 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
171 // when to tell if we're close enough to one freq or another
172 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
173
174 // TI tags charge at 134.2Khz
175 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
176 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
177
178 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
179 // connects to SSP_DIN and the SSP_DOUT logic level controls
180 // whether we're modulating the antenna (high)
181 // or listening to the antenna (low)
182 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
183
184 // get TI tag data into the buffer
185 AcquireTiType();
186
187 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
188
189 for (i=0; i<n-1; i++) {
190 // count cycles by looking for lo to hi zero crossings
191 if ( (dest[i]<0) && (dest[i+1]>0) ) {
192 cycles++;
193 // after 16 cycles, measure the frequency
194 if (cycles>15) {
195 cycles=0;
196 samples=i-samples; // number of samples in these 16 cycles
197
198 // TI bits are coming to us lsb first so shift them
199 // right through our 128 bit right shift register
200 shift0 = (shift0>>1) | (shift1 << 31);
201 shift1 = (shift1>>1) | (shift2 << 31);
202 shift2 = (shift2>>1) | (shift3 << 31);
203 shift3 >>= 1;
204
205 // check if the cycles fall close to the number
206 // expected for either the low or high frequency
207 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
208 // low frequency represents a 1
209 shift3 |= (1<<31);
210 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
211 // high frequency represents a 0
212 } else {
213 // probably detected a gay waveform or noise
214 // use this as gaydar or discard shift register and start again
215 shift3 = shift2 = shift1 = shift0 = 0;
216 }
217 samples = i;
218
219 // for each bit we receive, test if we've detected a valid tag
220
221 // if we see 17 zeroes followed by 6 ones, we might have a tag
222 // remember the bits are backwards
223 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
224 // if start and end bytes match, we have a tag so break out of the loop
225 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
226 cycles = 0xF0B; //use this as a flag (ugly but whatever)
227 break;
228 }
229 }
230 }
231 }
232 }
233
234 // if flag is set we have a tag
235 if (cycles!=0xF0B) {
236 DbpString("Info: No valid tag detected.");
237 } else {
238 // put 64 bit data into shift1 and shift0
239 shift0 = (shift0>>24) | (shift1 << 8);
240 shift1 = (shift1>>24) | (shift2 << 8);
241
242 // align 16 bit crc into lower half of shift2
243 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
244
245 // if r/w tag, check ident match
246 if ( shift3&(1<<15) ) {
247 DbpString("Info: TI tag is rewriteable");
248 // only 15 bits compare, last bit of ident is not valid
249 if ( ((shift3>>16)^shift0)&0x7fff ) {
250 DbpString("Error: Ident mismatch!");
251 } else {
252 DbpString("Info: TI tag ident is valid");
253 }
254 } else {
255 DbpString("Info: TI tag is readonly");
256 }
257
258 // WARNING the order of the bytes in which we calc crc below needs checking
259 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
260 // bytes in reverse or something
261 // calculate CRC
262 uint32_t crc=0;
263
264 crc = update_crc16(crc, (shift0)&0xff);
265 crc = update_crc16(crc, (shift0>>8)&0xff);
266 crc = update_crc16(crc, (shift0>>16)&0xff);
267 crc = update_crc16(crc, (shift0>>24)&0xff);
268 crc = update_crc16(crc, (shift1)&0xff);
269 crc = update_crc16(crc, (shift1>>8)&0xff);
270 crc = update_crc16(crc, (shift1>>16)&0xff);
271 crc = update_crc16(crc, (shift1>>24)&0xff);
272
273 Dbprintf("Info: Tag data: %x%08x, crc=%x",
274 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
275 if (crc != (shift2&0xffff)) {
276 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
277 } else {
278 DbpString("Info: CRC is good");
279 }
280 }
281 }
282
283 void WriteTIbyte(uint8_t b)
284 {
285 int i = 0;
286
287 // modulate 8 bits out to the antenna
288 for (i=0; i<8; i++)
289 {
290 if (b&(1<<i)) {
291 // stop modulating antenna
292 LOW(GPIO_SSC_DOUT);
293 SpinDelayUs(1000);
294 // modulate antenna
295 HIGH(GPIO_SSC_DOUT);
296 SpinDelayUs(1000);
297 } else {
298 // stop modulating antenna
299 LOW(GPIO_SSC_DOUT);
300 SpinDelayUs(300);
301 // modulate antenna
302 HIGH(GPIO_SSC_DOUT);
303 SpinDelayUs(1700);
304 }
305 }
306 }
307
308 void AcquireTiType(void)
309 {
310 int i, j, n;
311 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
312 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
313 #define TIBUFLEN 1250
314
315 // clear buffer
316 memset(BigBuf,0,sizeof(BigBuf));
317
318 // Set up the synchronous serial port
319 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
320 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
321
322 // steal this pin from the SSP and use it to control the modulation
323 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
324 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
325
326 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
327 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
328
329 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
330 // 48/2 = 24 MHz clock must be divided by 12
331 AT91C_BASE_SSC->SSC_CMR = 12;
332
333 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
334 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
335 AT91C_BASE_SSC->SSC_TCMR = 0;
336 AT91C_BASE_SSC->SSC_TFMR = 0;
337
338 LED_D_ON();
339
340 // modulate antenna
341 HIGH(GPIO_SSC_DOUT);
342
343 // Charge TI tag for 50ms.
344 SpinDelay(50);
345
346 // stop modulating antenna and listen
347 LOW(GPIO_SSC_DOUT);
348
349 LED_D_OFF();
350
351 i = 0;
352 for(;;) {
353 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
354 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
355 i++; if(i >= TIBUFLEN) break;
356 }
357 WDT_HIT();
358 }
359
360 // return stolen pin to SSP
361 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
362 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
363
364 char *dest = (char *)BigBuf;
365 n = TIBUFLEN*32;
366 // unpack buffer
367 for (i=TIBUFLEN-1; i>=0; i--) {
368 for (j=0; j<32; j++) {
369 if(BigBuf[i] & (1 << j)) {
370 dest[--n] = 1;
371 } else {
372 dest[--n] = -1;
373 }
374 }
375 }
376 }
377
378 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
379 // if crc provided, it will be written with the data verbatim (even if bogus)
380 // if not provided a valid crc will be computed from the data and written.
381 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
382 {
383 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
384 if(crc == 0) {
385 crc = update_crc16(crc, (idlo)&0xff);
386 crc = update_crc16(crc, (idlo>>8)&0xff);
387 crc = update_crc16(crc, (idlo>>16)&0xff);
388 crc = update_crc16(crc, (idlo>>24)&0xff);
389 crc = update_crc16(crc, (idhi)&0xff);
390 crc = update_crc16(crc, (idhi>>8)&0xff);
391 crc = update_crc16(crc, (idhi>>16)&0xff);
392 crc = update_crc16(crc, (idhi>>24)&0xff);
393 }
394 Dbprintf("Writing to tag: %x%08x, crc=%x",
395 (unsigned int) idhi, (unsigned int) idlo, crc);
396
397 // TI tags charge at 134.2Khz
398 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
399 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
400 // connects to SSP_DIN and the SSP_DOUT logic level controls
401 // whether we're modulating the antenna (high)
402 // or listening to the antenna (low)
403 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
404 LED_A_ON();
405
406 // steal this pin from the SSP and use it to control the modulation
407 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
408 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
409
410 // writing algorithm:
411 // a high bit consists of a field off for 1ms and field on for 1ms
412 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
413 // initiate a charge time of 50ms (field on) then immediately start writing bits
414 // start by writing 0xBB (keyword) and 0xEB (password)
415 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
416 // finally end with 0x0300 (write frame)
417 // all data is sent lsb firts
418 // finish with 15ms programming time
419
420 // modulate antenna
421 HIGH(GPIO_SSC_DOUT);
422 SpinDelay(50); // charge time
423
424 WriteTIbyte(0xbb); // keyword
425 WriteTIbyte(0xeb); // password
426 WriteTIbyte( (idlo )&0xff );
427 WriteTIbyte( (idlo>>8 )&0xff );
428 WriteTIbyte( (idlo>>16)&0xff );
429 WriteTIbyte( (idlo>>24)&0xff );
430 WriteTIbyte( (idhi )&0xff );
431 WriteTIbyte( (idhi>>8 )&0xff );
432 WriteTIbyte( (idhi>>16)&0xff );
433 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
434 WriteTIbyte( (crc )&0xff ); // crc lo
435 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
436 WriteTIbyte(0x00); // write frame lo
437 WriteTIbyte(0x03); // write frame hi
438 HIGH(GPIO_SSC_DOUT);
439 SpinDelay(50); // programming time
440
441 LED_A_OFF();
442
443 // get TI tag data into the buffer
444 AcquireTiType();
445
446 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
447 DbpString("Now use tiread to check");
448 }
449
450 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
451 {
452 int i;
453 uint8_t *buff = (uint8_t *)BigBuf;
454
455 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
456 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
457 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
458 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
459
460 // Give it a bit of time for the resonant antenna to settle.
461 SpinDelay(150);
462
463 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
464 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
465 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
466
467 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
468 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
469
470 i = 0;
471 for(;;) {
472 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
473 if(BUTTON_PRESS()) {
474 DbpString("Stopped");
475 return;
476 }
477 WDT_HIT();
478 }
479
480 if (ledcontrol)
481 LED_D_ON();
482
483 if(buff[i])
484 OPEN_COIL();
485 else
486 SHORT_COIL();
487
488 if (ledcontrol)
489 LED_D_OFF();
490
491 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
492 if(BUTTON_PRESS()) {
493 DbpString("Stopped");
494 return;
495 }
496 WDT_HIT();
497 }
498
499 i++;
500 if(i == period) {
501 i = 0;
502 if (gap) {
503 SHORT_COIL();
504 SpinDelayUs(gap);
505 }
506 }
507 }
508 }
509
510 #define DEBUG_FRAME_CONTENTS 1
511 void SimulateTagLowFrequencyBidir(int divisor, int t0)
512 {
513 }
514
515 // compose fc/8 fc/10 waveform
516 static void fc(int c, int *n) {
517 uint8_t *dest = (uint8_t *)BigBuf;
518 int idx;
519
520 // for when we want an fc8 pattern every 4 logical bits
521 if(c==0) {
522 dest[((*n)++)]=1;
523 dest[((*n)++)]=1;
524 dest[((*n)++)]=0;
525 dest[((*n)++)]=0;
526 dest[((*n)++)]=0;
527 dest[((*n)++)]=0;
528 dest[((*n)++)]=0;
529 dest[((*n)++)]=0;
530 }
531 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
532 if(c==8) {
533 for (idx=0; idx<6; idx++) {
534 dest[((*n)++)]=1;
535 dest[((*n)++)]=1;
536 dest[((*n)++)]=0;
537 dest[((*n)++)]=0;
538 dest[((*n)++)]=0;
539 dest[((*n)++)]=0;
540 dest[((*n)++)]=0;
541 dest[((*n)++)]=0;
542 }
543 }
544
545 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
546 if(c==10) {
547 for (idx=0; idx<5; idx++) {
548 dest[((*n)++)]=1;
549 dest[((*n)++)]=1;
550 dest[((*n)++)]=1;
551 dest[((*n)++)]=0;
552 dest[((*n)++)]=0;
553 dest[((*n)++)]=0;
554 dest[((*n)++)]=0;
555 dest[((*n)++)]=0;
556 dest[((*n)++)]=0;
557 dest[((*n)++)]=0;
558 }
559 }
560 }
561
562 // prepare a waveform pattern in the buffer based on the ID given then
563 // simulate a HID tag until the button is pressed
564 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
565 {
566 int n=0, i=0;
567 /*
568 HID tag bitstream format
569 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
570 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
571 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
572 A fc8 is inserted before every 4 bits
573 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
574 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
575 */
576
577 if (hi>0xFFF) {
578 DbpString("Tags can only have 44 bits.");
579 return;
580 }
581 fc(0,&n);
582 // special start of frame marker containing invalid bit sequences
583 fc(8, &n); fc(8, &n); // invalid
584 fc(8, &n); fc(10, &n); // logical 0
585 fc(10, &n); fc(10, &n); // invalid
586 fc(8, &n); fc(10, &n); // logical 0
587
588 WDT_HIT();
589 // manchester encode bits 43 to 32
590 for (i=11; i>=0; i--) {
591 if ((i%4)==3) fc(0,&n);
592 if ((hi>>i)&1) {
593 fc(10, &n); fc(8, &n); // low-high transition
594 } else {
595 fc(8, &n); fc(10, &n); // high-low transition
596 }
597 }
598
599 WDT_HIT();
600 // manchester encode bits 31 to 0
601 for (i=31; i>=0; i--) {
602 if ((i%4)==3) fc(0,&n);
603 if ((lo>>i)&1) {
604 fc(10, &n); fc(8, &n); // low-high transition
605 } else {
606 fc(8, &n); fc(10, &n); // high-low transition
607 }
608 }
609
610 if (ledcontrol)
611 LED_A_ON();
612 SimulateTagLowFrequency(n, 0, ledcontrol);
613
614 if (ledcontrol)
615 LED_A_OFF();
616 }
617
618 size_t fsk_demod(uint8_t * dest, size_t size)
619 {
620 uint32_t last_transition = 0;
621 uint32_t idx = 1;
622
623 // we don't care about actual value, only if it's more or less than a
624 // threshold essentially we capture zero crossings for later analysis
625 uint8_t threshold_value = 127;
626
627 // sync to first lo-hi transition, and threshold
628
629 //Need to threshold first sample
630 dest[0] = (dest[0] < threshold_value) ? 0 : 1;
631
632 size_t numBits = 0;
633 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
634 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
635 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
636 for(idx = 1; idx < size; idx++) {
637 // threshold current value
638 dest[idx] = (dest[idx] < threshold_value) ? 0 : 1;
639
640 // Check for 0->1 transition
641 if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition
642
643 dest[numBits] = (idx-last_transition < 9) ? 1 : 0;
644 last_transition = idx;
645 numBits++;
646 }
647 }
648 return numBits; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0
649 }
650
651
652 size_t aggregate_bits(uint8_t *dest,size_t size, uint8_t h2l_crossing_value,uint8_t l2h_crossing_value, uint8_t maxConsequtiveBits )
653 {
654 uint8_t lastval=dest[0];
655 uint32_t idx=0;
656 size_t numBits=0;
657 uint32_t n=1;
658
659 for( idx=1; idx < size; idx++) {
660
661 if (dest[idx]==lastval) {
662 n++;
663 continue;
664 }
665 //if lastval was 1, we have a 1->0 crossing
666 if ( dest[idx-1] ) {
667 n=(n+1) / h2l_crossing_value;
668 } else {// 0->1 crossing
669 n=(n+1) / l2h_crossing_value;
670 }
671 if (n == 0) n = 1;
672
673 if(n < maxConsequtiveBits)
674 {
675 memset(dest+numBits, dest[idx-1] , n);
676 numBits += n;
677 }
678 n=0;
679 lastval=dest[idx];
680 }//end for
681
682 return numBits;
683
684 }
685 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
686 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
687 {
688 uint8_t *dest = (uint8_t *)BigBuf;
689
690 size_t size=0,idx=0; //, found=0;
691 uint32_t hi2=0, hi=0, lo=0;
692
693 // Configure to go in 125Khz listen mode
694 LFSetupFPGAForADC(0, true);
695
696 while(!BUTTON_PRESS()) {
697
698 WDT_HIT();
699 if (ledcontrol) LED_A_ON();
700
701 DoAcquisition125k_internal(-1,true);
702 size = sizeof(BigBuf);
703
704 // FSK demodulator
705 size = fsk_demod(dest, size);
706
707 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
708 // 1->0 : fc/8 in sets of 6
709 // 0->1 : fc/10 in sets of 5
710 size = aggregate_bits(dest,size, 6,5,5);
711
712 WDT_HIT();
713
714 // final loop, go over previously decoded manchester data and decode into usable tag ID
715 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
716 uint8_t frame_marker_mask[] = {1,1,1,0,0,0};
717 int numshifts = 0;
718 idx = 0;
719 while( idx + sizeof(frame_marker_mask) < size) {
720 // search for a start of frame marker
721 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
722 { // frame marker found
723 idx+=sizeof(frame_marker_mask);
724
725 while(dest[idx] != dest[idx+1] && idx < size-2)
726 {
727 // Keep going until next frame marker (or error)
728 // Shift in a bit. Start by shifting high registers
729 hi2=(hi2<<1)|(hi>>31);
730 hi=(hi<<1)|(lo>>31);
731 //Then, shift in a 0 or one into low
732 if (dest[idx] && !dest[idx+1]) // 1 0
733 lo=(lo<<1)|0;
734 else // 0 1
735 lo=(lo<<1)|
736 1;
737 numshifts ++;
738 idx += 2;
739 }
740 //Dbprintf("Num shifts: %d ", numshifts);
741 // Hopefully, we read a tag and hit upon the next frame marker
742 if(idx + sizeof(frame_marker_mask) < size)
743 {
744 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
745 {
746 if (hi2 != 0){
747 Dbprintf("TAG ID: %x%08x%08x (%d)",
748 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
749 }
750 else {
751 Dbprintf("TAG ID: %x%08x (%d)",
752 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
753 }
754 }
755
756 }
757
758 // reset
759 hi2 = hi = lo = 0;
760 numshifts = 0;
761 }else
762 {
763 idx++;
764 }
765 }
766 WDT_HIT();
767
768 }
769 DbpString("Stopped");
770 if (ledcontrol) LED_A_OFF();
771 }
772
773 uint32_t bytebits_to_byte(uint8_t* src, int numbits)
774 {
775 uint32_t num = 0;
776 for(int i = 0 ; i < numbits ; i++)
777 {
778 num = (num << 1) | (*src);
779 src++;
780 }
781 return num;
782 }
783
784
785 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
786 {
787 uint8_t *dest = (uint8_t *)BigBuf;
788
789 size_t size=0, idx=0;
790 uint32_t code=0, code2=0;
791
792 // Configure to go in 125Khz listen mode
793 LFSetupFPGAForADC(0, true);
794
795 while(!BUTTON_PRESS()) {
796
797
798 WDT_HIT();
799 if (ledcontrol) LED_A_ON();
800
801 DoAcquisition125k_internal(-1,true);
802 size = sizeof(BigBuf);
803
804 // FSK demodulator
805 size = fsk_demod(dest, size);
806
807 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
808 // 1->0 : fc/8 in sets of 7
809 // 0->1 : fc/10 in sets of 6
810 size = aggregate_bits(dest, size, 7,6,13);
811
812 WDT_HIT();
813
814 //Handle the data
815 uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
816 for( idx=0; idx < size - 64; idx++) {
817
818 if ( memcmp(dest + idx, mask, sizeof(mask)) ) continue;
819
820 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7]);
821 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+8], dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15]);
822 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+16],dest[idx+17],dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23]);
823 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+24],dest[idx+25],dest[idx+26],dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31]);
824 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35],dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39]);
825 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44],dest[idx+45],dest[idx+46],dest[idx+47]);
826 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53],dest[idx+54],dest[idx+55]);
827 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
828
829 code = bytebits_to_byte(dest+idx,32);
830 code2 = bytebits_to_byte(dest+idx+32,32);
831
832 short version = bytebits_to_byte(dest+idx+14,4);
833 char unknown = bytebits_to_byte(dest+idx+19,8) ;
834 uint16_t number = bytebits_to_byte(dest+idx+36,9);
835
836 Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,unknown,number,code,code2);
837 if (ledcontrol) LED_D_OFF();
838
839 // if we're only looking for one tag
840 if (findone){
841 LED_A_OFF();
842 return;
843 }
844 }
845 WDT_HIT();
846 }
847 DbpString("Stopped");
848 if (ledcontrol) LED_A_OFF();
849 }
850
851 /*------------------------------
852 * T5555/T5557/T5567 routines
853 *------------------------------
854 */
855
856 /* T55x7 configuration register definitions */
857 #define T55x7_POR_DELAY 0x00000001
858 #define T55x7_ST_TERMINATOR 0x00000008
859 #define T55x7_PWD 0x00000010
860 #define T55x7_MAXBLOCK_SHIFT 5
861 #define T55x7_AOR 0x00000200
862 #define T55x7_PSKCF_RF_2 0
863 #define T55x7_PSKCF_RF_4 0x00000400
864 #define T55x7_PSKCF_RF_8 0x00000800
865 #define T55x7_MODULATION_DIRECT 0
866 #define T55x7_MODULATION_PSK1 0x00001000
867 #define T55x7_MODULATION_PSK2 0x00002000
868 #define T55x7_MODULATION_PSK3 0x00003000
869 #define T55x7_MODULATION_FSK1 0x00004000
870 #define T55x7_MODULATION_FSK2 0x00005000
871 #define T55x7_MODULATION_FSK1a 0x00006000
872 #define T55x7_MODULATION_FSK2a 0x00007000
873 #define T55x7_MODULATION_MANCHESTER 0x00008000
874 #define T55x7_MODULATION_BIPHASE 0x00010000
875 #define T55x7_BITRATE_RF_8 0
876 #define T55x7_BITRATE_RF_16 0x00040000
877 #define T55x7_BITRATE_RF_32 0x00080000
878 #define T55x7_BITRATE_RF_40 0x000C0000
879 #define T55x7_BITRATE_RF_50 0x00100000
880 #define T55x7_BITRATE_RF_64 0x00140000
881 #define T55x7_BITRATE_RF_100 0x00180000
882 #define T55x7_BITRATE_RF_128 0x001C0000
883
884 /* T5555 (Q5) configuration register definitions */
885 #define T5555_ST_TERMINATOR 0x00000001
886 #define T5555_MAXBLOCK_SHIFT 0x00000001
887 #define T5555_MODULATION_MANCHESTER 0
888 #define T5555_MODULATION_PSK1 0x00000010
889 #define T5555_MODULATION_PSK2 0x00000020
890 #define T5555_MODULATION_PSK3 0x00000030
891 #define T5555_MODULATION_FSK1 0x00000040
892 #define T5555_MODULATION_FSK2 0x00000050
893 #define T5555_MODULATION_BIPHASE 0x00000060
894 #define T5555_MODULATION_DIRECT 0x00000070
895 #define T5555_INVERT_OUTPUT 0x00000080
896 #define T5555_PSK_RF_2 0
897 #define T5555_PSK_RF_4 0x00000100
898 #define T5555_PSK_RF_8 0x00000200
899 #define T5555_USE_PWD 0x00000400
900 #define T5555_USE_AOR 0x00000800
901 #define T5555_BITRATE_SHIFT 12
902 #define T5555_FAST_WRITE 0x00004000
903 #define T5555_PAGE_SELECT 0x00008000
904
905 /*
906 * Relevant times in microsecond
907 * To compensate antenna falling times shorten the write times
908 * and enlarge the gap ones.
909 */
910 #define START_GAP 30*8 // 10 - 50fc 250
911 #define WRITE_GAP 20*8 // 8 - 30fc
912 #define WRITE_0 24*8 // 16 - 31fc 24fc 192
913 #define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
914
915 // VALUES TAKEN FROM EM4x function: SendForward
916 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
917 // WRITE_GAP = 128; (16*8)
918 // WRITE_1 = 256 32*8; (32*8)
919
920 // These timings work for 4469/4269/4305 (with the 55*8 above)
921 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
922
923 #define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
924
925 // Write one bit to card
926 void T55xxWriteBit(int bit)
927 {
928 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
929 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
930 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
931 if (!bit)
932 SpinDelayUs(WRITE_0);
933 else
934 SpinDelayUs(WRITE_1);
935 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
936 SpinDelayUs(WRITE_GAP);
937 }
938
939 // Write one card block in page 0, no lock
940 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
941 {
942 uint32_t i = 0;
943
944 // Set up FPGA, 125kHz
945 // Wait for config.. (192+8190xPOW)x8 == 67ms
946 LFSetupFPGAForADC(0, true);
947
948 // Now start writting
949 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
950 SpinDelayUs(START_GAP);
951
952 // Opcode
953 T55xxWriteBit(1);
954 T55xxWriteBit(0); //Page 0
955 if (PwdMode == 1){
956 // Pwd
957 for (i = 0x80000000; i != 0; i >>= 1)
958 T55xxWriteBit(Pwd & i);
959 }
960 // Lock bit
961 T55xxWriteBit(0);
962
963 // Data
964 for (i = 0x80000000; i != 0; i >>= 1)
965 T55xxWriteBit(Data & i);
966
967 // Block
968 for (i = 0x04; i != 0; i >>= 1)
969 T55xxWriteBit(Block & i);
970
971 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
972 // so wait a little more)
973 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
974 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
975 SpinDelay(20);
976 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
977 }
978
979 // Read one card block in page 0
980 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
981 {
982 uint8_t *dest = mifare_get_bigbufptr();
983 uint16_t bufferlength = T55xx_SAMPLES_SIZE;
984 uint32_t i = 0;
985
986 // Clear destination buffer before sending the command 0x80 = average.
987 memset(dest, 0x80, bufferlength);
988
989 // Set up FPGA, 125kHz
990 // Wait for config.. (192+8190xPOW)x8 == 67ms
991 LFSetupFPGAForADC(0, true);
992
993 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
994 SpinDelayUs(START_GAP);
995
996 // Opcode
997 T55xxWriteBit(1);
998 T55xxWriteBit(0); //Page 0
999 if (PwdMode == 1){
1000 // Pwd
1001 for (i = 0x80000000; i != 0; i >>= 1)
1002 T55xxWriteBit(Pwd & i);
1003 }
1004 // Lock bit
1005 T55xxWriteBit(0);
1006 // Block
1007 for (i = 0x04; i != 0; i >>= 1)
1008 T55xxWriteBit(Block & i);
1009
1010 // Turn field on to read the response
1011 TurnReadLFOn();
1012
1013 // Now do the acquisition
1014 i = 0;
1015 for(;;) {
1016 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1017 AT91C_BASE_SSC->SSC_THR = 0x43;
1018 LED_D_ON();
1019 }
1020 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1021 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1022 ++i;
1023 LED_D_OFF();
1024 if (i > bufferlength) break;
1025 }
1026 }
1027
1028 cmd_send(CMD_ACK,0,0,0,0,0);
1029 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1030 LED_D_OFF();
1031 }
1032
1033 // Read card traceability data (page 1)
1034 void T55xxReadTrace(void){
1035 uint8_t *dest = mifare_get_bigbufptr();
1036 uint16_t bufferlength = T55xx_SAMPLES_SIZE;
1037 int i=0;
1038
1039 // Clear destination buffer before sending the command 0x80 = average
1040 memset(dest, 0x80, bufferlength);
1041
1042 LFSetupFPGAForADC(0, true);
1043
1044 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1045 SpinDelayUs(START_GAP);
1046
1047 // Opcode
1048 T55xxWriteBit(1);
1049 T55xxWriteBit(1); //Page 1
1050
1051 // Turn field on to read the response
1052 TurnReadLFOn();
1053
1054 // Now do the acquisition
1055 for(;;) {
1056 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1057 AT91C_BASE_SSC->SSC_THR = 0x43;
1058 LED_D_ON();
1059 }
1060 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1061 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1062 ++i;
1063 LED_D_OFF();
1064
1065 if (i >= bufferlength) break;
1066 }
1067 }
1068
1069 cmd_send(CMD_ACK,0,0,0,0,0);
1070 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1071 LED_D_OFF();
1072 }
1073
1074 void TurnReadLFOn(){
1075 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1076 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1077 // Give it a bit of time for the resonant antenna to settle.
1078 //SpinDelay(30);
1079 SpinDelayUs(8*150);
1080 }
1081
1082 /*-------------- Cloning routines -----------*/
1083 // Copy HID id to card and setup block 0 config
1084 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1085 {
1086 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1087 int last_block = 0;
1088
1089 if (longFMT){
1090 // Ensure no more than 84 bits supplied
1091 if (hi2>0xFFFFF) {
1092 DbpString("Tags can only have 84 bits.");
1093 return;
1094 }
1095 // Build the 6 data blocks for supplied 84bit ID
1096 last_block = 6;
1097 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1098 for (int i=0;i<4;i++) {
1099 if (hi2 & (1<<(19-i)))
1100 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1101 else
1102 data1 |= (1<<((3-i)*2)); // 0 -> 01
1103 }
1104
1105 data2 = 0;
1106 for (int i=0;i<16;i++) {
1107 if (hi2 & (1<<(15-i)))
1108 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1109 else
1110 data2 |= (1<<((15-i)*2)); // 0 -> 01
1111 }
1112
1113 data3 = 0;
1114 for (int i=0;i<16;i++) {
1115 if (hi & (1<<(31-i)))
1116 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1117 else
1118 data3 |= (1<<((15-i)*2)); // 0 -> 01
1119 }
1120
1121 data4 = 0;
1122 for (int i=0;i<16;i++) {
1123 if (hi & (1<<(15-i)))
1124 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1125 else
1126 data4 |= (1<<((15-i)*2)); // 0 -> 01
1127 }
1128
1129 data5 = 0;
1130 for (int i=0;i<16;i++) {
1131 if (lo & (1<<(31-i)))
1132 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1133 else
1134 data5 |= (1<<((15-i)*2)); // 0 -> 01
1135 }
1136
1137 data6 = 0;
1138 for (int i=0;i<16;i++) {
1139 if (lo & (1<<(15-i)))
1140 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1141 else
1142 data6 |= (1<<((15-i)*2)); // 0 -> 01
1143 }
1144 }
1145 else {
1146 // Ensure no more than 44 bits supplied
1147 if (hi>0xFFF) {
1148 DbpString("Tags can only have 44 bits.");
1149 return;
1150 }
1151
1152 // Build the 3 data blocks for supplied 44bit ID
1153 last_block = 3;
1154
1155 data1 = 0x1D000000; // load preamble
1156
1157 for (int i=0;i<12;i++) {
1158 if (hi & (1<<(11-i)))
1159 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1160 else
1161 data1 |= (1<<((11-i)*2)); // 0 -> 01
1162 }
1163
1164 data2 = 0;
1165 for (int i=0;i<16;i++) {
1166 if (lo & (1<<(31-i)))
1167 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1168 else
1169 data2 |= (1<<((15-i)*2)); // 0 -> 01
1170 }
1171
1172 data3 = 0;
1173 for (int i=0;i<16;i++) {
1174 if (lo & (1<<(15-i)))
1175 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1176 else
1177 data3 |= (1<<((15-i)*2)); // 0 -> 01
1178 }
1179 }
1180
1181 LED_D_ON();
1182 // Program the data blocks for supplied ID
1183 // and the block 0 for HID format
1184 T55xxWriteBlock(data1,1,0,0);
1185 T55xxWriteBlock(data2,2,0,0);
1186 T55xxWriteBlock(data3,3,0,0);
1187
1188 if (longFMT) { // if long format there are 6 blocks
1189 T55xxWriteBlock(data4,4,0,0);
1190 T55xxWriteBlock(data5,5,0,0);
1191 T55xxWriteBlock(data6,6,0,0);
1192 }
1193
1194 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1195 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1196 T55x7_MODULATION_FSK2a |
1197 last_block << T55x7_MAXBLOCK_SHIFT,
1198 0,0,0);
1199
1200 LED_D_OFF();
1201
1202 DbpString("DONE!");
1203 }
1204
1205 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1206 {
1207 int data1=0, data2=0; //up to six blocks for long format
1208
1209 data1 = hi; // load preamble
1210 data2 = lo;
1211
1212 LED_D_ON();
1213 // Program the data blocks for supplied ID
1214 // and the block 0 for HID format
1215 T55xxWriteBlock(data1,1,0,0);
1216 T55xxWriteBlock(data2,2,0,0);
1217
1218 //Config Block
1219 T55xxWriteBlock(0x00147040,0,0,0);
1220 LED_D_OFF();
1221
1222 DbpString("DONE!");
1223 }
1224
1225 // Define 9bit header for EM410x tags
1226 #define EM410X_HEADER 0x1FF
1227 #define EM410X_ID_LENGTH 40
1228
1229 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1230 {
1231 int i, id_bit;
1232 uint64_t id = EM410X_HEADER;
1233 uint64_t rev_id = 0; // reversed ID
1234 int c_parity[4]; // column parity
1235 int r_parity = 0; // row parity
1236 uint32_t clock = 0;
1237
1238 // Reverse ID bits given as parameter (for simpler operations)
1239 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1240 if (i < 32) {
1241 rev_id = (rev_id << 1) | (id_lo & 1);
1242 id_lo >>= 1;
1243 } else {
1244 rev_id = (rev_id << 1) | (id_hi & 1);
1245 id_hi >>= 1;
1246 }
1247 }
1248
1249 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1250 id_bit = rev_id & 1;
1251
1252 if (i % 4 == 0) {
1253 // Don't write row parity bit at start of parsing
1254 if (i)
1255 id = (id << 1) | r_parity;
1256 // Start counting parity for new row
1257 r_parity = id_bit;
1258 } else {
1259 // Count row parity
1260 r_parity ^= id_bit;
1261 }
1262
1263 // First elements in column?
1264 if (i < 4)
1265 // Fill out first elements
1266 c_parity[i] = id_bit;
1267 else
1268 // Count column parity
1269 c_parity[i % 4] ^= id_bit;
1270
1271 // Insert ID bit
1272 id = (id << 1) | id_bit;
1273 rev_id >>= 1;
1274 }
1275
1276 // Insert parity bit of last row
1277 id = (id << 1) | r_parity;
1278
1279 // Fill out column parity at the end of tag
1280 for (i = 0; i < 4; ++i)
1281 id = (id << 1) | c_parity[i];
1282
1283 // Add stop bit
1284 id <<= 1;
1285
1286 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1287 LED_D_ON();
1288
1289 // Write EM410x ID
1290 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1291 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1292
1293 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1294 if (card) {
1295 // Clock rate is stored in bits 8-15 of the card value
1296 clock = (card & 0xFF00) >> 8;
1297 Dbprintf("Clock rate: %d", clock);
1298 switch (clock)
1299 {
1300 case 32:
1301 clock = T55x7_BITRATE_RF_32;
1302 break;
1303 case 16:
1304 clock = T55x7_BITRATE_RF_16;
1305 break;
1306 case 0:
1307 // A value of 0 is assumed to be 64 for backwards-compatibility
1308 // Fall through...
1309 case 64:
1310 clock = T55x7_BITRATE_RF_64;
1311 break;
1312 default:
1313 Dbprintf("Invalid clock rate: %d", clock);
1314 return;
1315 }
1316
1317 // Writing configuration for T55x7 tag
1318 T55xxWriteBlock(clock |
1319 T55x7_MODULATION_MANCHESTER |
1320 2 << T55x7_MAXBLOCK_SHIFT,
1321 0, 0, 0);
1322 }
1323 else
1324 // Writing configuration for T5555(Q5) tag
1325 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1326 T5555_MODULATION_MANCHESTER |
1327 2 << T5555_MAXBLOCK_SHIFT,
1328 0, 0, 0);
1329
1330 LED_D_OFF();
1331 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1332 (uint32_t)(id >> 32), (uint32_t)id);
1333 }
1334
1335 // Clone Indala 64-bit tag by UID to T55x7
1336 void CopyIndala64toT55x7(int hi, int lo)
1337 {
1338 //Program the 2 data blocks for supplied 64bit UID
1339 // and the block 0 for Indala64 format
1340 T55xxWriteBlock(hi,1,0,0);
1341 T55xxWriteBlock(lo,2,0,0);
1342 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1343 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1344 T55x7_MODULATION_PSK1 |
1345 2 << T55x7_MAXBLOCK_SHIFT,
1346 0, 0, 0);
1347 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1348 // T5567WriteBlock(0x603E1042,0);
1349
1350 DbpString("DONE!");
1351 }
1352
1353 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1354 {
1355 //Program the 7 data blocks for supplied 224bit UID
1356 // and the block 0 for Indala224 format
1357 T55xxWriteBlock(uid1,1,0,0);
1358 T55xxWriteBlock(uid2,2,0,0);
1359 T55xxWriteBlock(uid3,3,0,0);
1360 T55xxWriteBlock(uid4,4,0,0);
1361 T55xxWriteBlock(uid5,5,0,0);
1362 T55xxWriteBlock(uid6,6,0,0);
1363 T55xxWriteBlock(uid7,7,0,0);
1364 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1365 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1366 T55x7_MODULATION_PSK1 |
1367 7 << T55x7_MAXBLOCK_SHIFT,
1368 0,0,0);
1369 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1370 // T5567WriteBlock(0x603E10E2,0);
1371
1372 DbpString("DONE!");
1373 }
1374
1375
1376 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1377 #define max(x,y) ( x<y ? y:x)
1378
1379 int DemodPCF7931(uint8_t **outBlocks) {
1380 uint8_t BitStream[256];
1381 uint8_t Blocks[8][16];
1382 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1383 int GraphTraceLen = sizeof(BigBuf);
1384 int i, j, lastval, bitidx, half_switch;
1385 int clock = 64;
1386 int tolerance = clock / 8;
1387 int pmc, block_done;
1388 int lc, warnings = 0;
1389 int num_blocks = 0;
1390 int lmin=128, lmax=128;
1391 uint8_t dir;
1392
1393 AcquireRawAdcSamples125k(0);
1394
1395 lmin = 64;
1396 lmax = 192;
1397
1398 i = 2;
1399
1400 /* Find first local max/min */
1401 if(GraphBuffer[1] > GraphBuffer[0]) {
1402 while(i < GraphTraceLen) {
1403 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1404 break;
1405 i++;
1406 }
1407 dir = 0;
1408 }
1409 else {
1410 while(i < GraphTraceLen) {
1411 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1412 break;
1413 i++;
1414 }
1415 dir = 1;
1416 }
1417
1418 lastval = i++;
1419 half_switch = 0;
1420 pmc = 0;
1421 block_done = 0;
1422
1423 for (bitidx = 0; i < GraphTraceLen; i++)
1424 {
1425 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1426 {
1427 lc = i - lastval;
1428 lastval = i;
1429
1430 // Switch depending on lc length:
1431 // Tolerance is 1/8 of clock rate (arbitrary)
1432 if (abs(lc-clock/4) < tolerance) {
1433 // 16T0
1434 if((i - pmc) == lc) { /* 16T0 was previous one */
1435 /* It's a PMC ! */
1436 i += (128+127+16+32+33+16)-1;
1437 lastval = i;
1438 pmc = 0;
1439 block_done = 1;
1440 }
1441 else {
1442 pmc = i;
1443 }
1444 } else if (abs(lc-clock/2) < tolerance) {
1445 // 32TO
1446 if((i - pmc) == lc) { /* 16T0 was previous one */
1447 /* It's a PMC ! */
1448 i += (128+127+16+32+33)-1;
1449 lastval = i;
1450 pmc = 0;
1451 block_done = 1;
1452 }
1453 else if(half_switch == 1) {
1454 BitStream[bitidx++] = 0;
1455 half_switch = 0;
1456 }
1457 else
1458 half_switch++;
1459 } else if (abs(lc-clock) < tolerance) {
1460 // 64TO
1461 BitStream[bitidx++] = 1;
1462 } else {
1463 // Error
1464 warnings++;
1465 if (warnings > 10)
1466 {
1467 Dbprintf("Error: too many detection errors, aborting.");
1468 return 0;
1469 }
1470 }
1471
1472 if(block_done == 1) {
1473 if(bitidx == 128) {
1474 for(j=0; j<16; j++) {
1475 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1476 64*BitStream[j*8+6]+
1477 32*BitStream[j*8+5]+
1478 16*BitStream[j*8+4]+
1479 8*BitStream[j*8+3]+
1480 4*BitStream[j*8+2]+
1481 2*BitStream[j*8+1]+
1482 BitStream[j*8];
1483 }
1484 num_blocks++;
1485 }
1486 bitidx = 0;
1487 block_done = 0;
1488 half_switch = 0;
1489 }
1490 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1491 else dir = 1;
1492 }
1493 if(bitidx==255)
1494 bitidx=0;
1495 warnings = 0;
1496 if(num_blocks == 4) break;
1497 }
1498 memcpy(outBlocks, Blocks, 16*num_blocks);
1499 return num_blocks;
1500 }
1501
1502 int IsBlock0PCF7931(uint8_t *Block) {
1503 // Assume RFU means 0 :)
1504 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1505 return 1;
1506 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1507 return 1;
1508 return 0;
1509 }
1510
1511 int IsBlock1PCF7931(uint8_t *Block) {
1512 // Assume RFU means 0 :)
1513 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1514 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1515 return 1;
1516
1517 return 0;
1518 }
1519 #define ALLOC 16
1520
1521 void ReadPCF7931() {
1522 uint8_t Blocks[8][17];
1523 uint8_t tmpBlocks[4][16];
1524 int i, j, ind, ind2, n;
1525 int num_blocks = 0;
1526 int max_blocks = 8;
1527 int ident = 0;
1528 int error = 0;
1529 int tries = 0;
1530
1531 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1532
1533 do {
1534 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1535 n = DemodPCF7931((uint8_t**)tmpBlocks);
1536 if(!n)
1537 error++;
1538 if(error==10 && num_blocks == 0) {
1539 Dbprintf("Error, no tag or bad tag");
1540 return;
1541 }
1542 else if (tries==20 || error==10) {
1543 Dbprintf("Error reading the tag");
1544 Dbprintf("Here is the partial content");
1545 goto end;
1546 }
1547
1548 for(i=0; i<n; i++)
1549 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1550 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1551 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1552 if(!ident) {
1553 for(i=0; i<n; i++) {
1554 if(IsBlock0PCF7931(tmpBlocks[i])) {
1555 // Found block 0 ?
1556 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1557 // Found block 1!
1558 // \o/
1559 ident = 1;
1560 memcpy(Blocks[0], tmpBlocks[i], 16);
1561 Blocks[0][ALLOC] = 1;
1562 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1563 Blocks[1][ALLOC] = 1;
1564 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1565 // Debug print
1566 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1567 num_blocks = 2;
1568 // Handle following blocks
1569 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1570 if(j==n) j=0;
1571 if(j==i) break;
1572 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1573 Blocks[ind2][ALLOC] = 1;
1574 }
1575 break;
1576 }
1577 }
1578 }
1579 }
1580 else {
1581 for(i=0; i<n; i++) { // Look for identical block in known blocks
1582 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1583 for(j=0; j<max_blocks; j++) {
1584 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1585 // Found an identical block
1586 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1587 if(ind2 < 0)
1588 ind2 = max_blocks;
1589 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1590 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1591 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1592 Blocks[ind2][ALLOC] = 1;
1593 num_blocks++;
1594 if(num_blocks == max_blocks) goto end;
1595 }
1596 }
1597 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1598 if(ind2 > max_blocks)
1599 ind2 = 0;
1600 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1601 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1602 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1603 Blocks[ind2][ALLOC] = 1;
1604 num_blocks++;
1605 if(num_blocks == max_blocks) goto end;
1606 }
1607 }
1608 }
1609 }
1610 }
1611 }
1612 }
1613 tries++;
1614 if (BUTTON_PRESS()) return;
1615 } while (num_blocks != max_blocks);
1616 end:
1617 Dbprintf("-----------------------------------------");
1618 Dbprintf("Memory content:");
1619 Dbprintf("-----------------------------------------");
1620 for(i=0; i<max_blocks; i++) {
1621 if(Blocks[i][ALLOC]==1)
1622 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1623 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1624 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1625 else
1626 Dbprintf("<missing block %d>", i);
1627 }
1628 Dbprintf("-----------------------------------------");
1629
1630 return ;
1631 }
1632
1633
1634 //-----------------------------------
1635 // EM4469 / EM4305 routines
1636 //-----------------------------------
1637 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1638 #define FWD_CMD_WRITE 0xA
1639 #define FWD_CMD_READ 0x9
1640 #define FWD_CMD_DISABLE 0x5
1641
1642
1643 uint8_t forwardLink_data[64]; //array of forwarded bits
1644 uint8_t * forward_ptr; //ptr for forward message preparation
1645 uint8_t fwd_bit_sz; //forwardlink bit counter
1646 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1647
1648 //====================================================================
1649 // prepares command bits
1650 // see EM4469 spec
1651 //====================================================================
1652 //--------------------------------------------------------------------
1653 uint8_t Prepare_Cmd( uint8_t cmd ) {
1654 //--------------------------------------------------------------------
1655
1656 *forward_ptr++ = 0; //start bit
1657 *forward_ptr++ = 0; //second pause for 4050 code
1658
1659 *forward_ptr++ = cmd;
1660 cmd >>= 1;
1661 *forward_ptr++ = cmd;
1662 cmd >>= 1;
1663 *forward_ptr++ = cmd;
1664 cmd >>= 1;
1665 *forward_ptr++ = cmd;
1666
1667 return 6; //return number of emited bits
1668 }
1669
1670 //====================================================================
1671 // prepares address bits
1672 // see EM4469 spec
1673 //====================================================================
1674
1675 //--------------------------------------------------------------------
1676 uint8_t Prepare_Addr( uint8_t addr ) {
1677 //--------------------------------------------------------------------
1678
1679 register uint8_t line_parity;
1680
1681 uint8_t i;
1682 line_parity = 0;
1683 for(i=0;i<6;i++) {
1684 *forward_ptr++ = addr;
1685 line_parity ^= addr;
1686 addr >>= 1;
1687 }
1688
1689 *forward_ptr++ = (line_parity & 1);
1690
1691 return 7; //return number of emited bits
1692 }
1693
1694 //====================================================================
1695 // prepares data bits intreleaved with parity bits
1696 // see EM4469 spec
1697 //====================================================================
1698
1699 //--------------------------------------------------------------------
1700 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1701 //--------------------------------------------------------------------
1702
1703 register uint8_t line_parity;
1704 register uint8_t column_parity;
1705 register uint8_t i, j;
1706 register uint16_t data;
1707
1708 data = data_low;
1709 column_parity = 0;
1710
1711 for(i=0; i<4; i++) {
1712 line_parity = 0;
1713 for(j=0; j<8; j++) {
1714 line_parity ^= data;
1715 column_parity ^= (data & 1) << j;
1716 *forward_ptr++ = data;
1717 data >>= 1;
1718 }
1719 *forward_ptr++ = line_parity;
1720 if(i == 1)
1721 data = data_hi;
1722 }
1723
1724 for(j=0; j<8; j++) {
1725 *forward_ptr++ = column_parity;
1726 column_parity >>= 1;
1727 }
1728 *forward_ptr = 0;
1729
1730 return 45; //return number of emited bits
1731 }
1732
1733 //====================================================================
1734 // Forward Link send function
1735 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1736 // fwd_bit_count set with number of bits to be sent
1737 //====================================================================
1738 void SendForward(uint8_t fwd_bit_count) {
1739
1740 fwd_write_ptr = forwardLink_data;
1741 fwd_bit_sz = fwd_bit_count;
1742
1743 LED_D_ON();
1744
1745 //Field on
1746 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1747 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1748 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1749
1750 // Give it a bit of time for the resonant antenna to settle.
1751 // And for the tag to fully power up
1752 SpinDelay(150);
1753
1754 // force 1st mod pulse (start gap must be longer for 4305)
1755 fwd_bit_sz--; //prepare next bit modulation
1756 fwd_write_ptr++;
1757 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1758 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1759 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1760 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1761 SpinDelayUs(16*8); //16 cycles on (8us each)
1762
1763 // now start writting
1764 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1765 if(((*fwd_write_ptr++) & 1) == 1)
1766 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1767 else {
1768 //These timings work for 4469/4269/4305 (with the 55*8 above)
1769 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1770 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1771 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1772 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1773 SpinDelayUs(9*8); //16 cycles on (8us each)
1774 }
1775 }
1776 }
1777
1778
1779 void EM4xLogin(uint32_t Password) {
1780
1781 uint8_t fwd_bit_count;
1782
1783 forward_ptr = forwardLink_data;
1784 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1785 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1786
1787 SendForward(fwd_bit_count);
1788
1789 //Wait for command to complete
1790 SpinDelay(20);
1791
1792 }
1793
1794 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1795
1796 uint8_t *dest = mifare_get_bigbufptr();
1797 uint16_t bufferlength = 12000;
1798 uint32_t i = 0;
1799
1800 // Clear destination buffer before sending the command 0x80 = average.
1801 memset(dest, 0x80, bufferlength);
1802
1803 uint8_t fwd_bit_count;
1804
1805 //If password mode do login
1806 if (PwdMode == 1) EM4xLogin(Pwd);
1807
1808 forward_ptr = forwardLink_data;
1809 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1810 fwd_bit_count += Prepare_Addr( Address );
1811
1812 // Connect the A/D to the peak-detected low-frequency path.
1813 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1814 // Now set up the SSC to get the ADC samples that are now streaming at us.
1815 FpgaSetupSsc();
1816
1817 SendForward(fwd_bit_count);
1818
1819 // // Turn field on to read the response
1820 // TurnReadLFOn();
1821
1822 // Now do the acquisition
1823 i = 0;
1824 for(;;) {
1825 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1826 AT91C_BASE_SSC->SSC_THR = 0x43;
1827 }
1828 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1829 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1830 ++i;
1831 if (i >= bufferlength) break;
1832 }
1833 }
1834
1835 cmd_send(CMD_ACK,0,0,0,0,0);
1836 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1837 LED_D_OFF();
1838 }
1839
1840 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1841
1842 uint8_t fwd_bit_count;
1843
1844 //If password mode do login
1845 if (PwdMode == 1) EM4xLogin(Pwd);
1846
1847 forward_ptr = forwardLink_data;
1848 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1849 fwd_bit_count += Prepare_Addr( Address );
1850 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1851
1852 SendForward(fwd_bit_count);
1853
1854 //Wait for write to complete
1855 SpinDelay(20);
1856 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1857 LED_D_OFF();
1858 }
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