]> cvs.zerfleddert.de Git - proxmark3-svn/blob - armsrc/legicrf.c
projects / proxmark3-svn / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
FIX: 'hf 14a sim x' - this fixes the error with using moebius attack and sim. Updat...
[proxmark3-svn] / armsrc / legicrf.c
1 //-----------------------------------------------------------------------------
2 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
3 // 2016 Iceman
4 //
5 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
6 // at your option, any later version. See the LICENSE.txt file for the text of
7 // the license.
8 //-----------------------------------------------------------------------------
9 // LEGIC RF simulation code
10 //-----------------------------------------------------------------------------
11 #include "legicrf.h"
12
13 static struct legic_frame {
14 uint8_t bits;
15 uint32_t data;
16 } current_frame;
17
18 static enum {
19 STATE_DISCON,
20 STATE_IV,
21 STATE_CON,
22 } legic_state;
23
24 static crc_t legic_crc;
25 static int legic_read_count;
26 static uint32_t legic_prng_bc;
27 static uint32_t legic_prng_iv;
28
29 static int legic_phase_drift;
30 static int legic_frame_drift;
31 static int legic_reqresp_drift;
32
33 AT91PS_TC timer;
34 AT91PS_TC prng_timer;
35
36 /*
37 static void setup_timer(void) {
38 // Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
39 // this it won't be terribly accurate but should be good enough.
40 //
41 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
42 timer = AT91C_BASE_TC1;
43 timer->TC_CCR = AT91C_TC_CLKDIS;
44 timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
45 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
46
47 //
48 // Set up Timer 2 to use for measuring time between frames in
49 // tag simulation mode. Runs 4x faster as Timer 1
50 //
51 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);
52 prng_timer = AT91C_BASE_TC2;
53 prng_timer->TC_CCR = AT91C_TC_CLKDIS;
54 prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
55 prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
56 }
57
58 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
59 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
60
61 // fast clock
62 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
63 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
64 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
65 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
66 AT91C_BASE_TC0->TC_RA = 1;
67 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
68
69 */
70
71 // At TIMER_CLOCK3 (MCK/32)
72 // testing calculating in ticks. 1.5ticks = 1us
73 #define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks
74 #define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks
75 #define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */
76 #define TAG_BIT_PERIOD 142 // 100us == 100 * 1.5 == 150ticks
77 #define TAG_FRAME_WAIT 495 // 330us from READER frame end to TAG frame start. 330 * 1.5 == 495
78
79 #define RWD_TIME_FUZZ 20 // rather generous 13us, since the peak detector + hysteresis fuzz quite a bit
80
81 #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
82 #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
83
84 #define OFFSET_LOG 1024
85
86 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
87
88 #ifndef SHORT_COIL
89 # define SHORT_COIL LOW(GPIO_SSC_DOUT);
90 #endif
91 #ifndef OPEN_COIL
92 # define OPEN_COIL HIGH(GPIO_SSC_DOUT);
93 #endif
94 #ifndef LINE_IN
95 # define LINE_IN AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
96 #endif
97 // Pause pulse, off in 20us / 30ticks,
98 // ONE / ZERO bit pulse,
99 // one == 80us / 120ticks
100 // zero == 40us / 60ticks
101 #ifndef COIL_PULSE
102 # define COIL_PULSE(x) \
103 do { \
104 SHORT_COIL; \
105 WaitTicks( (RWD_TIME_PAUSE) ); \
106 OPEN_COIL; \
107 WaitTicks((x)); \
108 } while (0);
109 #endif
110
111 // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
112 // Historically it used to be FREE_BUFFER_SIZE, which was 2744.
113 #define LEGIC_CARD_MEMSIZE 1024
114 static uint8_t* cardmem;
115
116 static void frame_append_bit(struct legic_frame * const f, uint8_t bit) {
117 // Overflow, won't happen
118 if (f->bits >= 31) return;
119
120 f->data |= (bit << f->bits);
121 f->bits++;
122 }
123
124 static void frame_clean(struct legic_frame * const f) {
125 f->data = 0;
126 f->bits = 0;
127 }
128
129 // Prng works when waiting in 99.1us cycles.
130 // and while sending/receiving in bit frames (100, 60)
131 /*static void CalibratePrng( uint32_t time){
132 // Calculate Cycles based on timer 100us
133 uint32_t i = (time - sendFrameStop) / 100 ;
134
135 // substract cycles of finished frames
136 int k = i - legic_prng_count()+1;
137
138 // substract current frame length, rewind to beginning
139 if ( k > 0 )
140 legic_prng_forward(k);
141 }
142 */
143
144 /* Generate Keystream */
145 uint32_t get_key_stream(int skip, int count) {
146
147 int i;
148
149 // Use int to enlarge timer tc to 32bit
150 legic_prng_bc += prng_timer->TC_CV;
151
152 // reset the prng timer.
153
154 /* If skip == -1, forward prng time based */
155 if(skip == -1) {
156 i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */
157 i -= legic_prng_count(); /* substract cycles of finished frames */
158 i -= count; /* substract current frame length, rewind to beginning */
159 legic_prng_forward(i);
160 } else {
161 legic_prng_forward(skip);
162 }
163
164 i = (count == 6) ? -1 : legic_read_count;
165
166 /* Generate KeyStream */
167 return legic_prng_get_bits(count);
168 }
169
170 /* Send a frame in tag mode, the FPGA must have been set up by
171 * LegicRfSimulate
172 */
173 void frame_send_tag(uint16_t response, uint8_t bits) {
174
175 uint16_t mask = 1;
176
177 /* Bitbang the response */
178 SHORT_COIL;
179 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
180 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
181
182 /* TAG_FRAME_WAIT -> shift by 2 */
183 legic_prng_forward(3);
184 response ^= legic_prng_get_bits(bits);
185
186 /* Wait for the frame start */
187 WaitTicks( TAG_FRAME_WAIT );
188
189 for (; mask < BITMASK(bits); mask <<= 1) {
190 if (response & mask)
191 OPEN_COIL
192 else
193 SHORT_COIL
194 WaitTicks(TAG_BIT_PERIOD);
195 }
196 SHORT_COIL;
197 }
198
199 /* Send a frame in reader mode, the FPGA must have been set up by
200 * LegicRfReader
201 */
202 void frame_sendAsReader(uint32_t data, uint8_t bits){
203
204 uint32_t starttime = GET_TICKS, send = 0, mask = 1;
205
206 // xor lsfr onto data.
207 send = data ^ legic_prng_get_bits(bits);
208
209 for (; mask < BITMASK(bits); mask <<= 1) {
210 if (send & mask)
211 COIL_PULSE(RWD_TIME_1)
212 else
213 COIL_PULSE(RWD_TIME_0)
214 }
215
216 // Final pause to mark the end of the frame
217 COIL_PULSE(0);
218
219 // log
220 uint8_t cmdbytes[] = {bits, BYTEx(data,0), BYTEx(data,1), BYTEx(data,2), BYTEx(send,0), BYTEx(send,1), BYTEx(send,2)};
221 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, TRUE);
222 }
223
224 /* Receive a frame from the card in reader emulation mode, the FPGA and
225 * timer must have been set up by LegicRfReader and frame_sendAsReader.
226 *
227 * The LEGIC RF protocol from card to reader does not include explicit
228 * frame start/stop information or length information. The reader must
229 * know beforehand how many bits it wants to receive. (Notably: a card
230 * sending a stream of 0-bits is indistinguishable from no card present.)
231 *
232 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
233 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
234 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
235 * for edges. Count the edges in each bit interval. If they are approximately
236 * 0 this was a 0-bit, if they are approximately equal to the number of edges
237 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
238 * timer that's still running from frame_sendAsReader in order to get a synchronization
239 * with the frame that we just sent.
240 *
241 * FIXME: Because we're relying on the hysteresis to just do the right thing
242 * the range is severely reduced (and you'll probably also need a good antenna).
243 * So this should be fixed some time in the future for a proper receiver.
244 */
245 static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) {
246
247 if ( bits > 32 ) return;
248
249 uint8_t i = bits, edges = 0;
250 uint32_t the_bit = 1, next_bit_at = 0, data = 0;
251 uint32_t old_level = 0;
252 volatile uint32_t level = 0;
253
254 frame_clean(f);
255
256 // calibrate the prng.
257 legic_prng_forward(2);
258 data = legic_prng_get_bits(bits);
259
260 //FIXED time between sending frame and now listening frame. 330us
261 uint32_t starttime = GET_TICKS;
262 // its about 9+9 ticks delay from end-send to here.
263 WaitTicks( 477 );
264
265 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
266
267 while ( i-- ){
268 edges = 0;
269 while ( GET_TICKS < next_bit_at) {
270
271 level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
272
273 if (level != old_level)
274 ++edges;
275
276 old_level = level;
277 }
278
279 next_bit_at += TAG_BIT_PERIOD;
280
281 // We expect 42 edges (ONE)
282 if ( edges > 20 )
283 data ^= the_bit;
284
285 the_bit <<= 1;
286 }
287
288 // output
289 f->data = data;
290 f->bits = bits;
291
292 // log
293 uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
294 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
295 }
296
297 // Setup pm3 as a Legic Reader
298 static uint32_t setup_phase_reader(uint8_t iv) {
299
300 // Switch on carrier and let the tag charge for 5ms
301 HIGH(GPIO_SSC_DOUT);
302 WaitUS(5000);
303
304 ResetTicks();
305
306 legic_prng_init(0);
307
308 // send IV handshake
309 frame_sendAsReader(iv, 7);
310
311 // tag and reader has same IV.
312 legic_prng_init(iv);
313
314 frame_receiveAsReader(&current_frame, 6);
315
316 // 292us (438t) - fixed delay before sending ack.
317 // minus log and stuff 100tick?
318 WaitTicks(338);
319 legic_prng_forward(3);
320
321 // Send obsfuscated acknowledgment frame.
322 // 0x19 = 0x18 MIM22, 0x01 LSB READCMD
323 // 0x39 = 0x38 MIM256, MIM1024 0x01 LSB READCMD
324 switch ( current_frame.data ) {
325 case 0x0D: frame_sendAsReader(0x19, 6); break;
326 case 0x1D:
327 case 0x3D: frame_sendAsReader(0x39, 6); break;
328 default: break;
329 }
330
331 legic_prng_forward(2);
332 return current_frame.data;
333 }
334
335 void LegicCommonInit(bool clear_mem) {
336
337 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
338 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
339 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
340
341 /* Bitbang the transmitter */
342 SHORT_COIL;
343 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
344 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
345 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
346
347 // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
348 cardmem = BigBuf_get_EM_addr();
349 if ( clear_mem )
350 memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE);
351
352 clear_trace();
353 set_tracing(TRUE);
354 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
355
356 StartTicks();
357 }
358
359 // Switch off carrier, make sure tag is reset
360 static void switch_off_tag_rwd(void) {
361 SHORT_COIL;
362 WaitUS(20);
363 WDT_HIT();
364 }
365
366 // calculate crc4 for a legic READ command
367 static uint32_t legic4Crc(uint8_t cmd, uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
368 crc_clear(&legic_crc);
369 uint32_t temp = (value << cmd_sz) | (byte_index << 1) | cmd;
370 crc_update(&legic_crc, temp, cmd_sz + 8 );
371 return crc_finish(&legic_crc);
372 }
373
374 int legic_read_byte( uint16_t index, uint8_t cmd_sz) {
375
376 uint8_t byte, crc, calcCrc = 0;
377 uint32_t cmd = (index << 1) | LEGIC_READ;
378
379 // 90ticks = 60us (should be 100us but crc calc takes time.)
380 //WaitTicks(330); // 330ticks prng(4) - works
381 WaitTicks(240); // 240ticks prng(3) - works
382
383 frame_sendAsReader(cmd, cmd_sz);
384 frame_receiveAsReader(&current_frame, 12);
385
386 // CRC check.
387 byte = BYTEx(current_frame.data, 0);
388 crc = BYTEx(current_frame.data, 1);
389 calcCrc = legic4Crc(LEGIC_READ, index, byte, cmd_sz);
390
391 if( calcCrc != crc ) {
392 Dbprintf("!!! crc mismatch: %x != %x !!!", calcCrc, crc);
393 return -1;
394 }
395
396 legic_prng_forward(3);
397 return byte;
398 }
399
400 /*
401 * - assemble a write_cmd_frame with crc and send it
402 * - wait until the tag sends back an ACK ('1' bit unencrypted)
403 * - forward the prng based on the timing
404 */
405 bool legic_write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz) {
406
407 bool isOK = false;
408 int8_t i = 40;
409 uint8_t edges = 0;
410 uint8_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd;
411 uint32_t steps = 0, next_bit_at, start, crc, old_level = 0;
412
413 crc = legic4Crc(LEGIC_WRITE, index, byte, addr_sz+1);
414
415 // send write command
416 uint32_t cmd = LEGIC_WRITE;
417 cmd |= index << 1; // index
418 cmd |= byte << (addr_sz+1); // Data
419 cmd |= (crc & 0xF ) << (addr_sz+1+8); // CRC
420
421 WaitTicks(240);
422
423 frame_sendAsReader(cmd, cmd_sz);
424
425 LINE_IN;
426
427 start = GET_TICKS;
428
429 // ACK, - one single "1" bit after 3.6ms
430 // 3.6ms = 3600us * 1.5 = 5400ticks.
431 WaitTicks(5400);
432
433 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
434
435 while ( i-- ) {
436 WDT_HIT();
437 edges = 0;
438 while ( GET_TICKS < next_bit_at) {
439
440 volatile uint32_t level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
441
442 if (level != old_level)
443 ++edges;
444
445 old_level = level;
446 }
447
448 next_bit_at += TAG_BIT_PERIOD;
449
450 // We expect 42 edges (ONE)
451 if(edges > 20 ) {
452 steps = ( (GET_TICKS - start) / TAG_BIT_PERIOD);
453 legic_prng_forward(steps);
454 isOK = true;
455 goto OUT;
456 }
457 }
458
459 OUT: ;
460 legic_prng_forward(1);
461
462 uint8_t cmdbytes[] = {1, isOK, BYTEx(steps, 0), BYTEx(steps, 1) };
463 LogTrace(cmdbytes, sizeof(cmdbytes), start, GET_TICKS, NULL, FALSE);
464 return isOK;
465 }
466
467 int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) {
468
469 uint16_t i = 0;
470 uint8_t isOK = 1;
471 legic_card_select_t card;
472
473 LegicCommonInit(TRUE);
474
475 if ( legic_select_card_iv(&card, iv) ) {
476 isOK = 0;
477 goto OUT;
478 }
479
480 if (len + offset > card.cardsize)
481 len = card.cardsize - offset;
482
483 LED_B_ON();
484 while (i < len) {
485 int r = legic_read_byte(offset + i, card.cmdsize);
486
487 if (r == -1 || BUTTON_PRESS()) {
488 if ( MF_DBGLEVEL >= 2) DbpString("operation aborted");
489 isOK = 0;
490 goto OUT;
491 }
492 cardmem[i++] = r;
493 WDT_HIT();
494 }
495
496 OUT:
497 WDT_HIT();
498 switch_off_tag_rwd();
499 LEDsoff();
500 cmd_send(CMD_ACK, isOK, len, 0, cardmem, len);
501 return 0;
502 }
503
504 void LegicRfWriter(uint16_t offset, uint16_t len, uint8_t iv, uint8_t *data) {
505
506 #define LOWERLIMIT 4
507 uint8_t isOK = 1, msg = 0;
508 legic_card_select_t card;
509
510 // uid NOT is writeable.
511 if ( offset <= LOWERLIMIT ) {
512 isOK = 0;
513 goto OUT;
514 }
515
516 LegicCommonInit(TRUE);
517
518 if ( legic_select_card_iv(&card, iv) ) {
519 isOK = 0;
520 msg = 1;
521 goto OUT;
522 }
523
524 if ( len + offset > card.cardsize)
525 len = card.cardsize - offset;
526
527 LED_B_ON();
528 while( len > 0 ) {
529 --len;
530 if ( !legic_write_byte( len + offset, data[len], card.addrsize) ) {
531 Dbprintf("operation failed | %02X | %02X | %02X", len + offset, len, data[len] );
532 isOK = 0;
533 goto OUT;
534 }
535 WDT_HIT();
536 }
537 OUT:
538 cmd_send(CMD_ACK, isOK, msg,0,0,0);
539 switch_off_tag_rwd();
540 LEDsoff();
541 }
542
543 int legic_select_card_iv(legic_card_select_t *p_card, uint8_t iv){
544
545 if ( p_card == NULL ) return 1;
546
547 p_card->tagtype = setup_phase_reader(iv);
548
549 switch(p_card->tagtype) {
550 case 0x0d:
551 p_card->cmdsize = 6;
552 p_card->addrsize = 5;
553 p_card->cardsize = 22;
554 break;
555 case 0x1d:
556 p_card->cmdsize = 9;
557 p_card->addrsize = 8;
558 p_card->cardsize = 256;
559 break;
560 case 0x3d:
561 p_card->cmdsize = 11;
562 p_card->addrsize = 10;
563 p_card->cardsize = 1024;
564 break;
565 default:
566 p_card->cmdsize = 0;
567 p_card->addrsize = 0;
568 p_card->cardsize = 0;
569 return 2;
570 }
571 return 0;
572 }
573 int legic_select_card(legic_card_select_t *p_card){
574 return legic_select_card_iv(p_card, 0x01);
575 }
576
577 //-----------------------------------------------------------------------------
578 // Work with emulator memory
579 //
580 // Note: we call FpgaDownloadAndGo(FPGA_BITSTREAM_HF) here although FPGA is not
581 // involved in dealing with emulator memory. But if it is called later, it might
582 // destroy the Emulator Memory.
583 //-----------------------------------------------------------------------------
584 // arg0 = offset
585 // arg1 = num of bytes
586 void LegicEMemSet(uint32_t arg0, uint32_t arg1, uint8_t *data) {
587 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
588 legic_emlset_mem(data, arg0, arg1);
589 }
590 // arg0 = offset
591 // arg1 = num of bytes
592 void LegicEMemGet(uint32_t arg0, uint32_t arg1) {
593 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
594 uint8_t buf[USB_CMD_DATA_SIZE] = {0x00};
595 legic_emlget_mem(buf, arg0, arg1);
596 LED_B_ON();
597 cmd_send(CMD_ACK, arg0, arg1, 0, buf, USB_CMD_DATA_SIZE);
598 LED_B_OFF();
599 }
600 void legic_emlset_mem(uint8_t *data, int offset, int numofbytes) {
601 cardmem = BigBuf_get_EM_addr();
602 memcpy(cardmem + offset, data, numofbytes);
603 }
604 void legic_emlget_mem(uint8_t *data, int offset, int numofbytes) {
605 cardmem = BigBuf_get_EM_addr();
606 memcpy(data, cardmem + offset, numofbytes);
607 }
608
609 void LegicRfInfo(void){
610
611 int r;
612
613 uint8_t buf[sizeof(legic_card_select_t)] = {0x00};
614 legic_card_select_t *card = (legic_card_select_t*) buf;
615
616 LegicCommonInit(FALSE);
617
618 if ( legic_select_card(card) ) {
619 cmd_send(CMD_ACK,0,0,0,0,0);
620 goto OUT;
621 }
622
623 // read UID bytes
624 for ( uint8_t i = 0; i < sizeof(card->uid); ++i) {
625 r = legic_read_byte(i, card->cmdsize);
626 if ( r == -1 ) {
627 cmd_send(CMD_ACK,0,0,0,0,0);
628 goto OUT;
629 }
630 card->uid[i] = r & 0xFF;
631 }
632
633 // MCC byte.
634 r = legic_read_byte(4, card->cmdsize);
635 uint32_t calc_mcc = CRC8Legic(card->uid, 4);;
636 if ( r != calc_mcc) {
637 cmd_send(CMD_ACK,0,0,0,0,0);
638 goto OUT;
639 }
640
641 // OK
642 cmd_send(CMD_ACK, 1, 0, 0, buf, sizeof(legic_card_select_t));
643
644 OUT:
645 switch_off_tag_rwd();
646 LEDsoff();
647 }
648
649 /* Handle (whether to respond) a frame in tag mode
650 * Only called when simulating a tag.
651 */
652 static void frame_handle_tag(struct legic_frame const * const f)
653 {
654 // log
655 //uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
656 //LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
657 //Dbprintf("ICE: enter frame_handle_tag: %02x ", f->bits);
658
659 /* First Part of Handshake (IV) */
660 if(f->bits == 7) {
661
662 LED_C_ON();
663
664 // Reset prng timer
665 //ResetTimer(prng_timer);
666 ResetTicks();
667
668 // IV from reader.
669 legic_prng_init(f->data);
670
671 Dbprintf("ICE: IV: %02x ", f->data);
672
673 // We should have three tagtypes with three different answers.
674 legic_prng_forward(2);
675 //frame_send_tag(0x3d, 6); /* MIM1024 0x3d^0x26 = 0x1B */
676 frame_send_tag(0x1d, 6); // MIM256
677
678 legic_state = STATE_IV;
679 legic_read_count = 0;
680 legic_prng_bc = 0;
681 legic_prng_iv = f->data;
682
683 //ResetTimer(timer);
684 //WaitUS(280);
685 WaitTicks(388);
686 return;
687 }
688
689 /* 0x19==??? */
690 if(legic_state == STATE_IV) {
691 uint32_t local_key = get_key_stream(3, 6);
692 int xored = 0x39 ^ local_key;
693 if((f->bits == 6) && (f->data == xored)) {
694 legic_state = STATE_CON;
695
696 ResetTimer(timer);
697 WaitTicks(300);
698 return;
699
700 } else {
701 legic_state = STATE_DISCON;
702 LED_C_OFF();
703 Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored);
704 return;
705 }
706 }
707
708 /* Read */
709 if(f->bits == 11) {
710 if(legic_state == STATE_CON) {
711 uint32_t key = get_key_stream(2, 11); //legic_phase_drift, 11);
712 uint16_t addr = f->data ^ key;
713 addr >>= 1;
714 uint8_t data = cardmem[addr];
715
716 uint32_t crc = legic4Crc(LEGIC_READ, addr, data, 11) << 8;
717
718 //legic_read_count++;
719 //legic_prng_forward(legic_reqresp_drift);
720
721 frame_send_tag(crc | data, 12);
722 //ResetTimer(timer);
723 legic_prng_forward(2);
724 WaitTicks(330);
725 return;
726 }
727 }
728
729 /* Write */
730 if (f->bits == 23 || f->bits == 21 ) {
731 uint32_t key = get_key_stream(-1, 23); //legic_frame_drift, 23);
732 uint16_t addr = f->data ^ key;
733 addr >>= 1;
734 addr &= 0x3ff;
735 uint32_t data = f->data ^ key;
736 data >>= 11;
737 data &= 0xff;
738
739 cardmem[addr] = data;
740 /* write command */
741 legic_state = STATE_DISCON;
742 LED_C_OFF();
743 Dbprintf("write - addr: %x, data: %x", addr, data);
744 // should send a ACK after 3.6ms
745 return;
746 }
747
748 if(legic_state != STATE_DISCON) {
749 Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count);
750 Dbprintf("IV: %03.3x", legic_prng_iv);
751 }
752
753 legic_state = STATE_DISCON;
754 legic_read_count = 0;
755 WaitMS(10);
756 LED_C_OFF();
757 return;
758 }
759
760 /* Read bit by bit untill full frame is received
761 * Call to process frame end answer
762 */
763 static void emit(int bit) {
764
765 switch (bit) {
766 case 1:
767 frame_append_bit(&current_frame, 1);
768 break;
769 case 0:
770 frame_append_bit(&current_frame, 0);
771 break;
772 default:
773 if(current_frame.bits <= 4) {
774 frame_clean(&current_frame);
775 } else {
776 frame_handle_tag(&current_frame);
777 frame_clean(&current_frame);
778 }
779 WDT_HIT();
780 break;
781 }
782 }
783
784 void LegicRfSimulate(int phase, int frame, int reqresp)
785 {
786 /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
787 * modulation mode set to 212kHz subcarrier. We are getting the incoming raw
788 * envelope waveform on DIN and should send our response on DOUT.
789 *
790 * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
791 * measure the time between two rising edges on DIN, and no encoding on the
792 * subcarrier from card to reader, so we'll just shift out our verbatim data
793 * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
794 * seems to be 330us.
795 */
796
797 int old_level = 0, active = 0;
798 volatile int32_t level = 0;
799
800 legic_state = STATE_DISCON;
801 legic_phase_drift = phase;
802 legic_frame_drift = frame;
803 legic_reqresp_drift = reqresp;
804
805
806 /* to get the stream of bits from FPGA in sim mode.*/
807 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
808 // Set up the synchronous serial port
809 //FpgaSetupSsc();
810 // connect Demodulated Signal to ADC:
811 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
812 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
813 //FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
814
815 #define LEGIC_DMA_BUFFER 256
816 // The DMA buffer, used to stream samples from the FPGA
817 //uint8_t *dmaBuf = BigBuf_malloc(LEGIC_DMA_BUFFER);
818 //uint8_t *data = dmaBuf;
819 // Setup and start DMA.
820 // if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER) ){
821 // if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
822 // return;
823 // }
824
825 //StartCountSspClk();
826 /* Bitbang the receiver */
827 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
828 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
829
830 // need a way to determine which tagtype we are simulating
831
832 // hook up emulator memory
833 cardmem = BigBuf_get_EM_addr();
834
835 clear_trace();
836 set_tracing(TRUE);
837
838 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
839
840 StartTicks();
841
842 LED_B_ON();
843 DbpString("Starting Legic emulator, press button to end");
844
845 /*
846 * The mode FPGA_HF_SIMULATOR_MODULATE_212K works like this.
847 * - A 1-bit input to the FPGA becomes 8 pulses on 212kHz (fc/64) (18.88us).
848 * - A 0-bit input to the FPGA becomes an unmodulated time of 18.88us
849 *
850 * In this mode the SOF can be written as 00011101 = 0x1D
851 * The EOF can be written as 10111000 = 0xb8
852 * A logic 1 is 01
853 * A logic 0 is 10
854 volatile uint8_t b;
855 uint8_t i = 0;
856 while( !BUTTON_PRESS() ) {
857 WDT_HIT();
858
859 // not sending anything.
860 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
861 AT91C_BASE_SSC->SSC_THR = 0x00;
862 }
863
864 // receive
865 if ( AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY ) {
866 b = (uint8_t) AT91C_BASE_SSC->SSC_RHR;
867 bd[i] = b;
868 ++i;
869 // if(OutOfNDecoding(b & 0x0f))
870 // *len = Uart.byteCnt;
871 }
872
873 }
874 */
875
876 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
877
878 level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
879
880 uint32_t time = GET_TICKS;
881
882 if (level != old_level) {
883 if (level == 1) {
884
885 //Dbprintf("start, %u ", time);
886 StartTicks();
887 // did we get a signal
888 if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
889 // 1 bit
890 emit(1);
891 active = 1;
892 LED_A_ON();
893 } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
894 // 0 bit
895 emit(0);
896 active = 1;
897 LED_A_ON();
898 } else if (active) {
899 // invalid
900 emit(-1);
901 active = 0;
902 LED_A_OFF();
903 }
904 }
905 }
906
907
908 /* Frame end */
909 if(time >= (RWD_TIME_1 + RWD_TIME_FUZZ) && active) {
910 emit(-1);
911 active = 0;
912 LED_A_OFF();
913 }
914
915 /*
916 * Disable the counter, Then wait for the clock to acknowledge the
917 * shutdown in its status register. Reading the SR has the
918 * side-effect of clearing any pending state in there.
919 */
920 //if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA))
921 if(time >= (20 * RWD_TIME_1) )
922 StopTicks();
923
924 old_level = level;
925 WDT_HIT();
926 }
927
928 WDT_HIT();
929 DbpString("LEGIC Prime emulator stopped");
930 switch_off_tag_rwd();
931 FpgaDisableSscDma();
932 LEDsoff();
933 cmd_send(CMD_ACK, 1, 0, 0, 0, 0);
934 }
935
936
937 //-----------------------------------------------------------------------------
938 // Code up a string of octets at layer 2 (including CRC, we don't generate
939 // that here) so that they can be transmitted to the reader. Doesn't transmit
940 // them yet, just leaves them ready to send in ToSend[].
941 //-----------------------------------------------------------------------------
942 // static void CodeLegicAsTag(const uint8_t *cmd, int len)
943 // {
944 // int i;
945
946 // ToSendReset();
947
948 // // Transmit a burst of ones, as the initial thing that lets the
949 // // reader get phase sync. This (TR1) must be > 80/fs, per spec,
950 // // but tag that I've tried (a Paypass) exceeds that by a fair bit,
951 // // so I will too.
952 // for(i = 0; i < 20; i++) {
953 // ToSendStuffBit(1);
954 // ToSendStuffBit(1);
955 // ToSendStuffBit(1);
956 // ToSendStuffBit(1);
957 // }
958
959 // // Send SOF.
960 // for(i = 0; i < 10; i++) {
961 // ToSendStuffBit(0);
962 // ToSendStuffBit(0);
963 // ToSendStuffBit(0);
964 // ToSendStuffBit(0);
965 // }
966 // for(i = 0; i < 2; i++) {
967 // ToSendStuffBit(1);
968 // ToSendStuffBit(1);
969 // ToSendStuffBit(1);
970 // ToSendStuffBit(1);
971 // }
972
973 // for(i = 0; i < len; i++) {
974 // int j;
975 // uint8_t b = cmd[i];
976
977 // // Start bit
978 // ToSendStuffBit(0);
979 // ToSendStuffBit(0);
980 // ToSendStuffBit(0);
981 // ToSendStuffBit(0);
982
983 // // Data bits
984 // for(j = 0; j < 8; j++) {
985 // if(b & 1) {
986 // ToSendStuffBit(1);
987 // ToSendStuffBit(1);
988 // ToSendStuffBit(1);
989 // ToSendStuffBit(1);
990 // } else {
991 // ToSendStuffBit(0);
992 // ToSendStuffBit(0);
993 // ToSendStuffBit(0);
994 // ToSendStuffBit(0);
995 // }
996 // b >>= 1;
997 // }
998
999 // // Stop bit
1000 // ToSendStuffBit(1);
1001 // ToSendStuffBit(1);
1002 // ToSendStuffBit(1);
1003 // ToSendStuffBit(1);
1004 // }
1005
1006 // // Send EOF.
1007 // for(i = 0; i < 10; i++) {
1008 // ToSendStuffBit(0);
1009 // ToSendStuffBit(0);
1010 // ToSendStuffBit(0);
1011 // ToSendStuffBit(0);
1012 // }
1013 // for(i = 0; i < 2; i++) {
1014 // ToSendStuffBit(1);
1015 // ToSendStuffBit(1);
1016 // ToSendStuffBit(1);
1017 // ToSendStuffBit(1);
1018 // }
1019
1020 // // Convert from last byte pos to length
1021 // ToSendMax++;
1022 // }
1023
1024 //-----------------------------------------------------------------------------
1025 // The software UART that receives commands from the reader, and its state
1026 // variables.
1027 //-----------------------------------------------------------------------------
1028 /*
1029 static struct {
1030 enum {
1031 STATE_UNSYNCD,
1032 STATE_GOT_FALLING_EDGE_OF_SOF,
1033 STATE_AWAITING_START_BIT,
1034 STATE_RECEIVING_DATA
1035 } state;
1036 uint16_t shiftReg;
1037 int bitCnt;
1038 int byteCnt;
1039 int byteCntMax;
1040 int posCnt;
1041 uint8_t *output;
1042 } Uart;
1043 */
1044 /* Receive & handle a bit coming from the reader.
1045 *
1046 * This function is called 4 times per bit (every 2 subcarrier cycles).
1047 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1048 *
1049 * LED handling:
1050 * LED A -> ON once we have received the SOF and are expecting the rest.
1051 * LED A -> OFF once we have received EOF or are in error state or unsynced
1052 *
1053 * Returns: true if we received a EOF
1054 * false if we are still waiting for some more
1055 */
1056 // static RAMFUNC int HandleLegicUartBit(uint8_t bit)
1057 // {
1058 // switch(Uart.state) {
1059 // case STATE_UNSYNCD:
1060 // if(!bit) {
1061 // // we went low, so this could be the beginning of an SOF
1062 // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
1063 // Uart.posCnt = 0;
1064 // Uart.bitCnt = 0;
1065 // }
1066 // break;
1067
1068 // case STATE_GOT_FALLING_EDGE_OF_SOF:
1069 // Uart.posCnt++;
1070 // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
1071 // if(bit) {
1072 // if(Uart.bitCnt > 9) {
1073 // // we've seen enough consecutive
1074 // // zeros that it's a valid SOF
1075 // Uart.posCnt = 0;
1076 // Uart.byteCnt = 0;
1077 // Uart.state = STATE_AWAITING_START_BIT;
1078 // LED_A_ON(); // Indicate we got a valid SOF
1079 // } else {
1080 // // didn't stay down long enough
1081 // // before going high, error
1082 // Uart.state = STATE_UNSYNCD;
1083 // }
1084 // } else {
1085 // // do nothing, keep waiting
1086 // }
1087 // Uart.bitCnt++;
1088 // }
1089 // if(Uart.posCnt >= 4) Uart.posCnt = 0;
1090 // if(Uart.bitCnt > 12) {
1091 // // Give up if we see too many zeros without
1092 // // a one, too.
1093 // LED_A_OFF();
1094 // Uart.state = STATE_UNSYNCD;
1095 // }
1096 // break;
1097
1098 // case STATE_AWAITING_START_BIT:
1099 // Uart.posCnt++;
1100 // if(bit) {
1101 // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
1102 // // stayed high for too long between
1103 // // characters, error
1104 // Uart.state = STATE_UNSYNCD;
1105 // }
1106 // } else {
1107 // // falling edge, this starts the data byte
1108 // Uart.posCnt = 0;
1109 // Uart.bitCnt = 0;
1110 // Uart.shiftReg = 0;
1111 // Uart.state = STATE_RECEIVING_DATA;
1112 // }
1113 // break;
1114
1115 // case STATE_RECEIVING_DATA:
1116 // Uart.posCnt++;
1117 // if(Uart.posCnt == 2) {
1118 // // time to sample a bit
1119 // Uart.shiftReg >>= 1;
1120 // if(bit) {
1121 // Uart.shiftReg |= 0x200;
1122 // }
1123 // Uart.bitCnt++;
1124 // }
1125 // if(Uart.posCnt >= 4) {
1126 // Uart.posCnt = 0;
1127 // }
1128 // if(Uart.bitCnt == 10) {
1129 // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
1130 // {
1131 // // this is a data byte, with correct
1132 // // start and stop bits
1133 // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
1134 // Uart.byteCnt++;
1135
1136 // if(Uart.byteCnt >= Uart.byteCntMax) {
1137 // // Buffer overflowed, give up
1138 // LED_A_OFF();
1139 // Uart.state = STATE_UNSYNCD;
1140 // } else {
1141 // // so get the next byte now
1142 // Uart.posCnt = 0;
1143 // Uart.state = STATE_AWAITING_START_BIT;
1144 // }
1145 // } else if (Uart.shiftReg == 0x000) {
1146 // // this is an EOF byte
1147 // LED_A_OFF(); // Finished receiving
1148 // Uart.state = STATE_UNSYNCD;
1149 // if (Uart.byteCnt != 0) {
1150 // return TRUE;
1151 // }
1152 // } else {
1153 // // this is an error
1154 // LED_A_OFF();
1155 // Uart.state = STATE_UNSYNCD;
1156 // }
1157 // }
1158 // break;
1159
1160 // default:
1161 // LED_A_OFF();
1162 // Uart.state = STATE_UNSYNCD;
1163 // break;
1164 // }
1165
1166 // return FALSE;
1167 // }
1168 /*
1169
1170 static void UartReset() {
1171 Uart.byteCntMax = 3;
1172 Uart.state = STATE_UNSYNCD;
1173 Uart.byteCnt = 0;
1174 Uart.bitCnt = 0;
1175 Uart.posCnt = 0;
1176 memset(Uart.output, 0x00, 3);
1177 }
1178 */
1179 // static void UartInit(uint8_t *data) {
1180 // Uart.output = data;
1181 // UartReset();
1182 // }
1183
1184 //=============================================================================
1185 // An LEGIC reader. We take layer two commands, code them
1186 // appropriately, and then send them to the tag. We then listen for the
1187 // tag's response, which we leave in the buffer to be demodulated on the
1188 // PC side.
1189 //=============================================================================
1190 /*
1191 static struct {
1192 enum {
1193 DEMOD_UNSYNCD,
1194 DEMOD_PHASE_REF_TRAINING,
1195 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
1196 DEMOD_GOT_FALLING_EDGE_OF_SOF,
1197 DEMOD_AWAITING_START_BIT,
1198 DEMOD_RECEIVING_DATA
1199 } state;
1200 int bitCount;
1201 int posCount;
1202 int thisBit;
1203 uint16_t shiftReg;
1204 uint8_t *output;
1205 int len;
1206 int sumI;
1207 int sumQ;
1208 } Demod;
1209 */
1210 /*
1211 * Handles reception of a bit from the tag
1212 *
1213 * This function is called 2 times per bit (every 4 subcarrier cycles).
1214 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1215 *
1216 * LED handling:
1217 * LED C -> ON once we have received the SOF and are expecting the rest.
1218 * LED C -> OFF once we have received EOF or are unsynced
1219 *
1220 * Returns: true if we received a EOF
1221 * false if we are still waiting for some more
1222 *
1223 */
1224
1225 /*
1226 static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq)
1227 {
1228 int v = 0;
1229 int ai = ABS(ci);
1230 int aq = ABS(cq);
1231 int halfci = (ai >> 1);
1232 int halfcq = (aq >> 1);
1233
1234 switch(Demod.state) {
1235 case DEMOD_UNSYNCD:
1236
1237 CHECK_FOR_SUBCARRIER()
1238
1239 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
1240 Demod.state = DEMOD_PHASE_REF_TRAINING;
1241 Demod.sumI = ci;
1242 Demod.sumQ = cq;
1243 Demod.posCount = 1;
1244 }
1245 break;
1246
1247 case DEMOD_PHASE_REF_TRAINING:
1248 if(Demod.posCount < 8) {
1249
1250 CHECK_FOR_SUBCARRIER()
1251
1252 if (v > SUBCARRIER_DETECT_THRESHOLD) {
1253 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
1254 // note: synchronization time > 80 1/fs
1255 Demod.sumI += ci;
1256 Demod.sumQ += cq;
1257 ++Demod.posCount;
1258 } else {
1259 // subcarrier lost
1260 Demod.state = DEMOD_UNSYNCD;
1261 }
1262 } else {
1263 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
1264 }
1265 break;
1266
1267 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
1268
1269 MAKE_SOFT_DECISION()
1270
1271 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
1272 // logic '0' detected
1273 if (v <= 0) {
1274
1275 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
1276
1277 // start of SOF sequence
1278 Demod.posCount = 0;
1279 } else {
1280 // maximum length of TR1 = 200 1/fs
1281 if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
1282 }
1283 ++Demod.posCount;
1284 break;
1285
1286 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
1287 ++Demod.posCount;
1288
1289 MAKE_SOFT_DECISION()
1290
1291 if(v > 0) {
1292 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
1293 if(Demod.posCount < 10*2) {
1294 Demod.state = DEMOD_UNSYNCD;
1295 } else {
1296 LED_C_ON(); // Got SOF
1297 Demod.state = DEMOD_AWAITING_START_BIT;
1298 Demod.posCount = 0;
1299 Demod.len = 0;
1300 }
1301 } else {
1302 // low phase of SOF too long (> 12 etu)
1303 if(Demod.posCount > 13*2) {
1304 Demod.state = DEMOD_UNSYNCD;
1305 LED_C_OFF();
1306 }
1307 }
1308 break;
1309
1310 case DEMOD_AWAITING_START_BIT:
1311 ++Demod.posCount;
1312
1313 MAKE_SOFT_DECISION()
1314
1315 if(v > 0) {
1316 // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
1317 if(Demod.posCount > 3*2) {
1318 Demod.state = DEMOD_UNSYNCD;
1319 LED_C_OFF();
1320 }
1321 } else {
1322 // start bit detected
1323 Demod.bitCount = 0;
1324 Demod.posCount = 1; // this was the first half
1325 Demod.thisBit = v;
1326 Demod.shiftReg = 0;
1327 Demod.state = DEMOD_RECEIVING_DATA;
1328 }
1329 break;
1330
1331 case DEMOD_RECEIVING_DATA:
1332
1333 MAKE_SOFT_DECISION()
1334
1335 if(Demod.posCount == 0) {
1336 // first half of bit
1337 Demod.thisBit = v;
1338 Demod.posCount = 1;
1339 } else {
1340 // second half of bit
1341 Demod.thisBit += v;
1342 Demod.shiftReg >>= 1;
1343 // logic '1'
1344 if(Demod.thisBit > 0)
1345 Demod.shiftReg |= 0x200;
1346
1347 ++Demod.bitCount;
1348
1349 if(Demod.bitCount == 10) {
1350
1351 uint16_t s = Demod.shiftReg;
1352
1353 if((s & 0x200) && !(s & 0x001)) {
1354 // stop bit == '1', start bit == '0'
1355 uint8_t b = (s >> 1);
1356 Demod.output[Demod.len] = b;
1357 ++Demod.len;
1358 Demod.state = DEMOD_AWAITING_START_BIT;
1359 } else {
1360 Demod.state = DEMOD_UNSYNCD;
1361 LED_C_OFF();
1362
1363 if(s == 0x000) {
1364 // This is EOF (start, stop and all data bits == '0'
1365 return TRUE;
1366 }
1367 }
1368 }
1369 Demod.posCount = 0;
1370 }
1371 break;
1372
1373 default:
1374 Demod.state = DEMOD_UNSYNCD;
1375 LED_C_OFF();
1376 break;
1377 }
1378 return FALSE;
1379 }
1380 */
1381 /*
1382 // Clear out the state of the "UART" that receives from the tag.
1383 static void DemodReset() {
1384 Demod.len = 0;
1385 Demod.state = DEMOD_UNSYNCD;
1386 Demod.posCount = 0;
1387 Demod.sumI = 0;
1388 Demod.sumQ = 0;
1389 Demod.bitCount = 0;
1390 Demod.thisBit = 0;
1391 Demod.shiftReg = 0;
1392 memset(Demod.output, 0x00, 3);
1393 }
1394
1395 static void DemodInit(uint8_t *data) {
1396 Demod.output = data;
1397 DemodReset();
1398 }
1399 */
1400
1401 /*
1402 * Demodulate the samples we received from the tag, also log to tracebuffer
1403 * quiet: set to 'TRUE' to disable debug output
1404 */
1405
1406 /*
1407 #define LEGIC_DMA_BUFFER_SIZE 256
1408
1409 static void GetSamplesForLegicDemod(int n, bool quiet)
1410 {
1411 int max = 0;
1412 bool gotFrame = FALSE;
1413 int lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1414 int ci, cq, samples = 0;
1415
1416 BigBuf_free();
1417
1418 // And put the FPGA in the appropriate mode
1419 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ);
1420
1421 // The response (tag -> reader) that we're receiving.
1422 // Set up the demodulator for tag -> reader responses.
1423 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1424
1425 // The DMA buffer, used to stream samples from the FPGA
1426 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE);
1427 int8_t *upTo = dmaBuf;
1428
1429 // Setup and start DMA.
1430 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){
1431 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1432 return;
1433 }
1434
1435 // Signal field is ON with the appropriate LED:
1436 LED_D_ON();
1437 for(;;) {
1438 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
1439 if(behindBy > max) max = behindBy;
1440
1441 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) {
1442 ci = upTo[0];
1443 cq = upTo[1];
1444 upTo += 2;
1445 if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) {
1446 upTo = dmaBuf;
1447 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
1448 AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE;
1449 }
1450 lastRxCounter -= 2;
1451 if(lastRxCounter <= 0)
1452 lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1453
1454 samples += 2;
1455
1456 gotFrame = HandleLegicSamplesDemod(ci , cq );
1457 if ( gotFrame )
1458 break;
1459 }
1460
1461 if(samples > n || gotFrame)
1462 break;
1463 }
1464
1465 FpgaDisableSscDma();
1466
1467 if (!quiet && Demod.len == 0) {
1468 Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
1469 max,
1470 samples,
1471 gotFrame,
1472 Demod.len,
1473 Demod.sumI,
1474 Demod.sumQ
1475 );
1476 }
1477
1478 //Tracing
1479 if (Demod.len > 0) {
1480 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1481 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
1482 }
1483 }
1484
1485 */
1486
1487 //-----------------------------------------------------------------------------
1488 // Transmit the command (to the tag) that was placed in ToSend[].
1489 //-----------------------------------------------------------------------------
1490 /*
1491 static void TransmitForLegic(void)
1492 {
1493 int c;
1494
1495 FpgaSetupSsc();
1496
1497 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
1498 AT91C_BASE_SSC->SSC_THR = 0xff;
1499
1500 // Signal field is ON with the appropriate Red LED
1501 LED_D_ON();
1502
1503 // Signal we are transmitting with the Green LED
1504 LED_B_ON();
1505 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1506
1507 for(c = 0; c < 10;) {
1508 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1509 AT91C_BASE_SSC->SSC_THR = 0xff;
1510 c++;
1511 }
1512 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1513 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1514 (void)r;
1515 }
1516 WDT_HIT();
1517 }
1518
1519 c = 0;
1520 for(;;) {
1521 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1522 AT91C_BASE_SSC->SSC_THR = ToSend[c];
1523 legic_prng_forward(1); // forward the lfsr
1524 c++;
1525 if(c >= ToSendMax) {
1526 break;
1527 }
1528 }
1529 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1530 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1531 (void)r;
1532 }
1533 WDT_HIT();
1534 }
1535 LED_B_OFF();
1536 }
1537 */
1538
1539 //-----------------------------------------------------------------------------
1540 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1541 // so that it is ready to transmit to the tag using TransmitForLegic().
1542 //-----------------------------------------------------------------------------
1543 /*
1544 static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1545 {
1546 int i, j;
1547 uint8_t b;
1548
1549 ToSendReset();
1550
1551 // Send SOF
1552 for(i = 0; i < 7; i++)
1553 ToSendStuffBit(1);
1554
1555
1556 for(i = 0; i < cmdlen; i++) {
1557 // Start bit
1558 ToSendStuffBit(0);
1559
1560 // Data bits
1561 b = cmd[i];
1562 for(j = 0; j < bits; j++) {
1563 if(b & 1) {
1564 ToSendStuffBit(1);
1565 } else {
1566 ToSendStuffBit(0);
1567 }
1568 b >>= 1;
1569 }
1570 }
1571
1572 // Convert from last character reference to length
1573 ++ToSendMax;
1574 }
1575 */
1576 /**
1577 Convenience function to encode, transmit and trace Legic comms
1578 **/
1579 /*
1580 static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1581 {
1582 CodeLegicBitsAsReader(cmd, cmdlen, bits);
1583 TransmitForLegic();
1584 if (tracing) {
1585 uint8_t parity[1] = {0x00};
1586 LogTrace(cmd, cmdlen, 0, 0, parity, TRUE);
1587 }
1588 }
1589
1590 */
1591 // Set up LEGIC communication
1592 /*
1593 void ice_legic_setup() {
1594
1595 // standard things.
1596 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1597 BigBuf_free(); BigBuf_Clear_ext(false);
1598 clear_trace();
1599 set_tracing(TRUE);
1600 DemodReset();
1601 UartReset();
1602
1603 // Set up the synchronous serial port
1604 FpgaSetupSsc();
1605
1606 // connect Demodulated Signal to ADC:
1607 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1608
1609 // Signal field is on with the appropriate LED
1610 LED_D_ON();
1611 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1612 SpinDelay(20);
1613 // Start the timer
1614 //StartCountSspClk();
1615
1616 // initalize CRC
1617 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
1618
1619 // initalize prng
1620 legic_prng_init(0);
1621 }
1622 */
Proxmark3 GIT tracking
Impressum, Datenschutz