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Merge pull request #861 from pwpiwi/iclass_MAC_speedup
[proxmark3-svn] / armsrc / iclass.c
1 //-----------------------------------------------------------------------------
2 // Gerhard de Koning Gans - May 2008
3 // Hagen Fritsch - June 2010
4 // Gerhard de Koning Gans - May 2011
5 // Gerhard de Koning Gans - June 2012 - Added iClass card and reader emulation
6 //
7 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
8 // at your option, any later version. See the LICENSE.txt file for the text of
9 // the license.
10 //-----------------------------------------------------------------------------
11 // Routines to support iClass.
12 //-----------------------------------------------------------------------------
13 // Based on ISO14443a implementation. Still in experimental phase.
14 // Contribution made during a security research at Radboud University Nijmegen
15 //
16 // Please feel free to contribute and extend iClass support!!
17 //-----------------------------------------------------------------------------
18 //
19 // FIX:
20 // ====
21 // We still have sometimes a demodulation error when snooping iClass communication.
22 // The resulting trace of a read-block-03 command may look something like this:
23 //
24 // + 22279: : 0c 03 e8 01
25 //
26 // ...with an incorrect answer...
27 //
28 // + 85: 0: TAG ff! ff! ff! ff! ff! ff! ff! ff! bb 33 bb 00 01! 0e! 04! bb !crc
29 //
30 // We still left the error signalling bytes in the traces like 0xbb
31 //
32 // A correct trace should look like this:
33 //
34 // + 21112: : 0c 03 e8 01
35 // + 85: 0: TAG ff ff ff ff ff ff ff ff ea f5
36 //
37 //-----------------------------------------------------------------------------
38
39 #include "iclass.h"
40
41 #include "proxmark3.h"
42 #include "apps.h"
43 #include "util.h"
44 #include "string.h"
45 #include "common.h"
46 #include "cmd.h"
47 #include "iso14443a.h"
48 // Needed for CRC in emulation mode;
49 // same construction as in ISO 14443;
50 // different initial value (CRC_ICLASS)
51 #include "iso14443crc.h"
52 #include "iso15693tools.h"
53 #include "protocols.h"
54 #include "optimized_cipher.h"
55 #include "usb_cdc.h" // for usb_poll_validate_length
56 #include "fpgaloader.h"
57
58 static int timeout = 4096;
59
60 //-----------------------------------------------------------------------------
61 // The software UART that receives commands from the reader, and its state
62 // variables.
63 //-----------------------------------------------------------------------------
64 static struct {
65 enum {
66 STATE_UNSYNCD,
67 STATE_START_OF_COMMUNICATION,
68 STATE_RECEIVING
69 } state;
70 uint16_t shiftReg;
71 int bitCnt;
72 int byteCnt;
73 int byteCntMax;
74 int posCnt;
75 int nOutOfCnt;
76 int OutOfCnt;
77 int syncBit;
78 int samples;
79 int highCnt;
80 int swapper;
81 int counter;
82 int bitBuffer;
83 int dropPosition;
84 uint8_t *output;
85 } Uart;
86
87 static RAMFUNC int OutOfNDecoding(int bit) {
88 //int error = 0;
89 int bitright;
90
91 if (!Uart.bitBuffer) {
92 Uart.bitBuffer = bit ^ 0xFF0;
93 return false;
94 } else {
95 Uart.bitBuffer <<= 4;
96 Uart.bitBuffer ^= bit;
97 }
98
99 /*if (Uart.swapper) {
100 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
101 Uart.byteCnt++;
102 Uart.swapper = 0;
103 if (Uart.byteCnt > 15) { return true; }
104 }
105 else {
106 Uart.swapper = 1;
107 }*/
108
109 if (Uart.state != STATE_UNSYNCD) {
110 Uart.posCnt++;
111
112 if ((Uart.bitBuffer & Uart.syncBit) ^ Uart.syncBit) {
113 bit = 0x00;
114 } else {
115 bit = 0x01;
116 }
117 if (((Uart.bitBuffer << 1) & Uart.syncBit) ^ Uart.syncBit) {
118 bitright = 0x00;
119 } else {
120 bitright = 0x01;
121 }
122 if (bit != bitright) {
123 bit = bitright;
124 }
125
126
127 // So, now we only have to deal with *bit*, lets see...
128 if (Uart.posCnt == 1) {
129 // measurement first half bitperiod
130 if (!bit) {
131 // Drop in first half means that we are either seeing
132 // an SOF or an EOF.
133
134 if (Uart.nOutOfCnt == 1) {
135 // End of Communication
136 Uart.state = STATE_UNSYNCD;
137 Uart.highCnt = 0;
138 if (Uart.byteCnt == 0) {
139 // Its not straightforward to show single EOFs
140 // So just leave it and do not return true
141 Uart.output[0] = 0xf0;
142 Uart.byteCnt++;
143 } else {
144 return true;
145 }
146 } else if (Uart.state != STATE_START_OF_COMMUNICATION) {
147 // When not part of SOF or EOF, it is an error
148 Uart.state = STATE_UNSYNCD;
149 Uart.highCnt = 0;
150 //error = 4;
151 }
152 }
153 } else {
154 // measurement second half bitperiod
155 // Count the bitslot we are in... (ISO 15693)
156 Uart.nOutOfCnt++;
157
158 if (!bit) {
159 if (Uart.dropPosition) {
160 if (Uart.state == STATE_START_OF_COMMUNICATION) {
161 //error = 1;
162 } else {
163 //error = 7;
164 }
165 // It is an error if we already have seen a drop in current frame
166 Uart.state = STATE_UNSYNCD;
167 Uart.highCnt = 0;
168 } else {
169 Uart.dropPosition = Uart.nOutOfCnt;
170 }
171 }
172
173 Uart.posCnt = 0;
174
175
176 if (Uart.nOutOfCnt == Uart.OutOfCnt && Uart.OutOfCnt == 4) {
177 Uart.nOutOfCnt = 0;
178
179 if (Uart.state == STATE_START_OF_COMMUNICATION) {
180 if (Uart.dropPosition == 4) {
181 Uart.state = STATE_RECEIVING;
182 Uart.OutOfCnt = 256;
183 } else if (Uart.dropPosition == 3) {
184 Uart.state = STATE_RECEIVING;
185 Uart.OutOfCnt = 4;
186 //Uart.output[Uart.byteCnt] = 0xdd;
187 //Uart.byteCnt++;
188 } else {
189 Uart.state = STATE_UNSYNCD;
190 Uart.highCnt = 0;
191 }
192 Uart.dropPosition = 0;
193 } else {
194 // RECEIVING DATA
195 // 1 out of 4
196 if (!Uart.dropPosition) {
197 Uart.state = STATE_UNSYNCD;
198 Uart.highCnt = 0;
199 //error = 9;
200 } else {
201 Uart.shiftReg >>= 2;
202
203 // Swap bit order
204 Uart.dropPosition--;
205 //if (Uart.dropPosition == 1) { Uart.dropPosition = 2; }
206 //else if (Uart.dropPosition == 2) { Uart.dropPosition = 1; }
207
208 Uart.shiftReg ^= ((Uart.dropPosition & 0x03) << 6);
209 Uart.bitCnt += 2;
210 Uart.dropPosition = 0;
211
212 if (Uart.bitCnt == 8) {
213 Uart.output[Uart.byteCnt] = (Uart.shiftReg & 0xff);
214 Uart.byteCnt++;
215 Uart.bitCnt = 0;
216 Uart.shiftReg = 0;
217 }
218 }
219 }
220 } else if (Uart.nOutOfCnt == Uart.OutOfCnt) {
221 // RECEIVING DATA
222 // 1 out of 256
223 if (!Uart.dropPosition) {
224 Uart.state = STATE_UNSYNCD;
225 Uart.highCnt = 0;
226 //error = 3;
227 } else {
228 Uart.dropPosition--;
229 Uart.output[Uart.byteCnt] = (Uart.dropPosition & 0xff);
230 Uart.byteCnt++;
231 Uart.bitCnt = 0;
232 Uart.shiftReg = 0;
233 Uart.nOutOfCnt = 0;
234 Uart.dropPosition = 0;
235 }
236 }
237
238 /*if (error) {
239 Uart.output[Uart.byteCnt] = 0xAA;
240 Uart.byteCnt++;
241 Uart.output[Uart.byteCnt] = error & 0xFF;
242 Uart.byteCnt++;
243 Uart.output[Uart.byteCnt] = 0xAA;
244 Uart.byteCnt++;
245 Uart.output[Uart.byteCnt] = (Uart.bitBuffer >> 8) & 0xFF;
246 Uart.byteCnt++;
247 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
248 Uart.byteCnt++;
249 Uart.output[Uart.byteCnt] = (Uart.syncBit >> 3) & 0xFF;
250 Uart.byteCnt++;
251 Uart.output[Uart.byteCnt] = 0xAA;
252 Uart.byteCnt++;
253 return true;
254 }*/
255 }
256
257 } else {
258 bit = Uart.bitBuffer & 0xf0;
259 bit >>= 4;
260 bit ^= 0x0F; // drops become 1s ;-)
261 if (bit) {
262 // should have been high or at least (4 * 128) / fc
263 // according to ISO this should be at least (9 * 128 + 20) / fc
264 if (Uart.highCnt == 8) {
265 // we went low, so this could be start of communication
266 // it turns out to be safer to choose a less significant
267 // syncbit... so we check whether the neighbour also represents the drop
268 Uart.posCnt = 1; // apparently we are busy with our first half bit period
269 Uart.syncBit = bit & 8;
270 Uart.samples = 3;
271 if (!Uart.syncBit) { Uart.syncBit = bit & 4; Uart.samples = 2; }
272 else if (bit & 4) { Uart.syncBit = bit & 4; Uart.samples = 2; bit <<= 2; }
273 if (!Uart.syncBit) { Uart.syncBit = bit & 2; Uart.samples = 1; }
274 else if (bit & 2) { Uart.syncBit = bit & 2; Uart.samples = 1; bit <<= 1; }
275 if (!Uart.syncBit) { Uart.syncBit = bit & 1; Uart.samples = 0;
276 if (Uart.syncBit && (Uart.bitBuffer & 8)) {
277 Uart.syncBit = 8;
278
279 // the first half bit period is expected in next sample
280 Uart.posCnt = 0;
281 Uart.samples = 3;
282 }
283 } else if (bit & 1) { Uart.syncBit = bit & 1; Uart.samples = 0; }
284
285 Uart.syncBit <<= 4;
286 Uart.state = STATE_START_OF_COMMUNICATION;
287 Uart.bitCnt = 0;
288 Uart.byteCnt = 0;
289 Uart.nOutOfCnt = 0;
290 Uart.OutOfCnt = 4; // Start at 1/4, could switch to 1/256
291 Uart.dropPosition = 0;
292 Uart.shiftReg = 0;
293 //error = 0;
294 } else {
295 Uart.highCnt = 0;
296 }
297 } else if (Uart.highCnt < 8) {
298 Uart.highCnt++;
299 }
300 }
301
302 return false;
303 }
304
305
306 //=============================================================================
307 // Manchester
308 //=============================================================================
309
310 static struct {
311 enum {
312 DEMOD_UNSYNCD,
313 DEMOD_START_OF_COMMUNICATION,
314 DEMOD_START_OF_COMMUNICATION2,
315 DEMOD_START_OF_COMMUNICATION3,
316 DEMOD_SOF_COMPLETE,
317 DEMOD_MANCHESTER_D,
318 DEMOD_MANCHESTER_E,
319 DEMOD_END_OF_COMMUNICATION,
320 DEMOD_END_OF_COMMUNICATION2,
321 DEMOD_MANCHESTER_F,
322 DEMOD_ERROR_WAIT
323 } state;
324 int bitCount;
325 int posCount;
326 int syncBit;
327 uint16_t shiftReg;
328 int buffer;
329 int buffer2;
330 int buffer3;
331 int buff;
332 int samples;
333 int len;
334 enum {
335 SUB_NONE,
336 SUB_FIRST_HALF,
337 SUB_SECOND_HALF,
338 SUB_BOTH
339 } sub;
340 uint8_t *output;
341 } Demod;
342
343 static RAMFUNC int ManchesterDecoding(int v) {
344 int bit;
345 int modulation;
346 int error = 0;
347
348 bit = Demod.buffer;
349 Demod.buffer = Demod.buffer2;
350 Demod.buffer2 = Demod.buffer3;
351 Demod.buffer3 = v;
352
353 if (Demod.buff < 3) {
354 Demod.buff++;
355 return false;
356 }
357
358 if (Demod.state==DEMOD_UNSYNCD) {
359 Demod.output[Demod.len] = 0xfa;
360 Demod.syncBit = 0;
361 //Demod.samples = 0;
362 Demod.posCount = 1; // This is the first half bit period, so after syncing handle the second part
363
364 if (bit & 0x08) {
365 Demod.syncBit = 0x08;
366 }
367
368 if (bit & 0x04) {
369 if (Demod.syncBit) {
370 bit <<= 4;
371 }
372 Demod.syncBit = 0x04;
373 }
374
375 if (bit & 0x02) {
376 if (Demod.syncBit) {
377 bit <<= 2;
378 }
379 Demod.syncBit = 0x02;
380 }
381
382 if (bit & 0x01 && Demod.syncBit) {
383 Demod.syncBit = 0x01;
384 }
385
386 if (Demod.syncBit) {
387 Demod.len = 0;
388 Demod.state = DEMOD_START_OF_COMMUNICATION;
389 Demod.sub = SUB_FIRST_HALF;
390 Demod.bitCount = 0;
391 Demod.shiftReg = 0;
392 Demod.samples = 0;
393 if (Demod.posCount) {
394 //if (trigger) LED_A_OFF(); // Not useful in this case...
395 switch(Demod.syncBit) {
396 case 0x08: Demod.samples = 3; break;
397 case 0x04: Demod.samples = 2; break;
398 case 0x02: Demod.samples = 1; break;
399 case 0x01: Demod.samples = 0; break;
400 }
401 // SOF must be long burst... otherwise stay unsynced!!!
402 if (!(Demod.buffer & Demod.syncBit) || !(Demod.buffer2 & Demod.syncBit)) {
403 Demod.state = DEMOD_UNSYNCD;
404 }
405 } else {
406 // SOF must be long burst... otherwise stay unsynced!!!
407 if (!(Demod.buffer2 & Demod.syncBit) || !(Demod.buffer3 & Demod.syncBit)) {
408 Demod.state = DEMOD_UNSYNCD;
409 error = 0x88;
410 }
411
412 }
413 error = 0;
414
415 }
416 } else {
417 modulation = bit & Demod.syncBit;
418 modulation |= ((bit << 1) ^ ((Demod.buffer & 0x08) >> 3)) & Demod.syncBit;
419
420 Demod.samples += 4;
421
422 if (Demod.posCount==0) {
423 Demod.posCount = 1;
424 if (modulation) {
425 Demod.sub = SUB_FIRST_HALF;
426 } else {
427 Demod.sub = SUB_NONE;
428 }
429 } else {
430 Demod.posCount = 0;
431 /*(modulation && (Demod.sub == SUB_FIRST_HALF)) {
432 if (Demod.state!=DEMOD_ERROR_WAIT) {
433 Demod.state = DEMOD_ERROR_WAIT;
434 Demod.output[Demod.len] = 0xaa;
435 error = 0x01;
436 }
437 }*/
438 //else if (modulation) {
439 if (modulation) {
440 if (Demod.sub == SUB_FIRST_HALF) {
441 Demod.sub = SUB_BOTH;
442 } else {
443 Demod.sub = SUB_SECOND_HALF;
444 }
445 } else if (Demod.sub == SUB_NONE) {
446 if (Demod.state == DEMOD_SOF_COMPLETE) {
447 Demod.output[Demod.len] = 0x0f;
448 Demod.len++;
449 Demod.state = DEMOD_UNSYNCD;
450 // error = 0x0f;
451 return true;
452 } else {
453 Demod.state = DEMOD_ERROR_WAIT;
454 error = 0x33;
455 }
456 /*if (Demod.state!=DEMOD_ERROR_WAIT) {
457 Demod.state = DEMOD_ERROR_WAIT;
458 Demod.output[Demod.len] = 0xaa;
459 error = 0x01;
460 }*/
461 }
462
463 switch(Demod.state) {
464 case DEMOD_START_OF_COMMUNICATION:
465 if (Demod.sub == SUB_BOTH) {
466 //Demod.state = DEMOD_MANCHESTER_D;
467 Demod.state = DEMOD_START_OF_COMMUNICATION2;
468 Demod.posCount = 1;
469 Demod.sub = SUB_NONE;
470 } else {
471 Demod.output[Demod.len] = 0xab;
472 Demod.state = DEMOD_ERROR_WAIT;
473 error = 0xd2;
474 }
475 break;
476 case DEMOD_START_OF_COMMUNICATION2:
477 if (Demod.sub == SUB_SECOND_HALF) {
478 Demod.state = DEMOD_START_OF_COMMUNICATION3;
479 } else {
480 Demod.output[Demod.len] = 0xab;
481 Demod.state = DEMOD_ERROR_WAIT;
482 error = 0xd3;
483 }
484 break;
485 case DEMOD_START_OF_COMMUNICATION3:
486 if (Demod.sub == SUB_SECOND_HALF) {
487 // Demod.state = DEMOD_MANCHESTER_D;
488 Demod.state = DEMOD_SOF_COMPLETE;
489 //Demod.output[Demod.len] = Demod.syncBit & 0xFF;
490 //Demod.len++;
491 } else {
492 Demod.output[Demod.len] = 0xab;
493 Demod.state = DEMOD_ERROR_WAIT;
494 error = 0xd4;
495 }
496 break;
497 case DEMOD_SOF_COMPLETE:
498 case DEMOD_MANCHESTER_D:
499 case DEMOD_MANCHESTER_E:
500 // OPPOSITE FROM ISO14443 - 11110000 = 0 (1 in 14443)
501 // 00001111 = 1 (0 in 14443)
502 if (Demod.sub == SUB_SECOND_HALF) { // SUB_FIRST_HALF
503 Demod.bitCount++;
504 Demod.shiftReg = (Demod.shiftReg >> 1) ^ 0x100;
505 Demod.state = DEMOD_MANCHESTER_D;
506 } else if (Demod.sub == SUB_FIRST_HALF) { // SUB_SECOND_HALF
507 Demod.bitCount++;
508 Demod.shiftReg >>= 1;
509 Demod.state = DEMOD_MANCHESTER_E;
510 } else if (Demod.sub == SUB_BOTH) {
511 Demod.state = DEMOD_MANCHESTER_F;
512 } else {
513 Demod.state = DEMOD_ERROR_WAIT;
514 error = 0x55;
515 }
516 break;
517
518 case DEMOD_MANCHESTER_F:
519 // Tag response does not need to be a complete byte!
520 if (Demod.len > 0 || Demod.bitCount > 0) {
521 if (Demod.bitCount > 1) { // was > 0, do not interpret last closing bit, is part of EOF
522 Demod.shiftReg >>= (9 - Demod.bitCount); // right align data
523 Demod.output[Demod.len] = Demod.shiftReg & 0xff;
524 Demod.len++;
525 }
526
527 Demod.state = DEMOD_UNSYNCD;
528 return true;
529 } else {
530 Demod.output[Demod.len] = 0xad;
531 Demod.state = DEMOD_ERROR_WAIT;
532 error = 0x03;
533 }
534 break;
535
536 case DEMOD_ERROR_WAIT:
537 Demod.state = DEMOD_UNSYNCD;
538 break;
539
540 default:
541 Demod.output[Demod.len] = 0xdd;
542 Demod.state = DEMOD_UNSYNCD;
543 break;
544 }
545
546 /*if (Demod.bitCount>=9) {
547 Demod.output[Demod.len] = Demod.shiftReg & 0xff;
548 Demod.len++;
549
550 Demod.parityBits <<= 1;
551 Demod.parityBits ^= ((Demod.shiftReg >> 8) & 0x01);
552
553 Demod.bitCount = 0;
554 Demod.shiftReg = 0;
555 }*/
556 if (Demod.bitCount >= 8) {
557 Demod.shiftReg >>= 1;
558 Demod.output[Demod.len] = (Demod.shiftReg & 0xff);
559 Demod.len++;
560 Demod.bitCount = 0;
561 Demod.shiftReg = 0;
562 }
563
564 if (error) {
565 Demod.output[Demod.len] = 0xBB;
566 Demod.len++;
567 Demod.output[Demod.len] = error & 0xFF;
568 Demod.len++;
569 Demod.output[Demod.len] = 0xBB;
570 Demod.len++;
571 Demod.output[Demod.len] = bit & 0xFF;
572 Demod.len++;
573 Demod.output[Demod.len] = Demod.buffer & 0xFF;
574 Demod.len++;
575 // Look harder ;-)
576 Demod.output[Demod.len] = Demod.buffer2 & 0xFF;
577 Demod.len++;
578 Demod.output[Demod.len] = Demod.syncBit & 0xFF;
579 Demod.len++;
580 Demod.output[Demod.len] = 0xBB;
581 Demod.len++;
582 return true;
583 }
584
585 }
586
587 } // end (state != UNSYNCED)
588
589 return false;
590 }
591
592 //=============================================================================
593 // Finally, a `sniffer' for iClass communication
594 // Both sides of communication!
595 //=============================================================================
596
597 //-----------------------------------------------------------------------------
598 // Record the sequence of commands sent by the reader to the tag, with
599 // triggering so that we start recording at the point that the tag is moved
600 // near the reader.
601 //-----------------------------------------------------------------------------
602 void RAMFUNC SnoopIClass(void) {
603
604 // We won't start recording the frames that we acquire until we trigger;
605 // a good trigger condition to get started is probably when we see a
606 // response from the tag.
607 //int triggered = false; // false to wait first for card
608
609 // The command (reader -> tag) that we're receiving.
610 // The length of a received command will in most cases be no more than 18 bytes.
611 // So 32 should be enough!
612 #define ICLASS_BUFFER_SIZE 32
613 uint8_t readerToTagCmd[ICLASS_BUFFER_SIZE];
614 // The response (tag -> reader) that we're receiving.
615 uint8_t tagToReaderResponse[ICLASS_BUFFER_SIZE];
616
617 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
618
619 // free all BigBuf memory
620 BigBuf_free();
621 // The DMA buffer, used to stream samples from the FPGA
622 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
623
624 set_tracing(true);
625 clear_trace();
626 iso14a_set_trigger(false);
627
628 int lastRxCounter;
629 uint8_t *upTo;
630 int smpl;
631 int maxBehindBy = 0;
632
633 // Count of samples received so far, so that we can include timing
634 // information in the trace buffer.
635 int samples = 0;
636 rsamples = 0;
637
638 // Set up the demodulator for tag -> reader responses.
639 Demod.output = tagToReaderResponse;
640 Demod.len = 0;
641 Demod.state = DEMOD_UNSYNCD;
642
643 // Setup for the DMA.
644 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A);
645 upTo = dmaBuf;
646 lastRxCounter = DMA_BUFFER_SIZE;
647 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
648
649 // And the reader -> tag commands
650 memset(&Uart, 0, sizeof(Uart));
651 Uart.output = readerToTagCmd;
652 Uart.byteCntMax = 32; // was 100 (greg)////////////////////////////////////////////////////////////////////////
653 Uart.state = STATE_UNSYNCD;
654
655 // And put the FPGA in the appropriate mode
656 // Signal field is off with the appropriate LED
657 LED_D_OFF();
658 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_SNIFFER);
659 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
660
661 uint32_t time_0 = GetCountSspClk();
662 uint32_t time_start = 0;
663 uint32_t time_stop = 0;
664
665 int div = 0;
666 //int div2 = 0;
667 int decbyte = 0;
668 int decbyter = 0;
669
670 // And now we loop, receiving samples.
671 for (;;) {
672 LED_A_ON();
673 WDT_HIT();
674 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (DMA_BUFFER_SIZE-1);
675 if (behindBy > maxBehindBy) {
676 maxBehindBy = behindBy;
677 if (behindBy > (9 * DMA_BUFFER_SIZE / 10)) {
678 Dbprintf("blew circular buffer! behindBy=0x%x", behindBy);
679 goto done;
680 }
681 }
682 if (behindBy < 1) continue;
683
684 LED_A_OFF();
685 smpl = upTo[0];
686 upTo++;
687 lastRxCounter -= 1;
688 if (upTo - dmaBuf > DMA_BUFFER_SIZE) {
689 upTo -= DMA_BUFFER_SIZE;
690 lastRxCounter += DMA_BUFFER_SIZE;
691 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
692 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
693 }
694
695 //samples += 4;
696 samples += 1;
697
698 if (smpl & 0xF) {
699 decbyte ^= (1 << (3 - div));
700 }
701
702 // FOR READER SIDE COMMUMICATION...
703
704 decbyter <<= 2;
705 decbyter ^= (smpl & 0x30);
706
707 div++;
708
709 if ((div + 1) % 2 == 0) {
710 smpl = decbyter;
711 if (OutOfNDecoding((smpl & 0xF0) >> 4)) {
712 rsamples = samples - Uart.samples;
713 time_stop = (GetCountSspClk()-time_0) << 4;
714 LED_C_ON();
715
716 //if (!LogTrace(Uart.output, Uart.byteCnt, rsamples, Uart.parityBits,true)) break;
717 //if (!LogTrace(NULL, 0, Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, 0, true)) break;
718 uint8_t parity[MAX_PARITY_SIZE];
719 GetParity(Uart.output, Uart.byteCnt, parity);
720 LogTrace(Uart.output, Uart.byteCnt, time_start, time_stop, parity, true);
721
722 /* And ready to receive another command. */
723 Uart.state = STATE_UNSYNCD;
724 /* And also reset the demod code, which might have been */
725 /* false-triggered by the commands from the reader. */
726 Demod.state = DEMOD_UNSYNCD;
727 LED_B_OFF();
728 Uart.byteCnt = 0;
729 } else {
730 time_start = (GetCountSspClk()-time_0) << 4;
731 }
732 decbyter = 0;
733 }
734
735 if (div > 3) {
736 smpl = decbyte;
737 if (ManchesterDecoding(smpl & 0x0F)) {
738 time_stop = (GetCountSspClk()-time_0) << 4;
739
740 rsamples = samples - Demod.samples;
741 LED_B_ON();
742
743 uint8_t parity[MAX_PARITY_SIZE];
744 GetParity(Demod.output, Demod.len, parity);
745 LogTrace(Demod.output, Demod.len, time_start, time_stop, parity, false);
746
747 // And ready to receive another response.
748 memset(&Demod, 0, sizeof(Demod));
749 Demod.output = tagToReaderResponse;
750 Demod.state = DEMOD_UNSYNCD;
751 LED_C_OFF();
752 } else {
753 time_start = (GetCountSspClk()-time_0) << 4;
754 }
755
756 div = 0;
757 decbyte = 0x00;
758 }
759
760 if (BUTTON_PRESS()) {
761 DbpString("cancelled_a");
762 goto done;
763 }
764 }
765
766 DbpString("COMMAND FINISHED");
767
768 Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
769 Dbprintf("%x %x %x", Uart.byteCntMax, BigBuf_get_traceLen(), (int)Uart.output[0]);
770
771 done:
772 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
773 Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
774 Dbprintf("%x %x %x", Uart.byteCntMax, BigBuf_get_traceLen(), (int)Uart.output[0]);
775 LEDsoff();
776 }
777
778 void rotateCSN(uint8_t* originalCSN, uint8_t* rotatedCSN) {
779 int i;
780 for (i = 0; i < 8; i++) {
781 rotatedCSN[i] = (originalCSN[i] >> 3) | (originalCSN[(i+1)%8] << 5);
782 }
783 }
784
785 //-----------------------------------------------------------------------------
786 // Wait for commands from reader
787 // Stop when button is pressed
788 // Or return true when command is captured
789 //-----------------------------------------------------------------------------
790 static int GetIClassCommandFromReader(uint8_t *received, int *len, int maxLen)
791 {
792 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
793 // only, since we are receiving, not transmitting).
794 // Signal field is off with the appropriate LED
795 LED_D_OFF();
796 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
797
798 // Now run a `software UART' on the stream of incoming samples.
799 Uart.output = received;
800 Uart.byteCntMax = maxLen;
801 Uart.state = STATE_UNSYNCD;
802
803 for (;;) {
804 WDT_HIT();
805
806 if (BUTTON_PRESS()) return false;
807
808 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
809 AT91C_BASE_SSC->SSC_THR = 0x00;
810 }
811 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
812 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
813
814 if (OutOfNDecoding(b & 0x0f)) {
815 *len = Uart.byteCnt;
816 return true;
817 }
818 }
819 }
820 }
821
822 static uint8_t encode4Bits(const uint8_t b) {
823 uint8_t c = b & 0xF;
824 // OTA, the least significant bits first
825 // The columns are
826 // 1 - Bit value to send
827 // 2 - Reversed (big-endian)
828 // 3 - Encoded
829 // 4 - Hex values
830
831 switch(c){
832 // 1 2 3 4
833 case 15: return 0x55; // 1111 -> 1111 -> 01010101 -> 0x55
834 case 14: return 0x95; // 1110 -> 0111 -> 10010101 -> 0x95
835 case 13: return 0x65; // 1101 -> 1011 -> 01100101 -> 0x65
836 case 12: return 0xa5; // 1100 -> 0011 -> 10100101 -> 0xa5
837 case 11: return 0x59; // 1011 -> 1101 -> 01011001 -> 0x59
838 case 10: return 0x99; // 1010 -> 0101 -> 10011001 -> 0x99
839 case 9: return 0x69; // 1001 -> 1001 -> 01101001 -> 0x69
840 case 8: return 0xa9; // 1000 -> 0001 -> 10101001 -> 0xa9
841 case 7: return 0x56; // 0111 -> 1110 -> 01010110 -> 0x56
842 case 6: return 0x96; // 0110 -> 0110 -> 10010110 -> 0x96
843 case 5: return 0x66; // 0101 -> 1010 -> 01100110 -> 0x66
844 case 4: return 0xa6; // 0100 -> 0010 -> 10100110 -> 0xa6
845 case 3: return 0x5a; // 0011 -> 1100 -> 01011010 -> 0x5a
846 case 2: return 0x9a; // 0010 -> 0100 -> 10011010 -> 0x9a
847 case 1: return 0x6a; // 0001 -> 1000 -> 01101010 -> 0x6a
848 default: return 0xaa; // 0000 -> 0000 -> 10101010 -> 0xaa
849
850 }
851 }
852
853 //-----------------------------------------------------------------------------
854 // Prepare tag messages
855 //-----------------------------------------------------------------------------
856 static void CodeIClassTagAnswer(const uint8_t *cmd, int len) {
857
858 /*
859 * SOF comprises 3 parts;
860 * * An unmodulated time of 56.64 us
861 * * 24 pulses of 423.75 kHz (fc/32)
862 * * A logic 1, which starts with an unmodulated time of 18.88us
863 * followed by 8 pulses of 423.75kHz (fc/32)
864 *
865 *
866 * EOF comprises 3 parts:
867 * - A logic 0 (which starts with 8 pulses of fc/32 followed by an unmodulated
868 * time of 18.88us.
869 * - 24 pulses of fc/32
870 * - An unmodulated time of 56.64 us
871 *
872 *
873 * A logic 0 starts with 8 pulses of fc/32
874 * followed by an unmodulated time of 256/fc (~18,88us).
875 *
876 * A logic 0 starts with unmodulated time of 256/fc (~18,88us) followed by
877 * 8 pulses of fc/32 (also 18.88us)
878 *
879 * The mode FPGA_HF_SIMULATOR_MODULATE_424K_8BIT which we use to simulate tag,
880 * works like this.
881 * - A 1-bit input to the FPGA becomes 8 pulses on 423.5kHz (fc/32) (18.88us).
882 * - A 0-bit input to the FPGA becomes an unmodulated time of 18.88us
883 *
884 * In this mode the SOF can be written as 00011101 = 0x1D
885 * The EOF can be written as 10111000 = 0xb8
886 * A logic 1 is 01
887 * A logic 0 is 10
888 *
889 * */
890
891 int i;
892
893 ToSendReset();
894
895 // Send SOF
896 ToSend[++ToSendMax] = 0x1D;
897
898 for (i = 0; i < len; i++) {
899 uint8_t b = cmd[i];
900 ToSend[++ToSendMax] = encode4Bits(b & 0xF); // Least significant half
901 ToSend[++ToSendMax] = encode4Bits((b >>4) & 0xF); // Most significant half
902 }
903
904 // Send EOF
905 ToSend[++ToSendMax] = 0xB8;
906 //lastProxToAirDuration = 8*ToSendMax - 3*8 - 3*8;//Not counting zeroes in the beginning or end
907 // Convert from last byte pos to length
908 ToSendMax++;
909 }
910
911 // Only SOF
912 static void CodeIClassTagSOF() {
913 //So far a dummy implementation, not used
914 //int lastProxToAirDuration =0;
915
916 ToSendReset();
917 // Send SOF
918 ToSend[++ToSendMax] = 0x1D;
919 // lastProxToAirDuration = 8*ToSendMax - 3*8;//Not counting zeroes in the beginning
920
921 // Convert from last byte pos to length
922 ToSendMax++;
923 }
924
925 static void AppendCrc(uint8_t *data, int len) {
926 ComputeCrc14443(CRC_ICLASS, data, len, data+len, data+len+1);
927 }
928
929 static int SendIClassAnswer(uint8_t *resp, int respLen, int delay) {
930 int i = 0, d = 0;//, u = 0, d = 0;
931 uint8_t b = 0;
932
933 //FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K);
934 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_424K_8BIT);
935
936 AT91C_BASE_SSC->SSC_THR = 0x00;
937 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SIMULATOR);
938 while (!BUTTON_PRESS()) {
939 if ((AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)){
940 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
941 }
942 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)){
943 b = 0x00;
944 if (d < delay) {
945 d++;
946 }
947 else {
948 if (i < respLen) {
949 b = resp[i];
950 //Hack
951 //b = 0xAC;
952 }
953 i++;
954 }
955 AT91C_BASE_SSC->SSC_THR = b;
956 }
957
958 // if (i > respLen +4) break;
959 if (i > respLen + 1) break;
960 }
961
962 return 0;
963 }
964
965
966 #define MODE_SIM_CSN 0
967 #define MODE_EXIT_AFTER_MAC 1
968 #define MODE_FULLSIM 2
969
970 /**
971 * @brief Does the actual simulation
972 * @param csn - csn to use
973 * @param breakAfterMacReceived if true, returns after reader MAC has been received.
974 */
975 int doIClassSimulation(int simulationMode, uint8_t *reader_mac_buf) {
976 // free eventually allocated BigBuf memory
977 BigBuf_free_keep_EM();
978
979 State cipher_state;
980 // State cipher_state_reserve;
981 uint8_t *csn = BigBuf_get_EM_addr();
982 uint8_t *emulator = csn;
983 uint8_t sof_data[] = { 0x0F} ;
984 // CSN followed by two CRC bytes
985 uint8_t anticoll_data[10] = { 0 };
986 uint8_t csn_data[10] = { 0 };
987 memcpy(csn_data, csn, sizeof(csn_data));
988 Dbprintf("Simulating CSN %02x%02x%02x%02x%02x%02x%02x%02x", csn[0], csn[1], csn[2], csn[3], csn[4], csn[5], csn[6], csn[7]);
989
990 // Construct anticollision-CSN
991 rotateCSN(csn_data, anticoll_data);
992
993 // Compute CRC on both CSNs
994 ComputeCrc14443(CRC_ICLASS, anticoll_data, 8, &anticoll_data[8], &anticoll_data[9]);
995 ComputeCrc14443(CRC_ICLASS, csn_data, 8, &csn_data[8], &csn_data[9]);
996
997 uint8_t diversified_key[8] = { 0 };
998 // e-Purse
999 uint8_t card_challenge_data[8] = { 0x00 };
1000 if (simulationMode == MODE_FULLSIM) {
1001 //The diversified key should be stored on block 3
1002 //Get the diversified key from emulator memory
1003 memcpy(diversified_key, emulator + (8*3), 8);
1004 //Card challenge, a.k.a e-purse is on block 2
1005 memcpy(card_challenge_data, emulator + (8 * 2), 8);
1006 //Precalculate the cipher state, feeding it the CC
1007 cipher_state = opt_doTagMAC_1(card_challenge_data, diversified_key);
1008 }
1009
1010 int exitLoop = 0;
1011 // Reader 0a
1012 // Tag 0f
1013 // Reader 0c
1014 // Tag anticoll. CSN
1015 // Reader 81 anticoll. CSN
1016 // Tag CSN
1017
1018 uint8_t *modulated_response;
1019 int modulated_response_size = 0;
1020 uint8_t *trace_data = NULL;
1021 int trace_data_size = 0;
1022
1023 // Respond SOF -- takes 1 bytes
1024 uint8_t *resp_sof = BigBuf_malloc(2);
1025 int resp_sof_Len;
1026
1027 // Anticollision CSN (rotated CSN)
1028 // 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
1029 uint8_t *resp_anticoll = BigBuf_malloc(28);
1030 int resp_anticoll_len;
1031
1032 // CSN
1033 // 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
1034 uint8_t *resp_csn = BigBuf_malloc(30);
1035 int resp_csn_len;
1036
1037 // e-Purse
1038 // 18: Takes 2 bytes for SOF/EOF and 8 * 2 = 16 bytes (2 bytes/bit)
1039 uint8_t *resp_cc = BigBuf_malloc(20);
1040 int resp_cc_len;
1041
1042 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1043 int len;
1044
1045 // Prepare card messages
1046 ToSendMax = 0;
1047
1048 // First card answer: SOF
1049 CodeIClassTagSOF();
1050 memcpy(resp_sof, ToSend, ToSendMax);
1051 resp_sof_Len = ToSendMax;
1052
1053 // Anticollision CSN
1054 CodeIClassTagAnswer(anticoll_data, sizeof(anticoll_data));
1055 memcpy(resp_anticoll, ToSend, ToSendMax);
1056 resp_anticoll_len = ToSendMax;
1057
1058 // CSN
1059 CodeIClassTagAnswer(csn_data, sizeof(csn_data));
1060 memcpy(resp_csn, ToSend, ToSendMax);
1061 resp_csn_len = ToSendMax;
1062
1063 // e-Purse
1064 CodeIClassTagAnswer(card_challenge_data, sizeof(card_challenge_data));
1065 memcpy(resp_cc, ToSend, ToSendMax); resp_cc_len = ToSendMax;
1066
1067 //This is used for responding to READ-block commands or other data which is dynamically generated
1068 //First the 'trace'-data, not encoded for FPGA
1069 uint8_t *data_generic_trace = BigBuf_malloc(8 + 2);//8 bytes data + 2byte CRC is max tag answer
1070 //Then storage for the modulated data
1071 //Each bit is doubled when modulated for FPGA, and we also have SOF and EOF (2 bytes)
1072 uint8_t *data_response = BigBuf_malloc( (8+2) * 2 + 2);
1073
1074 // Start from off (no field generated)
1075 //FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1076 //SpinDelay(200);
1077 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1078 SpinDelay(100);
1079 StartCountSspClk();
1080 // We need to listen to the high-frequency, peak-detected path.
1081 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1082 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A);
1083
1084 // To control where we are in the protocol
1085 int cmdsRecvd = 0;
1086 uint32_t time_0 = GetCountSspClk();
1087 uint32_t t2r_time =0;
1088 uint32_t r2t_time =0;
1089
1090 LED_A_ON();
1091 bool buttonPressed = false;
1092 uint8_t response_delay = 1;
1093 while (!exitLoop) {
1094 response_delay = 1;
1095 LED_B_OFF();
1096 //Signal tracer
1097 // Can be used to get a trigger for an oscilloscope..
1098 LED_C_OFF();
1099
1100 if (!GetIClassCommandFromReader(receivedCmd, &len, 100)) {
1101 buttonPressed = true;
1102 break;
1103 }
1104 r2t_time = GetCountSspClk();
1105 //Signal tracer
1106 LED_C_ON();
1107
1108 // Okay, look at the command now.
1109 if (receivedCmd[0] == ICLASS_CMD_ACTALL) {
1110 // Reader in anticollission phase
1111 modulated_response = resp_sof;
1112 modulated_response_size = resp_sof_Len; //order = 1;
1113 trace_data = sof_data;
1114 trace_data_size = sizeof(sof_data);
1115 } else if (receivedCmd[0] == ICLASS_CMD_READ_OR_IDENTIFY && len == 1) {
1116 // Reader asks for anticollission CSN
1117 modulated_response = resp_anticoll;
1118 modulated_response_size = resp_anticoll_len; //order = 2;
1119 trace_data = anticoll_data;
1120 trace_data_size = sizeof(anticoll_data);
1121 //DbpString("Reader requests anticollission CSN:");
1122 } else if (receivedCmd[0] == ICLASS_CMD_SELECT) {
1123 // Reader selects anticollission CSN.
1124 // Tag sends the corresponding real CSN
1125 modulated_response = resp_csn;
1126 modulated_response_size = resp_csn_len; //order = 3;
1127 trace_data = csn_data;
1128 trace_data_size = sizeof(csn_data);
1129 //DbpString("Reader selects anticollission CSN:");
1130 } else if (receivedCmd[0] == ICLASS_CMD_READCHECK_KD) {
1131 // Read e-purse (88 02)
1132 modulated_response = resp_cc;
1133 modulated_response_size = resp_cc_len; //order = 4;
1134 trace_data = card_challenge_data;
1135 trace_data_size = sizeof(card_challenge_data);
1136 LED_B_ON();
1137 } else if (receivedCmd[0] == ICLASS_CMD_CHECK) {
1138 // Reader random and reader MAC!!!
1139 if (simulationMode == MODE_FULLSIM) {
1140 //NR, from reader, is in receivedCmd +1
1141 opt_doTagMAC_2(cipher_state, receivedCmd+1, data_generic_trace, diversified_key);
1142
1143 trace_data = data_generic_trace;
1144 trace_data_size = 4;
1145 CodeIClassTagAnswer(trace_data, trace_data_size);
1146 memcpy(data_response, ToSend, ToSendMax);
1147 modulated_response = data_response;
1148 modulated_response_size = ToSendMax;
1149 response_delay = 0; //We need to hurry here... (but maybe not too much... ??)
1150 //exitLoop = true;
1151 } else { //Not fullsim, we don't respond
1152 // We do not know what to answer, so lets keep quiet
1153 modulated_response = resp_sof;
1154 modulated_response_size = 0;
1155 trace_data = NULL;
1156 trace_data_size = 0;
1157 if (simulationMode == MODE_EXIT_AFTER_MAC) {
1158 // dbprintf:ing ...
1159 Dbprintf("CSN: %02x %02x %02x %02x %02x %02x %02x %02x"
1160 ,csn[0],csn[1],csn[2],csn[3],csn[4],csn[5],csn[6],csn[7]);
1161 Dbprintf("RDR: (len=%02d): %02x %02x %02x %02x %02x %02x %02x %02x %02x",len,
1162 receivedCmd[0], receivedCmd[1], receivedCmd[2],
1163 receivedCmd[3], receivedCmd[4], receivedCmd[5],
1164 receivedCmd[6], receivedCmd[7], receivedCmd[8]);
1165 if (reader_mac_buf != NULL) {
1166 memcpy(reader_mac_buf, receivedCmd+1, 8);
1167 }
1168 exitLoop = true;
1169 }
1170 }
1171
1172 } else if (receivedCmd[0] == ICLASS_CMD_HALT && len == 1) {
1173 // Reader ends the session
1174 modulated_response = resp_sof;
1175 modulated_response_size = 0; //order = 0;
1176 trace_data = NULL;
1177 trace_data_size = 0;
1178 } else if (simulationMode == MODE_FULLSIM && receivedCmd[0] == ICLASS_CMD_READ_OR_IDENTIFY && len == 4) {
1179 //Read block
1180 uint16_t blk = receivedCmd[1];
1181 //Take the data...
1182 memcpy(data_generic_trace, emulator + (blk << 3), 8);
1183 //Add crc
1184 AppendCrc(data_generic_trace, 8);
1185 trace_data = data_generic_trace;
1186 trace_data_size = 10;
1187 CodeIClassTagAnswer(trace_data, trace_data_size);
1188 memcpy(data_response, ToSend, ToSendMax);
1189 modulated_response = data_response;
1190 modulated_response_size = ToSendMax;
1191 } else if (receivedCmd[0] == ICLASS_CMD_UPDATE && simulationMode == MODE_FULLSIM) {
1192 //Probably the reader wants to update the nonce. Let's just ignore that for now.
1193 // OBS! If this is implemented, don't forget to regenerate the cipher_state
1194 //We're expected to respond with the data+crc, exactly what's already in the receivedcmd
1195 //receivedcmd is now UPDATE 1b | ADDRESS 1b| DATA 8b| Signature 4b or CRC 2b|
1196
1197 //Take the data...
1198 memcpy(data_generic_trace, receivedCmd+2, 8);
1199 //Add crc
1200 AppendCrc(data_generic_trace, 8);
1201 trace_data = data_generic_trace;
1202 trace_data_size = 10;
1203 CodeIClassTagAnswer(trace_data, trace_data_size);
1204 memcpy(data_response, ToSend, ToSendMax);
1205 modulated_response = data_response;
1206 modulated_response_size = ToSendMax;
1207 } else if (receivedCmd[0] == ICLASS_CMD_PAGESEL) {
1208 //Pagesel
1209 //Pagesel enables to select a page in the selected chip memory and return its configuration block
1210 //Chips with a single page will not answer to this command
1211 // It appears we're fine ignoring this.
1212 //Otherwise, we should answer 8bytes (block) + 2bytes CRC
1213 } else {
1214 //#db# Unknown command received from reader (len=5): 26 1 0 f6 a 44 44 44 44
1215 // Never seen this command before
1216 Dbprintf("Unknown command received from reader (len=%d): %x %x %x %x %x %x %x %x %x",
1217 len,
1218 receivedCmd[0], receivedCmd[1], receivedCmd[2],
1219 receivedCmd[3], receivedCmd[4], receivedCmd[5],
1220 receivedCmd[6], receivedCmd[7], receivedCmd[8]);
1221 // Do not respond
1222 modulated_response = resp_sof;
1223 modulated_response_size = 0; //order = 0;
1224 trace_data = NULL;
1225 trace_data_size = 0;
1226 }
1227
1228 if (cmdsRecvd > 100) {
1229 //DbpString("100 commands later...");
1230 //break;
1231 } else {
1232 cmdsRecvd++;
1233 }
1234 /**
1235 A legit tag has about 380us delay between reader EOT and tag SOF.
1236 **/
1237 if (modulated_response_size > 0) {
1238 SendIClassAnswer(modulated_response, modulated_response_size, response_delay);
1239 t2r_time = GetCountSspClk();
1240 }
1241
1242 uint8_t parity[MAX_PARITY_SIZE];
1243 GetParity(receivedCmd, len, parity);
1244 LogTrace(receivedCmd, len, (r2t_time-time_0) << 4, (r2t_time-time_0) << 4, parity, true);
1245
1246 if (trace_data != NULL) {
1247 GetParity(trace_data, trace_data_size, parity);
1248 LogTrace(trace_data, trace_data_size, (t2r_time-time_0) << 4, (t2r_time-time_0) << 4, parity, false);
1249 }
1250 if (!get_tracing()) {
1251 DbpString("Trace full");
1252 //break;
1253 }
1254 }
1255
1256 //Dbprintf("%x", cmdsRecvd);
1257 LED_A_OFF();
1258 LED_B_OFF();
1259 LED_C_OFF();
1260
1261 if (buttonPressed)
1262 {
1263 DbpString("Button pressed");
1264 }
1265 return buttonPressed;
1266 }
1267
1268 /**
1269 * @brief SimulateIClass simulates an iClass card.
1270 * @param arg0 type of simulation
1271 * - 0 uses the first 8 bytes in usb data as CSN
1272 * - 2 "dismantling iclass"-attack. This mode iterates through all CSN's specified
1273 * in the usb data. This mode collects MAC from the reader, in order to do an offline
1274 * attack on the keys. For more info, see "dismantling iclass" and proxclone.com.
1275 * - Other : Uses the default CSN (031fec8af7ff12e0)
1276 * @param arg1 - number of CSN's contained in datain (applicable for mode 2 only)
1277 * @param arg2
1278 * @param datain
1279 */
1280 void SimulateIClass(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain) {
1281 uint32_t simType = arg0;
1282 uint32_t numberOfCSNS = arg1;
1283 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1284
1285 // Enable and clear the trace
1286 set_tracing(true);
1287 clear_trace();
1288 //Use the emulator memory for SIM
1289 uint8_t *emulator = BigBuf_get_EM_addr();
1290
1291 if (simType == 0) {
1292 // Use the CSN from commandline
1293 memcpy(emulator, datain, 8);
1294 doIClassSimulation(MODE_SIM_CSN,NULL);
1295 } else if (simType == 1) {
1296 //Default CSN
1297 uint8_t csn_crc[] = { 0x03, 0x1f, 0xec, 0x8a, 0xf7, 0xff, 0x12, 0xe0, 0x00, 0x00 };
1298 // Use the CSN from commandline
1299 memcpy(emulator, csn_crc, 8);
1300 doIClassSimulation(MODE_SIM_CSN,NULL);
1301 } else if (simType == 2) {
1302 uint8_t mac_responses[USB_CMD_DATA_SIZE] = { 0 };
1303 Dbprintf("Going into attack mode, %d CSNS sent", numberOfCSNS);
1304 // In this mode, a number of csns are within datain. We'll simulate each one, one at a time
1305 // in order to collect MAC's from the reader. This can later be used in an offlne-attack
1306 // in order to obtain the keys, as in the "dismantling iclass"-paper.
1307 int i = 0;
1308 for ( ; i < numberOfCSNS && i*8+8 < USB_CMD_DATA_SIZE; i++) {
1309 // The usb data is 512 bytes, fitting 65 8-byte CSNs in there.
1310 memcpy(emulator, datain+(i*8), 8);
1311 if (doIClassSimulation(MODE_EXIT_AFTER_MAC,mac_responses+i*8)) {
1312 cmd_send(CMD_ACK, CMD_SIMULATE_TAG_ICLASS, i, 0, mac_responses, i*8);
1313 return; // Button pressed
1314 }
1315 }
1316 cmd_send(CMD_ACK, CMD_SIMULATE_TAG_ICLASS, i, 0, mac_responses, i*8);
1317 } else if (simType == 3) {
1318 //This is 'full sim' mode, where we use the emulator storage for data.
1319 doIClassSimulation(MODE_FULLSIM, NULL);
1320 } else {
1321 // We may want a mode here where we hardcode the csns to use (from proxclone).
1322 // That will speed things up a little, but not required just yet.
1323 Dbprintf("The mode is not implemented, reserved for future use");
1324 }
1325 Dbprintf("Done...");
1326
1327 }
1328
1329
1330 /// THE READER CODE
1331
1332 //-----------------------------------------------------------------------------
1333 // Transmit the command (to the tag) that was placed in ToSend[].
1334 //-----------------------------------------------------------------------------
1335 static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait) {
1336 int c;
1337 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1338 AT91C_BASE_SSC->SSC_THR = 0x00;
1339 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A);
1340
1341 if (wait) {
1342 if (*wait < 10) *wait = 10;
1343
1344 for (c = 0; c < *wait;) {
1345 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1346 AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing!
1347 c++;
1348 }
1349 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1350 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1351 (void)r;
1352 }
1353 WDT_HIT();
1354 }
1355 }
1356
1357 uint8_t sendbyte;
1358 bool firstpart = true;
1359 c = 0;
1360 for (;;) {
1361 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1362
1363 // DOUBLE THE SAMPLES!
1364 if (firstpart) {
1365 sendbyte = (cmd[c] & 0xf0) | (cmd[c] >> 4);
1366 } else {
1367 sendbyte = (cmd[c] & 0x0f) | (cmd[c] << 4);
1368 c++;
1369 }
1370 if (sendbyte == 0xff) {
1371 sendbyte = 0xfe;
1372 }
1373 AT91C_BASE_SSC->SSC_THR = sendbyte;
1374 firstpart = !firstpart;
1375
1376 if (c >= len) {
1377 break;
1378 }
1379 }
1380 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1381 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1382 (void)r;
1383 }
1384 WDT_HIT();
1385 }
1386 if (samples && wait) *samples = (c + *wait) << 3;
1387 }
1388
1389
1390 //-----------------------------------------------------------------------------
1391 // Prepare iClass reader command to send to FPGA
1392 //-----------------------------------------------------------------------------
1393 void CodeIClassCommand(const uint8_t *cmd, int len) {
1394 int i, j, k;
1395
1396 ToSendReset();
1397
1398 // Start of Communication: 1 out of 4
1399 ToSend[++ToSendMax] = 0xf0;
1400 ToSend[++ToSendMax] = 0x00;
1401 ToSend[++ToSendMax] = 0x0f;
1402 ToSend[++ToSendMax] = 0x00;
1403
1404 // Modulate the bytes
1405 for (i = 0; i < len; i++) {
1406 uint8_t b = cmd[i];
1407 for (j = 0; j < 4; j++) {
1408 for (k = 0; k < 4; k++) {
1409 if (k == (b & 3)) {
1410 ToSend[++ToSendMax] = 0xf0;
1411 } else {
1412 ToSend[++ToSendMax] = 0x00;
1413 }
1414 }
1415 b >>= 2;
1416 }
1417 }
1418
1419 // End of Communication
1420 ToSend[++ToSendMax] = 0x00;
1421 ToSend[++ToSendMax] = 0x00;
1422 ToSend[++ToSendMax] = 0xf0;
1423 ToSend[++ToSendMax] = 0x00;
1424
1425 // Convert from last character reference to length
1426 ToSendMax++;
1427 }
1428
1429 static void ReaderTransmitIClass(uint8_t *frame, int len) {
1430 int wait = 0;
1431 int samples = 0;
1432
1433 // This is tied to other size changes
1434 CodeIClassCommand(frame, len);
1435
1436 // Select the card
1437 TransmitIClassCommand(ToSend, ToSendMax, &samples, &wait);
1438 if (trigger)
1439 LED_A_ON();
1440
1441 // Store reader command in buffer
1442 uint8_t par[MAX_PARITY_SIZE];
1443 GetParity(frame, len, par);
1444 LogTrace(frame, len, rsamples, rsamples, par, true);
1445 }
1446
1447 //-----------------------------------------------------------------------------
1448 // Wait a certain time for tag response
1449 // If a response is captured return true
1450 // If it takes too long return false
1451 //-----------------------------------------------------------------------------
1452 static int GetIClassAnswer(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed) {
1453 //uint8_t *buffer
1454 // buffer needs to be 512 bytes
1455 int c;
1456
1457 // Set FPGA mode to "reader listen mode", no modulation (listen
1458 // only, since we are receiving, not transmitting).
1459 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1460
1461 // Now get the answer from the card
1462 Demod.output = receivedResponse;
1463 Demod.len = 0;
1464 Demod.state = DEMOD_UNSYNCD;
1465
1466 uint8_t b;
1467 if (elapsed) *elapsed = 0;
1468
1469 bool skip = false;
1470
1471 c = 0;
1472 for (;;) {
1473 WDT_HIT();
1474
1475 if (BUTTON_PRESS()) return false;
1476
1477 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1478 AT91C_BASE_SSC->SSC_THR = 0x00; // To make use of exact timing of next command from reader!!
1479 if (elapsed) (*elapsed)++;
1480 }
1481 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1482 if (c < timeout) {
1483 c++;
1484 } else {
1485 return false;
1486 }
1487 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1488 skip = !skip;
1489 if (skip) continue;
1490
1491 if (ManchesterDecoding(b & 0x0f)) {
1492 *samples = c << 3;
1493 return true;
1494 }
1495 }
1496 }
1497 }
1498
1499 static int ReaderReceiveIClass(uint8_t *receivedAnswer) {
1500 int samples = 0;
1501 if (!GetIClassAnswer(receivedAnswer, 160, &samples, 0)) {
1502 return false;
1503 }
1504 rsamples += samples;
1505 uint8_t parity[MAX_PARITY_SIZE];
1506 GetParity(receivedAnswer, Demod.len, parity);
1507 LogTrace(receivedAnswer, Demod.len, rsamples, rsamples, parity, false);
1508 if (samples == 0) return false;
1509 return Demod.len;
1510 }
1511
1512 static void setupIclassReader() {
1513 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1514 // Reset trace buffer
1515 set_tracing(true);
1516 clear_trace();
1517
1518 // Setup SSC
1519 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A);
1520 // Start from off (no field generated)
1521 // Signal field is off with the appropriate LED
1522 LED_D_OFF();
1523 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1524 SpinDelay(200);
1525
1526 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1527
1528 // Now give it time to spin up.
1529 // Signal field is on with the appropriate LED
1530 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1531 SpinDelay(200);
1532 LED_A_ON();
1533
1534 }
1535
1536 static bool sendCmdGetResponseWithRetries(uint8_t* command, size_t cmdsize, uint8_t* resp, uint8_t expected_size, uint8_t retries) {
1537 while (retries-- > 0) {
1538 ReaderTransmitIClass(command, cmdsize);
1539 if (expected_size == ReaderReceiveIClass(resp)) {
1540 return true;
1541 }
1542 }
1543 return false;//Error
1544 }
1545
1546 /**
1547 * @brief Talks to an iclass tag, sends the commands to get CSN and CC.
1548 * @param card_data where the CSN and CC are stored for return
1549 * @return 0 = fail
1550 * 1 = Got CSN
1551 * 2 = Got CSN and CC
1552 */
1553 static uint8_t handshakeIclassTag_ext(uint8_t *card_data, bool use_credit_key) {
1554 static uint8_t act_all[] = { 0x0a };
1555 //static uint8_t identify[] = { 0x0c };
1556 static uint8_t identify[] = { 0x0c, 0x00, 0x73, 0x33 };
1557 static uint8_t select[] = { 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1558 static uint8_t readcheck_cc[]= { 0x88, 0x02 };
1559 if (use_credit_key)
1560 readcheck_cc[0] = 0x18;
1561 else
1562 readcheck_cc[0] = 0x88;
1563
1564 uint8_t resp[ICLASS_BUFFER_SIZE];
1565
1566 uint8_t read_status = 0;
1567
1568 // Send act_all
1569 ReaderTransmitIClass(act_all, 1);
1570 // Card present?
1571 if (!ReaderReceiveIClass(resp)) return read_status;//Fail
1572 //Send Identify
1573 ReaderTransmitIClass(identify, 1);
1574 //We expect a 10-byte response here, 8 byte anticollision-CSN and 2 byte CRC
1575 uint8_t len = ReaderReceiveIClass(resp);
1576 if (len != 10) return read_status;//Fail
1577
1578 //Copy the Anti-collision CSN to our select-packet
1579 memcpy(&select[1], resp, 8);
1580 //Select the card
1581 ReaderTransmitIClass(select, sizeof(select));
1582 //We expect a 10-byte response here, 8 byte CSN and 2 byte CRC
1583 len = ReaderReceiveIClass(resp);
1584 if (len != 10) return read_status;//Fail
1585
1586 //Success - level 1, we got CSN
1587 //Save CSN in response data
1588 memcpy(card_data, resp, 8);
1589
1590 //Flag that we got to at least stage 1, read CSN
1591 read_status = 1;
1592
1593 // Card selected, now read e-purse (cc) (only 8 bytes no CRC)
1594 ReaderTransmitIClass(readcheck_cc, sizeof(readcheck_cc));
1595 if (ReaderReceiveIClass(resp) == 8) {
1596 //Save CC (e-purse) in response data
1597 memcpy(card_data+8, resp, 8);
1598 read_status++;
1599 }
1600
1601 return read_status;
1602 }
1603
1604 static uint8_t handshakeIclassTag(uint8_t *card_data) {
1605 return handshakeIclassTag_ext(card_data, false);
1606 }
1607
1608
1609 // Reader iClass Anticollission
1610 void ReaderIClass(uint8_t arg0) {
1611
1612 uint8_t card_data[6 * 8] = {0};
1613 memset(card_data, 0xFF, sizeof(card_data));
1614 uint8_t last_csn[8] = {0,0,0,0,0,0,0,0};
1615 uint8_t resp[ICLASS_BUFFER_SIZE];
1616 memset(resp, 0xFF, sizeof(resp));
1617 //Read conf block CRC(0x01) => 0xfa 0x22
1618 uint8_t readConf[] = { ICLASS_CMD_READ_OR_IDENTIFY, 0x01, 0xfa, 0x22};
1619 //Read App Issuer Area block CRC(0x05) => 0xde 0x64
1620 uint8_t readAA[] = { ICLASS_CMD_READ_OR_IDENTIFY, 0x05, 0xde, 0x64};
1621
1622 int read_status= 0;
1623 uint8_t result_status = 0;
1624 // flag to read until one tag is found successfully
1625 bool abort_after_read = arg0 & FLAG_ICLASS_READER_ONLY_ONCE;
1626 // flag to only try 5 times to find one tag then return
1627 bool try_once = arg0 & FLAG_ICLASS_READER_ONE_TRY;
1628 // if neither abort_after_read nor try_once then continue reading until button pressed.
1629
1630 bool use_credit_key = arg0 & FLAG_ICLASS_READER_CEDITKEY;
1631 // test flags for what blocks to be sure to read
1632 uint8_t flagReadConfig = arg0 & FLAG_ICLASS_READER_CONF;
1633 uint8_t flagReadCC = arg0 & FLAG_ICLASS_READER_CC;
1634 uint8_t flagReadAA = arg0 & FLAG_ICLASS_READER_AA;
1635
1636 set_tracing(true);
1637 setupIclassReader();
1638
1639 uint16_t tryCnt = 0;
1640 bool userCancelled = BUTTON_PRESS() || usb_poll_validate_length();
1641 while (!userCancelled) {
1642 // if only looking for one card try 2 times if we missed it the first time
1643 if (try_once && tryCnt > 2) {
1644 break;
1645 }
1646 tryCnt++;
1647 if (!get_tracing()) {
1648 DbpString("Trace full");
1649 break;
1650 }
1651 WDT_HIT();
1652
1653 read_status = handshakeIclassTag_ext(card_data, use_credit_key);
1654
1655 if (read_status == 0) continue;
1656 if (read_status == 1) result_status = FLAG_ICLASS_READER_CSN;
1657 if (read_status == 2) result_status = FLAG_ICLASS_READER_CSN | FLAG_ICLASS_READER_CC;
1658
1659 // handshakeIclass returns CSN|CC, but the actual block
1660 // layout is CSN|CONFIG|CC, so here we reorder the data,
1661 // moving CC forward 8 bytes
1662 memcpy(card_data+16, card_data+8, 8);
1663 //Read block 1, config
1664 if (flagReadConfig) {
1665 if (sendCmdGetResponseWithRetries(readConf, sizeof(readConf), resp, 10, 10)) {
1666 result_status |= FLAG_ICLASS_READER_CONF;
1667 memcpy(card_data+8, resp, 8);
1668 } else {
1669 Dbprintf("Failed to dump config block");
1670 }
1671 }
1672
1673 //Read block 5, AA
1674 if (flagReadAA) {
1675 if (sendCmdGetResponseWithRetries(readAA, sizeof(readAA), resp, 10, 10)) {
1676 result_status |= FLAG_ICLASS_READER_AA;
1677 memcpy(card_data + (8*5), resp, 8);
1678 } else {
1679 //Dbprintf("Failed to dump AA block");
1680 }
1681 }
1682
1683 // 0 : CSN
1684 // 1 : Configuration
1685 // 2 : e-purse
1686 // (3,4 write-only, kc and kd)
1687 // 5 Application issuer area
1688 //
1689 //Then we can 'ship' back the 8 * 6 bytes of data,
1690 // with 0xFF:s in block 3 and 4.
1691
1692 LED_B_ON();
1693 //Send back to client, but don't bother if we already sent this -
1694 // only useful if looping in arm (not try_once && not abort_after_read)
1695 if (memcmp(last_csn, card_data, 8) != 0) {
1696 // If caller requires that we get Conf, CC, AA, continue until we got it
1697 if ( (result_status ^ FLAG_ICLASS_READER_CSN ^ flagReadConfig ^ flagReadCC ^ flagReadAA) == 0) {
1698 cmd_send(CMD_ACK, result_status, 0, 0, card_data, sizeof(card_data));
1699 if (abort_after_read) {
1700 LED_A_OFF();
1701 LED_B_OFF();
1702 return;
1703 }
1704 //Save that we already sent this....
1705 memcpy(last_csn, card_data, 8);
1706 }
1707
1708 }
1709 LED_B_OFF();
1710 userCancelled = BUTTON_PRESS() || usb_poll_validate_length();
1711 }
1712 if (userCancelled) {
1713 cmd_send(CMD_ACK, 0xFF, 0, 0, card_data, 0);
1714 } else {
1715 cmd_send(CMD_ACK, 0, 0, 0, card_data, 0);
1716 }
1717 LED_A_OFF();
1718 }
1719
1720 void ReaderIClass_Replay(uint8_t arg0, uint8_t *MAC) {
1721
1722 uint8_t card_data[USB_CMD_DATA_SIZE]={0};
1723 uint16_t block_crc_LUT[255] = {0};
1724
1725 //Generate a lookup table for block crc
1726 for (int block = 0; block < 255; block++){
1727 char bl = block;
1728 block_crc_LUT[block] = iclass_crc16(&bl ,1);
1729 }
1730 //Dbprintf("Lookup table: %02x %02x %02x" ,block_crc_LUT[0],block_crc_LUT[1],block_crc_LUT[2]);
1731
1732 uint8_t check[] = { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1733 uint8_t read[] = { 0x0c, 0x00, 0x00, 0x00 };
1734
1735 uint16_t crc = 0;
1736 uint8_t cardsize = 0;
1737 uint8_t mem = 0;
1738
1739 static struct memory_t {
1740 int k16;
1741 int book;
1742 int k2;
1743 int lockauth;
1744 int keyaccess;
1745 } memory;
1746
1747 uint8_t resp[ICLASS_BUFFER_SIZE];
1748
1749 setupIclassReader();
1750 set_tracing(true);
1751
1752 while (!BUTTON_PRESS()) {
1753
1754 WDT_HIT();
1755
1756 if (!get_tracing()) {
1757 DbpString("Trace full");
1758 break;
1759 }
1760
1761 uint8_t read_status = handshakeIclassTag(card_data);
1762 if (read_status < 2) continue;
1763
1764 //for now replay captured auth (as cc not updated)
1765 memcpy(check+5, MAC, 4);
1766
1767 if (!sendCmdGetResponseWithRetries(check, sizeof(check), resp, 4, 5)) {
1768 Dbprintf("Error: Authentication Fail!");
1769 continue;
1770 }
1771
1772 //first get configuration block (block 1)
1773 crc = block_crc_LUT[1];
1774 read[1] = 1;
1775 read[2] = crc >> 8;
1776 read[3] = crc & 0xff;
1777
1778 if (!sendCmdGetResponseWithRetries(read, sizeof(read),resp, 10, 10)) {
1779 Dbprintf("Dump config (block 1) failed");
1780 continue;
1781 }
1782
1783 mem = resp[5];
1784 memory.k16 = (mem & 0x80);
1785 memory.book = (mem & 0x20);
1786 memory.k2 = (mem & 0x8);
1787 memory.lockauth = (mem & 0x2);
1788 memory.keyaccess = (mem & 0x1);
1789
1790 cardsize = memory.k16 ? 255 : 32;
1791 WDT_HIT();
1792 //Set card_data to all zeroes, we'll fill it with data
1793 memset(card_data, 0x0, USB_CMD_DATA_SIZE);
1794 uint8_t failedRead = 0;
1795 uint32_t stored_data_length = 0;
1796 //then loop around remaining blocks
1797 for (int block = 0; block < cardsize; block++) {
1798 read[1] = block;
1799 crc = block_crc_LUT[block];
1800 read[2] = crc >> 8;
1801 read[3] = crc & 0xff;
1802
1803 if (sendCmdGetResponseWithRetries(read, sizeof(read), resp, 10, 10)) {
1804 Dbprintf(" %02x: %02x %02x %02x %02x %02x %02x %02x %02x",
1805 block, resp[0], resp[1], resp[2],
1806 resp[3], resp[4], resp[5],
1807 resp[6], resp[7]);
1808
1809 //Fill up the buffer
1810 memcpy(card_data+stored_data_length, resp, 8);
1811 stored_data_length += 8;
1812 if (stored_data_length +8 > USB_CMD_DATA_SIZE) {
1813 //Time to send this off and start afresh
1814 cmd_send(CMD_ACK,
1815 stored_data_length,//data length
1816 failedRead,//Failed blocks?
1817 0,//Not used ATM
1818 card_data, stored_data_length);
1819 //reset
1820 stored_data_length = 0;
1821 failedRead = 0;
1822 }
1823
1824 } else {
1825 failedRead = 1;
1826 stored_data_length += 8;//Otherwise, data becomes misaligned
1827 Dbprintf("Failed to dump block %d", block);
1828 }
1829 }
1830
1831 //Send off any remaining data
1832 if (stored_data_length > 0) {
1833 cmd_send(CMD_ACK,
1834 stored_data_length,//data length
1835 failedRead,//Failed blocks?
1836 0,//Not used ATM
1837 card_data,
1838 stored_data_length);
1839 }
1840 //If we got here, let's break
1841 break;
1842 }
1843 //Signal end of transmission
1844 cmd_send(CMD_ACK,
1845 0,//data length
1846 0,//Failed blocks?
1847 0,//Not used ATM
1848 card_data,
1849 0);
1850
1851 LED_A_OFF();
1852 }
1853
1854 void iClass_ReadCheck(uint8_t blockNo, uint8_t keyType) {
1855 uint8_t readcheck[] = { keyType, blockNo };
1856 uint8_t resp[] = {0,0,0,0,0,0,0,0};
1857 size_t isOK = 0;
1858 isOK = sendCmdGetResponseWithRetries(readcheck, sizeof(readcheck), resp, sizeof(resp), 6);
1859 cmd_send(CMD_ACK,isOK, 0, 0, 0, 0);
1860 }
1861
1862 void iClass_Authentication(uint8_t *MAC) {
1863 uint8_t check[] = { ICLASS_CMD_CHECK, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1864 uint8_t resp[ICLASS_BUFFER_SIZE];
1865 memcpy(check+5, MAC, 4);
1866 bool isOK;
1867 isOK = sendCmdGetResponseWithRetries(check, sizeof(check), resp, 4, 6);
1868 cmd_send(CMD_ACK,isOK, 0, 0, 0, 0);
1869 }
1870
1871 bool iClass_ReadBlock(uint8_t blockNo, uint8_t *readdata) {
1872 uint8_t readcmd[] = {ICLASS_CMD_READ_OR_IDENTIFY, blockNo, 0x00, 0x00}; //0x88, 0x00 // can i use 0C?
1873 char bl = blockNo;
1874 uint16_t rdCrc = iclass_crc16(&bl, 1);
1875 readcmd[2] = rdCrc >> 8;
1876 readcmd[3] = rdCrc & 0xff;
1877 uint8_t resp[] = {0,0,0,0,0,0,0,0,0,0};
1878 bool isOK = false;
1879
1880 //readcmd[1] = blockNo;
1881 isOK = sendCmdGetResponseWithRetries(readcmd, sizeof(readcmd), resp, 10, 10);
1882 memcpy(readdata, resp, sizeof(resp));
1883
1884 return isOK;
1885 }
1886
1887 void iClass_ReadBlk(uint8_t blockno) {
1888 uint8_t readblockdata[] = {0,0,0,0,0,0,0,0,0,0};
1889 bool isOK = false;
1890 isOK = iClass_ReadBlock(blockno, readblockdata);
1891 cmd_send(CMD_ACK, isOK, 0, 0, readblockdata, 8);
1892 }
1893
1894 void iClass_Dump(uint8_t blockno, uint8_t numblks) {
1895 uint8_t readblockdata[] = {0,0,0,0,0,0,0,0,0,0};
1896 bool isOK = false;
1897 uint8_t blkCnt = 0;
1898
1899 BigBuf_free();
1900 uint8_t *dataout = BigBuf_malloc(255*8);
1901 if (dataout == NULL) {
1902 Dbprintf("out of memory");
1903 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1904 LED_D_OFF();
1905 cmd_send(CMD_ACK, 0, 1, 0, 0, 0);
1906 LED_A_OFF();
1907 return;
1908 }
1909 memset(dataout, 0xFF, 255*8);
1910
1911 for ( ; blkCnt < numblks; blkCnt++) {
1912 isOK = iClass_ReadBlock(blockno+blkCnt, readblockdata);
1913 if (!isOK || (readblockdata[0] == 0xBB || readblockdata[7] == 0xBB || readblockdata[2] == 0xBB)) { //try again
1914 isOK = iClass_ReadBlock(blockno+blkCnt, readblockdata);
1915 if (!isOK) {
1916 Dbprintf("Block %02X failed to read", blkCnt+blockno);
1917 break;
1918 }
1919 }
1920 memcpy(dataout + (blkCnt*8), readblockdata, 8);
1921 }
1922 //return pointer to dump memory in arg3
1923 cmd_send(CMD_ACK, isOK, blkCnt, BigBuf_max_traceLen(), 0, 0);
1924 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1925 LEDsoff();
1926 BigBuf_free();
1927 }
1928
1929 static bool iClass_WriteBlock_ext(uint8_t blockNo, uint8_t *data) {
1930 uint8_t write[] = { ICLASS_CMD_UPDATE, blockNo, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1931 //uint8_t readblockdata[10];
1932 //write[1] = blockNo;
1933 memcpy(write+2, data, 12); // data + mac
1934 char *wrCmd = (char *)(write+1);
1935 uint16_t wrCrc = iclass_crc16(wrCmd, 13);
1936 write[14] = wrCrc >> 8;
1937 write[15] = wrCrc & 0xff;
1938 uint8_t resp[] = {0,0,0,0,0,0,0,0,0,0};
1939 bool isOK = false;
1940
1941 isOK = sendCmdGetResponseWithRetries(write, sizeof(write), resp, sizeof(resp), 10);
1942 if (isOK) { //if reader responded correctly
1943 //Dbprintf("WriteResp: %02X%02X%02X%02X%02X%02X%02X%02X%02X%02X",resp[0],resp[1],resp[2],resp[3],resp[4],resp[5],resp[6],resp[7],resp[8],resp[9]);
1944 if (memcmp(write+2, resp, 8)) { //if response is not equal to write values
1945 if (blockNo != 3 && blockNo != 4) { //if not programming key areas (note key blocks don't get programmed with actual key data it is xor data)
1946 //error try again
1947 isOK = sendCmdGetResponseWithRetries(write, sizeof(write), resp, sizeof(resp), 10);
1948 }
1949 }
1950 }
1951 return isOK;
1952 }
1953
1954 void iClass_WriteBlock(uint8_t blockNo, uint8_t *data) {
1955 bool isOK = iClass_WriteBlock_ext(blockNo, data);
1956 if (isOK){
1957 Dbprintf("Write block [%02x] successful", blockNo);
1958 } else {
1959 Dbprintf("Write block [%02x] failed", blockNo);
1960 }
1961 cmd_send(CMD_ACK, isOK, 0, 0, 0, 0);
1962 }
1963
1964 void iClass_Clone(uint8_t startblock, uint8_t endblock, uint8_t *data) {
1965 int i;
1966 int written = 0;
1967 int total_block = (endblock - startblock) + 1;
1968 for (i = 0; i < total_block; i++) {
1969 // block number
1970 if (iClass_WriteBlock_ext(i+startblock, data + (i*12))){
1971 Dbprintf("Write block [%02x] successful", i + startblock);
1972 written++;
1973 } else {
1974 if (iClass_WriteBlock_ext(i+startblock, data + (i*12))){
1975 Dbprintf("Write block [%02x] successful", i + startblock);
1976 written++;
1977 } else {
1978 Dbprintf("Write block [%02x] failed", i + startblock);
1979 }
1980 }
1981 }
1982 if (written == total_block)
1983 Dbprintf("Clone complete");
1984 else
1985 Dbprintf("Clone incomplete");
1986
1987 cmd_send(CMD_ACK, 1, 0, 0, 0, 0);
1988 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1989 LEDsoff();
1990 }
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