cvs.zerfleddert.de Git - proxmark3-svn/blob - armsrc/lfops.c

   1 //-----------------------------------------------------------------------------
   2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
   3 // at your option, any later version. See the LICENSE.txt file for the text of
   4 // the license.
   5 //-----------------------------------------------------------------------------
   6 // Miscellaneous routines for low frequency tag operations.
   7 // Tags supported here so far are Texas Instruments (TI), HID
   8 // Also routines for raw mode reading/simulating of LF waveform
   9 //-----------------------------------------------------------------------------
  10
  11 #include "proxmark3.h"
  12 #include "apps.h"
  13 #include "util.h"
  14 #include "hitag2.h"
  15 #include "crc16.h"
  16 #include "string.h"
  17 #include "lfdemod.h"
  18
  19
  20 /**
  21 * Does the sample acquisition. If threshold is specified, the actual sampling
  22 * is not commenced until the threshold has been reached.
  23 * @param trigger_threshold - the threshold
  24 * @param silent - is true, now outputs are made. If false, dbprints the status
  25 */
  26 void DoAcquisition125k_internal(int trigger_threshold,bool silent)
  27 {
  28     uint8_t *dest = (uint8_t *)BigBuf;
  29     int n = sizeof(BigBuf);
  30     int i;
  31
  32     memset(dest, 0, n);
  33     i = 0;
  34     for(;;) {
  35         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
  36             AT91C_BASE_SSC->SSC_THR = 0x43;
  37             LED_D_ON();
  38         }
  39         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
  40             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
  41             LED_D_OFF();
  42             if (trigger_threshold != -1 && dest[i] < trigger_threshold)
  43                 continue;
  44             else
  45                 trigger_threshold = -1;
  46             if (++i >= n) break;
  47         }
  48     }
  49     if(!silent)
  50     {
  51         Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
  52                  dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
  53
  54     }
  55 }
  56 /**
  57 * Perform sample aquisition.
  58 */
  59 void DoAcquisition125k(int trigger_threshold)
  60 {
  61     DoAcquisition125k_internal(trigger_threshold, false);
  62 }
  63
  64 /**
  65 * Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
  66 * if not already loaded, sets divisor and starts up the antenna.
  67 * @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
  68 *                                  0 or 95 ==> 125 KHz
  69 *
  70 **/
  71 void LFSetupFPGAForADC(int divisor, bool lf_field)
  72 {
  73     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
  74     if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
  75         FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
  76     else if (divisor == 0)
  77         FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
  78     else
  79         FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
  80
  81     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
  82
  83     // Connect the A/D to the peak-detected low-frequency path.
  84     SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
  85     // Give it a bit of time for the resonant antenna to settle.
  86     SpinDelay(50);
  87     // Now set up the SSC to get the ADC samples that are now streaming at us.
  88     FpgaSetupSsc();
  89 }
  90 /**
  91 * Initializes the FPGA, and acquires the samples.
  92 **/
  93 void AcquireRawAdcSamples125k(int divisor)
  94 {
  95     LFSetupFPGAForADC(divisor, true);
  96     // Now call the acquisition routine
  97     DoAcquisition125k_internal(-1,false);
  98 }
  99 /**
 100 * Initializes the FPGA for snoop-mode, and acquires the samples.
 101 **/
 102
 103 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
 104 {
 105     LFSetupFPGAForADC(divisor, false);
 106     DoAcquisition125k(trigger_threshold);
 107 }
 108
 109 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
 110 {
 111
 112     /* Make sure the tag is reset */
 113     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 114     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 115     SpinDelay(2500);
 116
 117
 118     int divisor_used = 95; // 125 KHz
 119     // see if 'h' was specified
 120
 121     if (command[strlen((char *) command) - 1] == 'h')
 122         divisor_used = 88; // 134.8 KHz
 123
 124
 125     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
 126     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 127     // Give it a bit of time for the resonant antenna to settle.
 128     SpinDelay(50);
 129
 130     // And a little more time for the tag to fully power up
 131     SpinDelay(2000);
 132
 133     // Now set up the SSC to get the ADC samples that are now streaming at us.
 134     FpgaSetupSsc();
 135
 136     // now modulate the reader field
 137     while(*command != '\0' && *command != ' ') {
 138         FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 139         LED_D_OFF();
 140         SpinDelayUs(delay_off);
 141         FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
 142
 143         FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 144         LED_D_ON();
 145         if(*(command++) == '0')
 146             SpinDelayUs(period_0);
 147         else
 148             SpinDelayUs(period_1);
 149     }
 150     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 151     LED_D_OFF();
 152     SpinDelayUs(delay_off);
 153     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
 154
 155     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 156
 157     // now do the read
 158     DoAcquisition125k(-1);
 159 }
 160
 161 /* blank r/w tag data stream
 162 ...0000000000000000 01111111
 163 1010101010101010101010101010101010101010101010101010101010101010
 164 0011010010100001
 165 01111111
 166 101010101010101[0]000...
 167
 168 [5555fe852c5555555555555555fe0000]
 169 */
 170 void ReadTItag(void)
 171 {
 172     // some hardcoded initial params
 173     // when we read a TI tag we sample the zerocross line at 2Mhz
 174     // TI tags modulate a 1 as 16 cycles of 123.2Khz
 175     // TI tags modulate a 0 as 16 cycles of 134.2Khz
 176 #define FSAMPLE 2000000
 177 #define FREQLO 123200
 178 #define FREQHI 134200
 179
 180     signed char *dest = (signed char *)BigBuf;
 181     int n = sizeof(BigBuf);
 182
 183     // 128 bit shift register [shift3:shift2:shift1:shift0]
 184     uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
 185
 186     int i, cycles=0, samples=0;
 187     // how many sample points fit in 16 cycles of each frequency
 188     uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
 189     // when to tell if we're close enough to one freq or another
 190     uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
 191
 192     // TI tags charge at 134.2Khz
 193     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 194     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
 195
 196     // Place FPGA in passthrough mode, in this mode the CROSS_LO line
 197     // connects to SSP_DIN and the SSP_DOUT logic level controls
 198     // whether we're modulating the antenna (high)
 199     // or listening to the antenna (low)
 200     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
 201
 202     // get TI tag data into the buffer
 203     AcquireTiType();
 204
 205     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 206
 207     for (i=0; i<n-1; i++) {
 208         // count cycles by looking for lo to hi zero crossings
 209         if ( (dest[i]<0) && (dest[i+1]>0) ) {
 210             cycles++;
 211             // after 16 cycles, measure the frequency
 212             if (cycles>15) {
 213                 cycles=0;
 214                 samples=i-samples; // number of samples in these 16 cycles
 215
 216                 // TI bits are coming to us lsb first so shift them
 217                 // right through our 128 bit right shift register
 218                 shift0 = (shift0>>1) | (shift1 << 31);
 219                 shift1 = (shift1>>1) | (shift2 << 31);
 220                 shift2 = (shift2>>1) | (shift3 << 31);
 221                 shift3 >>= 1;
 222
 223                 // check if the cycles fall close to the number
 224                 // expected for either the low or high frequency
 225                 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
 226                     // low frequency represents a 1
 227                     shift3 |= (1<<31);
 228                 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
 229                     // high frequency represents a 0
 230                 } else {
 231                     // probably detected a gay waveform or noise
 232                     // use this as gaydar or discard shift register and start again
 233                     shift3 = shift2 = shift1 = shift0 = 0;
 234                 }
 235                 samples = i;
 236
 237                 // for each bit we receive, test if we've detected a valid tag
 238
 239                 // if we see 17 zeroes followed by 6 ones, we might have a tag
 240                 // remember the bits are backwards
 241                 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
 242                     // if start and end bytes match, we have a tag so break out of the loop
 243                     if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
 244                         cycles = 0xF0B; //use this as a flag (ugly but whatever)
 245                         break;
 246                     }
 247                 }
 248             }
 249         }
 250     }
 251
 252     // if flag is set we have a tag
 253     if (cycles!=0xF0B) {
 254         DbpString("Info: No valid tag detected.");
 255     } else {
 256         // put 64 bit data into shift1 and shift0
 257         shift0 = (shift0>>24) | (shift1 << 8);
 258         shift1 = (shift1>>24) | (shift2 << 8);
 259
 260         // align 16 bit crc into lower half of shift2
 261         shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
 262
 263         // if r/w tag, check ident match
 264         if ( shift3&(1<<15) ) {
 265             DbpString("Info: TI tag is rewriteable");
 266             // only 15 bits compare, last bit of ident is not valid
 267             if ( ((shift3>>16)^shift0)&0x7fff ) {
 268                 DbpString("Error: Ident mismatch!");
 269             } else {
 270                 DbpString("Info: TI tag ident is valid");
 271             }
 272         } else {
 273             DbpString("Info: TI tag is readonly");
 274         }
 275
 276         // WARNING the order of the bytes in which we calc crc below needs checking
 277         // i'm 99% sure the crc algorithm is correct, but it may need to eat the
 278         // bytes in reverse or something
 279         // calculate CRC
 280         uint32_t crc=0;
 281
 282         crc = update_crc16(crc, (shift0)&0xff);
 283         crc = update_crc16(crc, (shift0>>8)&0xff);
 284         crc = update_crc16(crc, (shift0>>16)&0xff);
 285         crc = update_crc16(crc, (shift0>>24)&0xff);
 286         crc = update_crc16(crc, (shift1)&0xff);
 287         crc = update_crc16(crc, (shift1>>8)&0xff);
 288         crc = update_crc16(crc, (shift1>>16)&0xff);
 289         crc = update_crc16(crc, (shift1>>24)&0xff);
 290
 291         Dbprintf("Info: Tag data: %x%08x, crc=%x",
 292                  (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
 293         if (crc != (shift2&0xffff)) {
 294             Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
 295         } else {
 296             DbpString("Info: CRC is good");
 297         }
 298     }
 299 }
 300
 301 void WriteTIbyte(uint8_t b)
 302 {
 303     int i = 0;
 304
 305     // modulate 8 bits out to the antenna
 306     for (i=0; i<8; i++)
 307     {
 308         if (b&(1<<i)) {
 309             // stop modulating antenna
 310             LOW(GPIO_SSC_DOUT);
 311             SpinDelayUs(1000);
 312             // modulate antenna
 313             HIGH(GPIO_SSC_DOUT);
 314             SpinDelayUs(1000);
 315         } else {
 316             // stop modulating antenna
 317             LOW(GPIO_SSC_DOUT);
 318             SpinDelayUs(300);
 319             // modulate antenna
 320             HIGH(GPIO_SSC_DOUT);
 321             SpinDelayUs(1700);
 322         }
 323     }
 324 }
 325
 326 void AcquireTiType(void)
 327 {
 328     int i, j, n;
 329     // tag transmission is <20ms, sampling at 2M gives us 40K samples max
 330     // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
 331 #define TIBUFLEN 1250
 332
 333     // clear buffer
 334     memset(BigBuf,0,sizeof(BigBuf));
 335
 336     // Set up the synchronous serial port
 337     AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
 338     AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
 339
 340     // steal this pin from the SSP and use it to control the modulation
 341     AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
 342     AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
 343
 344     AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
 345     AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
 346
 347     // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
 348     // 48/2 = 24 MHz clock must be divided by 12
 349     AT91C_BASE_SSC->SSC_CMR = 12;
 350
 351     AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
 352     AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
 353     AT91C_BASE_SSC->SSC_TCMR = 0;
 354     AT91C_BASE_SSC->SSC_TFMR = 0;
 355
 356     LED_D_ON();
 357
 358     // modulate antenna
 359     HIGH(GPIO_SSC_DOUT);
 360
 361     // Charge TI tag for 50ms.
 362     SpinDelay(50);
 363
 364     // stop modulating antenna and listen
 365     LOW(GPIO_SSC_DOUT);
 366
 367     LED_D_OFF();
 368
 369     i = 0;
 370     for(;;) {
 371         if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
 372             BigBuf[i] = AT91C_BASE_SSC->SSC_RHR;        // store 32 bit values in buffer
 373             i++; if(i >= TIBUFLEN) break;
 374         }
 375         WDT_HIT();
 376     }
 377
 378     // return stolen pin to SSP
 379     AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
 380     AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
 381
 382     char *dest = (char *)BigBuf;
 383     n = TIBUFLEN*32;
 384     // unpack buffer
 385     for (i=TIBUFLEN-1; i>=0; i--) {
 386         for (j=0; j<32; j++) {
 387             if(BigBuf[i] & (1 << j)) {
 388                 dest[--n] = 1;
 389             } else {
 390                 dest[--n] = -1;
 391             }
 392         }
 393     }
 394 }
 395
 396 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
 397 // if crc provided, it will be written with the data verbatim (even if bogus)
 398 // if not provided a valid crc will be computed from the data and written.
 399 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 400 {
 401     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 402     if(crc == 0) {
 403         crc = update_crc16(crc, (idlo)&0xff);
 404         crc = update_crc16(crc, (idlo>>8)&0xff);
 405         crc = update_crc16(crc, (idlo>>16)&0xff);
 406         crc = update_crc16(crc, (idlo>>24)&0xff);
 407         crc = update_crc16(crc, (idhi)&0xff);
 408         crc = update_crc16(crc, (idhi>>8)&0xff);
 409         crc = update_crc16(crc, (idhi>>16)&0xff);
 410         crc = update_crc16(crc, (idhi>>24)&0xff);
 411     }
 412     Dbprintf("Writing to tag: %x%08x, crc=%x",
 413              (unsigned int) idhi, (unsigned int) idlo, crc);
 414
 415     // TI tags charge at 134.2Khz
 416     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
 417     // Place FPGA in passthrough mode, in this mode the CROSS_LO line
 418     // connects to SSP_DIN and the SSP_DOUT logic level controls
 419     // whether we're modulating the antenna (high)
 420     // or listening to the antenna (low)
 421     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
 422     LED_A_ON();
 423
 424     // steal this pin from the SSP and use it to control the modulation
 425     AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
 426     AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
 427
 428     // writing algorithm:
 429     // a high bit consists of a field off for 1ms and field on for 1ms
 430     // a low bit consists of a field off for 0.3ms and field on for 1.7ms
 431     // initiate a charge time of 50ms (field on) then immediately start writing bits
 432     // start by writing 0xBB (keyword) and 0xEB (password)
 433     // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
 434     // finally end with 0x0300 (write frame)
 435     // all data is sent lsb firts
 436     // finish with 15ms programming time
 437
 438     // modulate antenna
 439     HIGH(GPIO_SSC_DOUT);
 440     SpinDelay(50);      // charge time
 441
 442     WriteTIbyte(0xbb); // keyword
 443     WriteTIbyte(0xeb); // password
 444     WriteTIbyte( (idlo    )&0xff );
 445     WriteTIbyte( (idlo>>8 )&0xff );
 446     WriteTIbyte( (idlo>>16)&0xff );
 447     WriteTIbyte( (idlo>>24)&0xff );
 448     WriteTIbyte( (idhi    )&0xff );
 449     WriteTIbyte( (idhi>>8 )&0xff );
 450     WriteTIbyte( (idhi>>16)&0xff );
 451     WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
 452     WriteTIbyte( (crc     )&0xff ); // crc lo
 453     WriteTIbyte( (crc>>8  )&0xff ); // crc hi
 454     WriteTIbyte(0x00); // write frame lo
 455     WriteTIbyte(0x03); // write frame hi
 456     HIGH(GPIO_SSC_DOUT);
 457     SpinDelay(50);      // programming time
 458
 459     LED_A_OFF();
 460
 461     // get TI tag data into the buffer
 462     AcquireTiType();
 463
 464     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 465     DbpString("Now use tiread to check");
 466 }
 467
 468 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 469 {
 470     int i;
 471     uint8_t *tab = (uint8_t *)BigBuf;
 472
 473     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 474     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
 475
 476     AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
 477
 478     AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
 479     AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
 480
 481 #define SHORT_COIL()    LOW(GPIO_SSC_DOUT)
 482 #define OPEN_COIL()             HIGH(GPIO_SSC_DOUT)
 483
 484     i = 0;
 485     for(;;) {
 486         while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
 487             if(BUTTON_PRESS()) {
 488                 DbpString("Stopped");
 489                 return;
 490             }
 491             WDT_HIT();
 492         }
 493
 494         if (ledcontrol)
 495             LED_D_ON();
 496
 497         if(tab[i])
 498             OPEN_COIL();
 499         else
 500             SHORT_COIL();
 501
 502         if (ledcontrol)
 503             LED_D_OFF();
 504
 505         while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
 506             if(BUTTON_PRESS()) {
 507                 DbpString("Stopped");
 508                 return;
 509             }
 510             WDT_HIT();
 511         }
 512
 513         i++;
 514         if(i == period) {
 515             i = 0;
 516             if (gap) {
 517                 SHORT_COIL();
 518                 SpinDelayUs(gap);
 519             }
 520         }
 521     }
 522 }
 523
 524 #define DEBUG_FRAME_CONTENTS 1
 525 void SimulateTagLowFrequencyBidir(int divisor, int t0)
 526 {
 527 }
 528
 529 // compose fc/8 fc/10 waveform
 530 static void fc(int c, int *n) {
 531     uint8_t *dest = (uint8_t *)BigBuf;
 532     int idx;
 533
 534     // for when we want an fc8 pattern every 4 logical bits
 535     if(c==0) {
 536         dest[((*n)++)]=1;
 537         dest[((*n)++)]=1;
 538         dest[((*n)++)]=0;
 539         dest[((*n)++)]=0;
 540         dest[((*n)++)]=0;
 541         dest[((*n)++)]=0;
 542         dest[((*n)++)]=0;
 543         dest[((*n)++)]=0;
 544     }
 545     //  an fc/8  encoded bit is a bit pattern of  11000000  x6 = 48 samples
 546     if(c==8) {
 547         for (idx=0; idx<6; idx++) {
 548             dest[((*n)++)]=1;
 549             dest[((*n)++)]=1;
 550             dest[((*n)++)]=0;
 551             dest[((*n)++)]=0;
 552             dest[((*n)++)]=0;
 553             dest[((*n)++)]=0;
 554             dest[((*n)++)]=0;
 555             dest[((*n)++)]=0;
 556         }
 557     }
 558
 559     //  an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
 560     if(c==10) {
 561         for (idx=0; idx<5; idx++) {
 562             dest[((*n)++)]=1;
 563             dest[((*n)++)]=1;
 564             dest[((*n)++)]=1;
 565             dest[((*n)++)]=0;
 566             dest[((*n)++)]=0;
 567             dest[((*n)++)]=0;
 568             dest[((*n)++)]=0;
 569             dest[((*n)++)]=0;
 570             dest[((*n)++)]=0;
 571             dest[((*n)++)]=0;
 572         }
 573     }
 574 }
 575
 576 // prepare a waveform pattern in the buffer based on the ID given then
 577 // simulate a HID tag until the button is pressed
 578 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 579 {
 580     int n=0, i=0;
 581     /*
 582      HID tag bitstream format
 583      The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
 584      A 1 bit is represented as 6 fc8 and 5 fc10 patterns
 585      A 0 bit is represented as 5 fc10 and 6 fc8 patterns
 586      A fc8 is inserted before every 4 bits
 587      A special start of frame pattern is used consisting a0b0 where a and b are neither 0
 588      nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
 589     */
 590
 591     if (hi>0xFFF) {
 592         DbpString("Tags can only have 44 bits.");
 593         return;
 594     }
 595     fc(0,&n);
 596     // special start of frame marker containing invalid bit sequences
 597     fc(8,  &n); fc(8,  &n);     // invalid
 598     fc(8,  &n); fc(10, &n); // logical 0
 599     fc(10, &n); fc(10, &n); // invalid
 600     fc(8,  &n); fc(10, &n); // logical 0
 601
 602     WDT_HIT();
 603     // manchester encode bits 43 to 32
 604     for (i=11; i>=0; i--) {
 605         if ((i%4)==3) fc(0,&n);
 606         if ((hi>>i)&1) {
 607             fc(10, &n); fc(8,  &n);             // low-high transition
 608         } else {
 609             fc(8,  &n); fc(10, &n);             // high-low transition
 610         }
 611     }
 612
 613     WDT_HIT();
 614     // manchester encode bits 31 to 0
 615     for (i=31; i>=0; i--) {
 616         if ((i%4)==3) fc(0,&n);
 617         if ((lo>>i)&1) {
 618             fc(10, &n); fc(8,  &n);             // low-high transition
 619         } else {
 620             fc(8,  &n); fc(10, &n);             // high-low transition
 621         }
 622     }
 623
 624     if (ledcontrol)
 625         LED_A_ON();
 626
 627     SimulateTagLowFrequency(n, 0, ledcontrol);
 628
 629     if (ledcontrol)
 630         LED_A_OFF();
 631 }
 632
 633 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
 634 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 635 {
 636     uint8_t *dest = (uint8_t *)BigBuf;
 637
 638     size_t size=0; //, found=0;
 639     uint32_t hi2=0, hi=0, lo=0;
 640
 641     // Configure to go in 125Khz listen mode
 642     LFSetupFPGAForADC(95, true);
 643
 644     while(!BUTTON_PRESS()) {
 645
 646         WDT_HIT();
 647         if (ledcontrol) LED_A_ON();
 648
 649         DoAcquisition125k_internal(-1,true);
 650         // FSK demodulator
 651                 size = HIDdemodFSK(dest, sizeof(BigBuf), &hi2, &hi, &lo);
 652
 653         WDT_HIT();
 654
 655                 if (size>0 && lo>0){
 656             // final loop, go over previously decoded manchester data and decode into usable tag ID
 657             // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
 658             if (hi2 != 0){ //extra large HID tags
 659                 Dbprintf("TAG ID: %x%08x%08x (%d)",
 660                          (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
 661             }else {  //standard HID tags <38 bits
 662                 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
 663                 uint8_t bitlen = 0;
 664                 uint32_t fc = 0;
 665                 uint32_t cardnum = 0;
 666                 if (((hi>>5)&1)==1){//if bit 38 is set then < 37 bit format is used
 667                     uint32_t lo2=0;
 668                     lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
 669                     uint8_t idx3 = 1;
 670                     while(lo2>1){ //find last bit set to 1 (format len bit)
 671                         lo2=lo2>>1;
 672                         idx3++;
 673                     }
 674                     bitlen =idx3+19;
 675                     fc =0;
 676                     cardnum=0;
 677                     if(bitlen==26){
 678                         cardnum = (lo>>1)&0xFFFF;
 679                         fc = (lo>>17)&0xFF;
 680                     }
 681                     if(bitlen==37){
 682                         cardnum = (lo>>1)&0x7FFFF;
 683                         fc = ((hi&0xF)<<12)|(lo>>20);
 684                     }
 685                     if(bitlen==34){
 686                         cardnum = (lo>>1)&0xFFFF;
 687                         fc= ((hi&1)<<15)|(lo>>17);
 688                     }
 689                     if(bitlen==35){
 690                         cardnum = (lo>>1)&0xFFFFF;
 691                         fc = ((hi&1)<<11)|(lo>>21);
 692                     }
 693                 }
 694                 else { //if bit 38 is not set then 37 bit format is used
 695                     bitlen= 37;
 696                     fc =0;
 697                     cardnum=0;
 698                     if(bitlen==37){
 699                         cardnum = (lo>>1)&0x7FFFF;
 700                         fc = ((hi&0xF)<<12)|(lo>>20);
 701                     }
 702                 }
 703                 //Dbprintf("TAG ID: %x%08x (%d)",
 704                 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
 705                 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
 706                          (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
 707                          (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
 708             }
 709             if (findone){
 710                 if (ledcontrol) LED_A_OFF();
 711                 return;
 712             }
 713             // reset
 714             hi2 = hi = lo = 0;
 715         }
 716         WDT_HIT();
 717     }
 718     DbpString("Stopped");
 719     if (ledcontrol) LED_A_OFF();
 720 }
 721
 722 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
 723 {
 724     uint8_t *dest = (uint8_t *)BigBuf;
 725
 726         size_t size=0;
 727     int clk=0, invert=0, errCnt=0;
 728     uint64_t lo=0;
 729     // Configure to go in 125Khz listen mode
 730     LFSetupFPGAForADC(95, true);
 731
 732     while(!BUTTON_PRESS()) {
 733
 734         WDT_HIT();
 735         if (ledcontrol) LED_A_ON();
 736
 737         DoAcquisition125k_internal(-1,true);
 738         size  = sizeof(BigBuf);
 739         //Dbprintf("DEBUG: Buffer got");
 740                 //askdemod and manchester decode
 741                 errCnt = askmandemod(dest, &size, &clk, &invert);
 742         //Dbprintf("DEBUG: ASK Got");
 743         WDT_HIT();
 744
 745         if (errCnt>=0){
 746                         lo = Em410xDecode(dest,size);
 747             //Dbprintf("DEBUG: EM GOT");
 748             if (lo>0){
 749                                 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
 750                                     (uint32_t)(lo>>32),
 751                                     (uint32_t)lo,
 752                                     (uint32_t)(lo&0xFFFF),
 753                                     (uint32_t)((lo>>16LL) & 0xFF),
 754                                     (uint32_t)(lo & 0xFFFFFF));
 755             }
 756             if (findone){
 757                 if (ledcontrol) LED_A_OFF();
 758                 return;
 759             }
 760         } else{
 761             //Dbprintf("DEBUG: No Tag");
 762         }
 763         WDT_HIT();
 764         lo = 0;
 765         clk=0;
 766         invert=0;
 767         errCnt=0;
 768         size=0;
 769     }
 770     DbpString("Stopped");
 771     if (ledcontrol) LED_A_OFF();
 772 }
 773
 774 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 775 {
 776     uint8_t *dest = (uint8_t *)BigBuf;
 777     int idx=0;
 778     uint32_t code=0, code2=0;
 779     uint8_t version=0;
 780     uint8_t facilitycode=0;
 781     uint16_t number=0;
 782     // Configure to go in 125Khz listen mode
 783     LFSetupFPGAForADC(95, true);
 784
 785     while(!BUTTON_PRESS()) {
 786         WDT_HIT();
 787         if (ledcontrol) LED_A_ON();
 788         DoAcquisition125k_internal(-1,true);
 789         //fskdemod and get start index
 790         WDT_HIT();
 791         idx = IOdemodFSK(dest,sizeof(BigBuf));
 792         if (idx>0){
 793             //valid tag found
 794
 795             //Index map
 796             //0           10          20          30          40          50          60
 797             //|           |           |           |           |           |           |
 798             //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
 799             //-----------------------------------------------------------------------------
 800             //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
 801             //
 802             //XSF(version)facility:codeone+codetwo
 803             //Handle the data
 804             if(findone){ //only print binary if we are doing one
 805                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx],   dest[idx+1],   dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
 806                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
 807                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
 808                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
 809                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
 810                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
 811                 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
 812             }
 813             code = bytebits_to_byte(dest+idx,32);
 814             code2 = bytebits_to_byte(dest+idx+32,32);
 815             version = bytebits_to_byte(dest+idx+27,8); //14,4
 816             facilitycode = bytebits_to_byte(dest+idx+18,8) ;
 817             number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
 818
 819             Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
 820             // if we're only looking for one tag
 821             if (findone){
 822                 if (ledcontrol) LED_A_OFF();
 823                 //LED_A_OFF();
 824                 return;
 825             }
 826             code=code2=0;
 827             version=facilitycode=0;
 828             number=0;
 829             idx=0;
 830         }
 831         WDT_HIT();
 832     }
 833     DbpString("Stopped");
 834     if (ledcontrol) LED_A_OFF();
 835 }
 836
 837 /*------------------------------
 838  * T5555/T5557/T5567 routines
 839  *------------------------------
 840  */
 841
 842 /* T55x7 configuration register definitions */
 843 #define T55x7_POR_DELAY                 0x00000001
 844 #define T55x7_ST_TERMINATOR             0x00000008
 845 #define T55x7_PWD                       0x00000010
 846 #define T55x7_MAXBLOCK_SHIFT            5
 847 #define T55x7_AOR                       0x00000200
 848 #define T55x7_PSKCF_RF_2                0
 849 #define T55x7_PSKCF_RF_4                0x00000400
 850 #define T55x7_PSKCF_RF_8                0x00000800
 851 #define T55x7_MODULATION_DIRECT         0
 852 #define T55x7_MODULATION_PSK1           0x00001000
 853 #define T55x7_MODULATION_PSK2           0x00002000
 854 #define T55x7_MODULATION_PSK3           0x00003000
 855 #define T55x7_MODULATION_FSK1           0x00004000
 856 #define T55x7_MODULATION_FSK2           0x00005000
 857 #define T55x7_MODULATION_FSK1a          0x00006000
 858 #define T55x7_MODULATION_FSK2a          0x00007000
 859 #define T55x7_MODULATION_MANCHESTER     0x00008000
 860 #define T55x7_MODULATION_BIPHASE        0x00010000
 861 #define T55x7_BITRATE_RF_8              0
 862 #define T55x7_BITRATE_RF_16             0x00040000
 863 #define T55x7_BITRATE_RF_32             0x00080000
 864 #define T55x7_BITRATE_RF_40             0x000C0000
 865 #define T55x7_BITRATE_RF_50             0x00100000
 866 #define T55x7_BITRATE_RF_64             0x00140000
 867 #define T55x7_BITRATE_RF_100            0x00180000
 868 #define T55x7_BITRATE_RF_128            0x001C0000
 869
 870 /* T5555 (Q5) configuration register definitions */
 871 #define T5555_ST_TERMINATOR             0x00000001
 872 #define T5555_MAXBLOCK_SHIFT            0x00000001
 873 #define T5555_MODULATION_MANCHESTER     0
 874 #define T5555_MODULATION_PSK1           0x00000010
 875 #define T5555_MODULATION_PSK2           0x00000020
 876 #define T5555_MODULATION_PSK3           0x00000030
 877 #define T5555_MODULATION_FSK1           0x00000040
 878 #define T5555_MODULATION_FSK2           0x00000050
 879 #define T5555_MODULATION_BIPHASE        0x00000060
 880 #define T5555_MODULATION_DIRECT         0x00000070
 881 #define T5555_INVERT_OUTPUT             0x00000080
 882 #define T5555_PSK_RF_2                  0
 883 #define T5555_PSK_RF_4                  0x00000100
 884 #define T5555_PSK_RF_8                  0x00000200
 885 #define T5555_USE_PWD                   0x00000400
 886 #define T5555_USE_AOR                   0x00000800
 887 #define T5555_BITRATE_SHIFT             12
 888 #define T5555_FAST_WRITE                0x00004000
 889 #define T5555_PAGE_SELECT               0x00008000
 890
 891 /*
 892  * Relevant times in microsecond
 893  * To compensate antenna falling times shorten the write times
 894  * and enlarge the gap ones.
 895  */
 896 #define START_GAP 250
 897 #define WRITE_GAP 160
 898 #define WRITE_0   144 // 192
 899 #define WRITE_1   400 // 432 for T55x7; 448 for E5550
 900
 901 // Write one bit to card
 902 void T55xxWriteBit(int bit)
 903 {
 904     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 905     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 906     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 907     if (bit == 0)
 908         SpinDelayUs(WRITE_0);
 909     else
 910         SpinDelayUs(WRITE_1);
 911     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 912     SpinDelayUs(WRITE_GAP);
 913 }
 914
 915 // Write one card block in page 0, no lock
 916 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 917 {
 918     //unsigned int i;  //enio adjustment 12/10/14
 919     uint32_t i;
 920
 921     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 922     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 923     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 924
 925     // Give it a bit of time for the resonant antenna to settle.
 926     // And for the tag to fully power up
 927     SpinDelay(150);
 928
 929     // Now start writting
 930     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 931     SpinDelayUs(START_GAP);
 932
 933     // Opcode
 934     T55xxWriteBit(1);
 935     T55xxWriteBit(0); //Page 0
 936     if (PwdMode == 1){
 937         // Pwd
 938         for (i = 0x80000000; i != 0; i >>= 1)
 939             T55xxWriteBit(Pwd & i);
 940     }
 941     // Lock bit
 942     T55xxWriteBit(0);
 943
 944     // Data
 945     for (i = 0x80000000; i != 0; i >>= 1)
 946         T55xxWriteBit(Data & i);
 947
 948     // Block
 949     for (i = 0x04; i != 0; i >>= 1)
 950         T55xxWriteBit(Block & i);
 951
 952     // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
 953     // so wait a little more)
 954     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 955     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 956     SpinDelay(20);
 957     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 958 }
 959
 960 // Read one card block in page 0
 961 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 962 {
 963     uint8_t *dest = (uint8_t *)BigBuf;
 964     //int m=0, i=0; //enio adjustment 12/10/14
 965     uint32_t m=0, i=0;
 966     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 967     m = sizeof(BigBuf);
 968     // Clear destination buffer before sending the command
 969     memset(dest, 128, m);
 970     // Connect the A/D to the peak-detected low-frequency path.
 971     SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
 972     // Now set up the SSC to get the ADC samples that are now streaming at us.
 973     FpgaSetupSsc();
 974
 975     LED_D_ON();
 976     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 977     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 978
 979     // Give it a bit of time for the resonant antenna to settle.
 980     // And for the tag to fully power up
 981     SpinDelay(150);
 982
 983     // Now start writting
 984     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 985     SpinDelayUs(START_GAP);
 986
 987     // Opcode
 988     T55xxWriteBit(1);
 989     T55xxWriteBit(0); //Page 0
 990     if (PwdMode == 1){
 991         // Pwd
 992         for (i = 0x80000000; i != 0; i >>= 1)
 993             T55xxWriteBit(Pwd & i);
 994     }
 995     // Lock bit
 996     T55xxWriteBit(0);
 997     // Block
 998     for (i = 0x04; i != 0; i >>= 1)
 999         T55xxWriteBit(Block & i);
1000
1001     // Turn field on to read the response
1002     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1003     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1004
1005     // Now do the acquisition
1006     i = 0;
1007     for(;;) {
1008         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1009             AT91C_BASE_SSC->SSC_THR = 0x43;
1010         }
1011         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1012             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1013             // we don't care about actual value, only if it's more or less than a
1014             // threshold essentially we capture zero crossings for later analysis
1015             //                  if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1016             i++;
1017             if (i >= m) break;
1018         }
1019     }
1020
1021     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1022     LED_D_OFF();
1023     DbpString("DONE!");
1024 }
1025
1026 // Read card traceability data (page 1)
1027 void T55xxReadTrace(void){
1028     uint8_t *dest = (uint8_t *)BigBuf;
1029     int m=0, i=0;
1030
1031     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1032     m = sizeof(BigBuf);
1033     // Clear destination buffer before sending the command
1034     memset(dest, 128, m);
1035     // Connect the A/D to the peak-detected low-frequency path.
1036     SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1037     // Now set up the SSC to get the ADC samples that are now streaming at us.
1038     FpgaSetupSsc();
1039
1040     LED_D_ON();
1041     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1042     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1043
1044     // Give it a bit of time for the resonant antenna to settle.
1045     // And for the tag to fully power up
1046     SpinDelay(150);
1047
1048     // Now start writting
1049     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1050     SpinDelayUs(START_GAP);
1051
1052     // Opcode
1053     T55xxWriteBit(1);
1054     T55xxWriteBit(1); //Page 1
1055
1056     // Turn field on to read the response
1057     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1058     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1059
1060     // Now do the acquisition
1061     i = 0;
1062     for(;;) {
1063         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1064             AT91C_BASE_SSC->SSC_THR = 0x43;
1065         }
1066         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1067             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1068             i++;
1069             if (i >= m) break;
1070         }
1071     }
1072
1073     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1074     LED_D_OFF();
1075     DbpString("DONE!");
1076 }
1077
1078 /*-------------- Cloning routines -----------*/
1079 // Copy HID id to card and setup block 0 config
1080 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1081 {
1082     int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1083     int last_block = 0;
1084
1085     if (longFMT){
1086         // Ensure no more than 84 bits supplied
1087         if (hi2>0xFFFFF) {
1088             DbpString("Tags can only have 84 bits.");
1089             return;
1090         }
1091         // Build the 6 data blocks for supplied 84bit ID
1092         last_block = 6;
1093         data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1094         for (int i=0;i<4;i++) {
1095             if (hi2 & (1<<(19-i)))
1096                 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1097             else
1098                 data1 |= (1<<((3-i)*2)); // 0 -> 01
1099         }
1100
1101         data2 = 0;
1102         for (int i=0;i<16;i++) {
1103             if (hi2 & (1<<(15-i)))
1104                 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1105             else
1106                 data2 |= (1<<((15-i)*2)); // 0 -> 01
1107         }
1108
1109         data3 = 0;
1110         for (int i=0;i<16;i++) {
1111             if (hi & (1<<(31-i)))
1112                 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1113             else
1114                 data3 |= (1<<((15-i)*2)); // 0 -> 01
1115         }
1116
1117         data4 = 0;
1118         for (int i=0;i<16;i++) {
1119             if (hi & (1<<(15-i)))
1120                 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1121             else
1122                 data4 |= (1<<((15-i)*2)); // 0 -> 01
1123         }
1124
1125         data5 = 0;
1126         for (int i=0;i<16;i++) {
1127             if (lo & (1<<(31-i)))
1128                 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1129             else
1130                 data5 |= (1<<((15-i)*2)); // 0 -> 01
1131         }
1132
1133         data6 = 0;
1134         for (int i=0;i<16;i++) {
1135             if (lo & (1<<(15-i)))
1136                 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1137             else
1138                 data6 |= (1<<((15-i)*2)); // 0 -> 01
1139         }
1140     }
1141     else {
1142         // Ensure no more than 44 bits supplied
1143         if (hi>0xFFF) {
1144             DbpString("Tags can only have 44 bits.");
1145             return;
1146         }
1147
1148         // Build the 3 data blocks for supplied 44bit ID
1149         last_block = 3;
1150
1151         data1 = 0x1D000000; // load preamble
1152
1153         for (int i=0;i<12;i++) {
1154             if (hi & (1<<(11-i)))
1155                 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1156             else
1157                 data1 |= (1<<((11-i)*2)); // 0 -> 01
1158         }
1159
1160         data2 = 0;
1161         for (int i=0;i<16;i++) {
1162             if (lo & (1<<(31-i)))
1163                 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1164             else
1165                 data2 |= (1<<((15-i)*2)); // 0 -> 01
1166         }
1167
1168         data3 = 0;
1169         for (int i=0;i<16;i++) {
1170             if (lo & (1<<(15-i)))
1171                 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1172             else
1173                 data3 |= (1<<((15-i)*2)); // 0 -> 01
1174         }
1175     }
1176
1177     LED_D_ON();
1178     // Program the data blocks for supplied ID
1179     // and the block 0 for HID format
1180     T55xxWriteBlock(data1,1,0,0);
1181     T55xxWriteBlock(data2,2,0,0);
1182     T55xxWriteBlock(data3,3,0,0);
1183
1184     if (longFMT) { // if long format there are 6 blocks
1185         T55xxWriteBlock(data4,4,0,0);
1186         T55xxWriteBlock(data5,5,0,0);
1187         T55xxWriteBlock(data6,6,0,0);
1188     }
1189
1190     // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1191     T55xxWriteBlock(T55x7_BITRATE_RF_50    |
1192                     T55x7_MODULATION_FSK2a |
1193                     last_block << T55x7_MAXBLOCK_SHIFT,
1194                     0,0,0);
1195
1196     LED_D_OFF();
1197
1198     DbpString("DONE!");
1199 }
1200
1201 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1202 {
1203     int data1=0, data2=0; //up to six blocks for long format
1204
1205     data1 = hi;  // load preamble
1206     data2 = lo;
1207
1208     LED_D_ON();
1209     // Program the data blocks for supplied ID
1210     // and the block 0 for HID format
1211     T55xxWriteBlock(data1,1,0,0);
1212     T55xxWriteBlock(data2,2,0,0);
1213
1214     //Config Block
1215     T55xxWriteBlock(0x00147040,0,0,0);
1216     LED_D_OFF();
1217
1218     DbpString("DONE!");
1219 }
1220
1221 // Define 9bit header for EM410x tags
1222 #define EM410X_HEADER           0x1FF
1223 #define EM410X_ID_LENGTH        40
1224
1225 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1226 {
1227     int i, id_bit;
1228     uint64_t id = EM410X_HEADER;
1229     uint64_t rev_id = 0;        // reversed ID
1230     int c_parity[4];    // column parity
1231     int r_parity = 0;   // row parity
1232     uint32_t clock = 0;
1233
1234     // Reverse ID bits given as parameter (for simpler operations)
1235     for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1236         if (i < 32) {
1237             rev_id = (rev_id << 1) | (id_lo & 1);
1238             id_lo >>= 1;
1239         } else {
1240             rev_id = (rev_id << 1) | (id_hi & 1);
1241             id_hi >>= 1;
1242         }
1243     }
1244
1245     for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1246         id_bit = rev_id & 1;
1247
1248         if (i % 4 == 0) {
1249             // Don't write row parity bit at start of parsing
1250             if (i)
1251                 id = (id << 1) | r_parity;
1252             // Start counting parity for new row
1253             r_parity = id_bit;
1254         } else {
1255             // Count row parity
1256             r_parity ^= id_bit;
1257         }
1258
1259         // First elements in column?
1260         if (i < 4)
1261             // Fill out first elements
1262             c_parity[i] = id_bit;
1263         else
1264             // Count column parity
1265             c_parity[i % 4] ^= id_bit;
1266
1267         // Insert ID bit
1268         id = (id << 1) | id_bit;
1269         rev_id >>= 1;
1270     }
1271
1272     // Insert parity bit of last row
1273     id = (id << 1) | r_parity;
1274
1275     // Fill out column parity at the end of tag
1276     for (i = 0; i < 4; ++i)
1277         id = (id << 1) | c_parity[i];
1278
1279     // Add stop bit
1280     id <<= 1;
1281
1282     Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1283     LED_D_ON();
1284
1285     // Write EM410x ID
1286     T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1287     T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1288
1289     // Config for EM410x (RF/64, Manchester, Maxblock=2)
1290     if (card) {
1291         // Clock rate is stored in bits 8-15 of the card value
1292         clock = (card & 0xFF00) >> 8;
1293         Dbprintf("Clock rate: %d", clock);
1294         switch (clock)
1295         {
1296         case 32:
1297             clock = T55x7_BITRATE_RF_32;
1298             break;
1299         case 16:
1300             clock = T55x7_BITRATE_RF_16;
1301             break;
1302         case 0:
1303             // A value of 0 is assumed to be 64 for backwards-compatibility
1304             // Fall through...
1305         case 64:
1306             clock = T55x7_BITRATE_RF_64;
1307             break;
1308         default:
1309             Dbprintf("Invalid clock rate: %d", clock);
1310             return;
1311         }
1312
1313         // Writing configuration for T55x7 tag
1314         T55xxWriteBlock(clock       |
1315                         T55x7_MODULATION_MANCHESTER |
1316                         2 << T55x7_MAXBLOCK_SHIFT,
1317                         0, 0, 0);
1318     }
1319     else
1320         // Writing configuration for T5555(Q5) tag
1321         T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1322                         T5555_MODULATION_MANCHESTER   |
1323                         2 << T5555_MAXBLOCK_SHIFT,
1324                         0, 0, 0);
1325
1326     LED_D_OFF();
1327     Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1328              (uint32_t)(id >> 32), (uint32_t)id);
1329 }
1330
1331 // Clone Indala 64-bit tag by UID to T55x7
1332 void CopyIndala64toT55x7(int hi, int lo)
1333 {
1334     //Program the 2 data blocks for supplied 64bit UID
1335     // and the block 0 for Indala64 format
1336     T55xxWriteBlock(hi,1,0,0);
1337     T55xxWriteBlock(lo,2,0,0);
1338     //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1339     T55xxWriteBlock(T55x7_BITRATE_RF_32    |
1340                     T55x7_MODULATION_PSK1 |
1341                     2 << T55x7_MAXBLOCK_SHIFT,
1342                     0, 0, 0);
1343     //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1344     //  T5567WriteBlock(0x603E1042,0);
1345
1346     DbpString("DONE!");
1347 }
1348
1349 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1350 {
1351     //Program the 7 data blocks for supplied 224bit UID
1352     // and the block 0 for Indala224 format
1353     T55xxWriteBlock(uid1,1,0,0);
1354     T55xxWriteBlock(uid2,2,0,0);
1355     T55xxWriteBlock(uid3,3,0,0);
1356     T55xxWriteBlock(uid4,4,0,0);
1357     T55xxWriteBlock(uid5,5,0,0);
1358     T55xxWriteBlock(uid6,6,0,0);
1359     T55xxWriteBlock(uid7,7,0,0);
1360     //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1361     T55xxWriteBlock(T55x7_BITRATE_RF_32    |
1362                     T55x7_MODULATION_PSK1 |
1363                     7 << T55x7_MAXBLOCK_SHIFT,
1364                     0,0,0);
1365     //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1366     //  T5567WriteBlock(0x603E10E2,0);
1367
1368     DbpString("DONE!");
1369 }
1370
1371
1372 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1373 #define max(x,y) ( x<y ? y:x)
1374
1375 int DemodPCF7931(uint8_t **outBlocks) {
1376     uint8_t BitStream[256];
1377     uint8_t Blocks[8][16];
1378     uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1379     int GraphTraceLen = sizeof(BigBuf);
1380     int i, j, lastval, bitidx, half_switch;
1381     int clock = 64;
1382     int tolerance = clock / 8;
1383     int pmc, block_done;
1384     int lc, warnings = 0;
1385     int num_blocks = 0;
1386     int lmin=128, lmax=128;
1387     uint8_t dir;
1388
1389     AcquireRawAdcSamples125k(0);
1390
1391     lmin = 64;
1392     lmax = 192;
1393
1394     i = 2;
1395
1396     /* Find first local max/min */
1397     if(GraphBuffer[1] > GraphBuffer[0]) {
1398         while(i < GraphTraceLen) {
1399             if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1400                 break;
1401             i++;
1402         }
1403         dir = 0;
1404     }
1405     else {
1406         while(i < GraphTraceLen) {
1407             if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1408                 break;
1409             i++;
1410         }
1411         dir = 1;
1412     }
1413
1414     lastval = i++;
1415     half_switch = 0;
1416     pmc = 0;
1417     block_done = 0;
1418
1419     for (bitidx = 0; i < GraphTraceLen; i++)
1420     {
1421         if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1422         {
1423             lc = i - lastval;
1424             lastval = i;
1425
1426             // Switch depending on lc length:
1427             // Tolerance is 1/8 of clock rate (arbitrary)
1428             if (abs(lc-clock/4) < tolerance) {
1429                 // 16T0
1430                 if((i - pmc) == lc) { /* 16T0 was previous one */
1431                     /* It's a PMC ! */
1432                     i += (128+127+16+32+33+16)-1;
1433                     lastval = i;
1434                     pmc = 0;
1435                     block_done = 1;
1436                 }
1437                 else {
1438                     pmc = i;
1439                 }
1440             } else if (abs(lc-clock/2) < tolerance) {
1441                 // 32TO
1442                 if((i - pmc) == lc) { /* 16T0 was previous one */
1443                     /* It's a PMC ! */
1444                     i += (128+127+16+32+33)-1;
1445                     lastval = i;
1446                     pmc = 0;
1447                     block_done = 1;
1448                 }
1449                 else if(half_switch == 1) {
1450                     BitStream[bitidx++] = 0;
1451                     half_switch = 0;
1452                 }
1453                 else
1454                     half_switch++;
1455             } else if (abs(lc-clock) < tolerance) {
1456                 // 64TO
1457                 BitStream[bitidx++] = 1;
1458             } else {
1459                 // Error
1460                 warnings++;
1461                 if (warnings > 10)
1462                 {
1463                     Dbprintf("Error: too many detection errors, aborting.");
1464                     return 0;
1465                 }
1466             }
1467
1468             if(block_done == 1) {
1469                 if(bitidx == 128) {
1470                     for(j=0; j<16; j++) {
1471                         Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1472                                 64*BitStream[j*8+6]+
1473                                 32*BitStream[j*8+5]+
1474                                 16*BitStream[j*8+4]+
1475                                 8*BitStream[j*8+3]+
1476                                 4*BitStream[j*8+2]+
1477                                 2*BitStream[j*8+1]+
1478                                 BitStream[j*8];
1479                     }
1480                     num_blocks++;
1481                 }
1482                 bitidx = 0;
1483                 block_done = 0;
1484                 half_switch = 0;
1485             }
1486             if(i < GraphTraceLen)
1487             {
1488                 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1489                 else dir = 1;
1490             }
1491         }
1492         if(bitidx==255)
1493             bitidx=0;
1494         warnings = 0;
1495         if(num_blocks == 4) break;
1496     }
1497     memcpy(outBlocks, Blocks, 16*num_blocks);
1498     return num_blocks;
1499 }
1500
1501 int IsBlock0PCF7931(uint8_t *Block) {
1502     // Assume RFU means 0 :)
1503     if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1504         return 1;
1505     if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1506         return 1;
1507     return 0;
1508 }
1509
1510 int IsBlock1PCF7931(uint8_t *Block) {
1511     // Assume RFU means 0 :)
1512     if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1513         if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1514             return 1;
1515
1516     return 0;
1517 }
1518
1519 #define ALLOC 16
1520
1521 void ReadPCF7931() {
1522     uint8_t Blocks[8][17];
1523     uint8_t tmpBlocks[4][16];
1524     int i, j, ind, ind2, n;
1525     int num_blocks = 0;
1526     int max_blocks = 8;
1527     int ident = 0;
1528     int error = 0;
1529     int tries = 0;
1530
1531     memset(Blocks, 0, 8*17*sizeof(uint8_t));
1532
1533     do {
1534         memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1535         n = DemodPCF7931((uint8_t**)tmpBlocks);
1536         if(!n)
1537             error++;
1538         if(error==10 && num_blocks == 0) {
1539             Dbprintf("Error, no tag or bad tag");
1540             return;
1541         }
1542         else if (tries==20 || error==10) {
1543             Dbprintf("Error reading the tag");
1544             Dbprintf("Here is the partial content");
1545             goto end;
1546         }
1547
1548         for(i=0; i<n; i++)
1549             Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1550                      tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1551                     tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1552         if(!ident) {
1553             for(i=0; i<n; i++) {
1554                 if(IsBlock0PCF7931(tmpBlocks[i])) {
1555                     // Found block 0 ?
1556                     if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1557                         // Found block 1!
1558                         // \o/
1559                         ident = 1;
1560                         memcpy(Blocks[0], tmpBlocks[i], 16);
1561                         Blocks[0][ALLOC] = 1;
1562                         memcpy(Blocks[1], tmpBlocks[i+1], 16);
1563                         Blocks[1][ALLOC] = 1;
1564                         max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1565                         // Debug print
1566                         Dbprintf("(dbg) Max blocks: %d", max_blocks);
1567                         num_blocks = 2;
1568                         // Handle following blocks
1569                         for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1570                             if(j==n) j=0;
1571                             if(j==i) break;
1572                             memcpy(Blocks[ind2], tmpBlocks[j], 16);
1573                             Blocks[ind2][ALLOC] = 1;
1574                         }
1575                         break;
1576                     }
1577                 }
1578             }
1579         }
1580         else {
1581             for(i=0; i<n; i++) { // Look for identical block in known blocks
1582                 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1583                     for(j=0; j<max_blocks; j++) {
1584                         if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1585                             // Found an identical block
1586                             for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1587                                 if(ind2 < 0)
1588                                     ind2 = max_blocks;
1589                                 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1590                                     // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1591                                     memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1592                                     Blocks[ind2][ALLOC] = 1;
1593                                     num_blocks++;
1594                                     if(num_blocks == max_blocks) goto end;
1595                                 }
1596                             }
1597                             for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1598                                 if(ind2 > max_blocks)
1599                                     ind2 = 0;
1600                                 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1601                                     // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1602                                     memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1603                                     Blocks[ind2][ALLOC] = 1;
1604                                     num_blocks++;
1605                                     if(num_blocks == max_blocks) goto end;
1606                                 }
1607                             }
1608                         }
1609                     }
1610                 }
1611             }
1612         }
1613         tries++;
1614         if (BUTTON_PRESS()) return;
1615     } while (num_blocks != max_blocks);
1616 end:
1617     Dbprintf("-----------------------------------------");
1618     Dbprintf("Memory content:");
1619     Dbprintf("-----------------------------------------");
1620     for(i=0; i<max_blocks; i++) {
1621         if(Blocks[i][ALLOC]==1)
1622             Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1623                      Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1624                     Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1625         else
1626             Dbprintf("<missing block %d>", i);
1627     }
1628     Dbprintf("-----------------------------------------");
1629
1630     return ;
1631 }
1632
1633
1634 //-----------------------------------
1635 // EM4469 / EM4305 routines
1636 //-----------------------------------
1637 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1638 #define FWD_CMD_WRITE 0xA
1639 #define FWD_CMD_READ 0x9
1640 #define FWD_CMD_DISABLE 0x5
1641
1642
1643 uint8_t forwardLink_data[64]; //array of forwarded bits
1644 uint8_t * forward_ptr; //ptr for forward message preparation
1645 uint8_t fwd_bit_sz; //forwardlink bit counter
1646 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1647
1648 //====================================================================
1649 // prepares command bits
1650 // see EM4469 spec
1651 //====================================================================
1652 //--------------------------------------------------------------------
1653 uint8_t Prepare_Cmd( uint8_t cmd ) {
1654     //--------------------------------------------------------------------
1655
1656     *forward_ptr++ = 0; //start bit
1657     *forward_ptr++ = 0; //second pause for 4050 code
1658
1659     *forward_ptr++ = cmd;
1660     cmd >>= 1;
1661     *forward_ptr++ = cmd;
1662     cmd >>= 1;
1663     *forward_ptr++ = cmd;
1664     cmd >>= 1;
1665     *forward_ptr++ = cmd;
1666
1667     return 6; //return number of emited bits
1668 }
1669
1670 //====================================================================
1671 // prepares address bits
1672 // see EM4469 spec
1673 //====================================================================
1674
1675 //--------------------------------------------------------------------
1676 uint8_t Prepare_Addr( uint8_t addr ) {
1677     //--------------------------------------------------------------------
1678
1679     register uint8_t line_parity;
1680
1681     uint8_t i;
1682     line_parity = 0;
1683     for(i=0;i<6;i++) {
1684         *forward_ptr++ = addr;
1685         line_parity ^= addr;
1686         addr >>= 1;
1687     }
1688
1689     *forward_ptr++ = (line_parity & 1);
1690
1691     return 7; //return number of emited bits
1692 }
1693
1694 //====================================================================
1695 // prepares data bits intreleaved with parity bits
1696 // see EM4469 spec
1697 //====================================================================
1698
1699 //--------------------------------------------------------------------
1700 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1701     //--------------------------------------------------------------------
1702
1703     register uint8_t line_parity;
1704     register uint8_t column_parity;
1705     register uint8_t i, j;
1706     register uint16_t data;
1707
1708     data = data_low;
1709     column_parity = 0;
1710
1711     for(i=0; i<4; i++) {
1712         line_parity = 0;
1713         for(j=0; j<8; j++) {
1714             line_parity ^= data;
1715             column_parity ^= (data & 1) << j;
1716             *forward_ptr++ = data;
1717             data >>= 1;
1718         }
1719         *forward_ptr++ = line_parity;
1720         if(i == 1)
1721             data = data_hi;
1722     }
1723
1724     for(j=0; j<8; j++) {
1725         *forward_ptr++ = column_parity;
1726         column_parity >>= 1;
1727     }
1728     *forward_ptr = 0;
1729
1730     return 45; //return number of emited bits
1731 }
1732
1733 //====================================================================
1734 // Forward Link send function
1735 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1736 // fwd_bit_count set with number of bits to be sent
1737 //====================================================================
1738 void SendForward(uint8_t fwd_bit_count) {
1739
1740     fwd_write_ptr = forwardLink_data;
1741     fwd_bit_sz = fwd_bit_count;
1742
1743     LED_D_ON();
1744
1745     //Field on
1746     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1747     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1748     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1749
1750     // Give it a bit of time for the resonant antenna to settle.
1751     // And for the tag to fully power up
1752     SpinDelay(150);
1753
1754     // force 1st mod pulse (start gap must be longer for 4305)
1755     fwd_bit_sz--; //prepare next bit modulation
1756     fwd_write_ptr++;
1757     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1758     SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1759     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1760     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1761     SpinDelayUs(16*8); //16 cycles on (8us each)
1762
1763     // now start writting
1764     while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1765         if(((*fwd_write_ptr++) & 1) == 1)
1766             SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1767         else {
1768             //These timings work for 4469/4269/4305 (with the 55*8 above)
1769             FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1770             SpinDelayUs(23*8); //16-4 cycles off (8us each)
1771             FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1772             FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1773             SpinDelayUs(9*8); //16 cycles on (8us each)
1774         }
1775     }
1776 }
1777
1778 void EM4xLogin(uint32_t Password) {
1779
1780     uint8_t fwd_bit_count;
1781
1782     forward_ptr = forwardLink_data;
1783     fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1784     fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1785
1786     SendForward(fwd_bit_count);
1787
1788     //Wait for command to complete
1789     SpinDelay(20);
1790
1791 }
1792
1793 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1794
1795     uint8_t fwd_bit_count;
1796     uint8_t *dest = (uint8_t *)BigBuf;
1797     int m=0, i=0;
1798
1799     //If password mode do login
1800     if (PwdMode == 1) EM4xLogin(Pwd);
1801
1802     forward_ptr = forwardLink_data;
1803     fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1804     fwd_bit_count += Prepare_Addr( Address );
1805
1806     m = sizeof(BigBuf);
1807     // Clear destination buffer before sending the command
1808     memset(dest, 128, m);
1809     // Connect the A/D to the peak-detected low-frequency path.
1810     SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1811     // Now set up the SSC to get the ADC samples that are now streaming at us.
1812     FpgaSetupSsc();
1813
1814     SendForward(fwd_bit_count);
1815
1816     // Now do the acquisition
1817     i = 0;
1818     for(;;) {
1819         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1820             AT91C_BASE_SSC->SSC_THR = 0x43;
1821         }
1822         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1823             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1824             i++;
1825             if (i >= m) break;
1826         }
1827     }
1828     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1829     LED_D_OFF();
1830 }
1831
1832 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1833
1834     uint8_t fwd_bit_count;
1835
1836     //If password mode do login
1837     if (PwdMode == 1) EM4xLogin(Pwd);
1838
1839     forward_ptr = forwardLink_data;
1840     fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1841     fwd_bit_count += Prepare_Addr( Address );
1842     fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1843
1844     SendForward(fwd_bit_count);
1845
1846     //Wait for write to complete
1847     SpinDelay(20);
1848     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1849     LED_D_OFF();
1850 }