cvs.zerfleddert.de Git - proxmark3-svn/blob - fpga/hi_read_tx.v

   1 //-----------------------------------------------------------------------------
   2 // The way that we connect things when transmitting a command to an ISO
   3 // 15693 tag, using 100% modulation only for now.
   4 //
   5 // Jonathan Westhues, April 2006
   6 //-----------------------------------------------------------------------------
   7
   8 module hi_read_tx(
   9     pck0, ck_1356meg, ck_1356megb,
  10     pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
  11     adc_d, adc_clk,
  12     ssp_frame, ssp_din, ssp_dout, ssp_clk,
  13     cross_hi, cross_lo,
  14     dbg,
  15     shallow_modulation
  16 );
  17     input pck0, ck_1356meg, ck_1356megb;
  18     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
  19     input [7:0] adc_d;
  20     output adc_clk;
  21     input ssp_dout;
  22     output ssp_frame, ssp_din, ssp_clk;
  23     input cross_hi, cross_lo;
  24     output dbg;
  25     input shallow_modulation;
  26
  27 // low frequency outputs, not relevant
  28 assign pwr_lo = 1'b0;
  29 assign pwr_oe2 = 1'b0;
  30
  31 // The high-frequency stuff. For now, for testing, just bring out the carrier,
  32 // and allow the ARM to modulate it over the SSP.
  33 reg pwr_hi;
  34 reg pwr_oe1;
  35 reg pwr_oe3;
  36 reg pwr_oe4;
  37
  38 always @(ck_1356megb or ssp_dout or shallow_modulation)
  39 begin
  40     if(shallow_modulation)
  41     begin
  42         pwr_hi <= ck_1356megb;
  43         pwr_oe1 <= 1'b0;
  44         pwr_oe3 <= 1'b0;
  45         pwr_oe4 <= ~ssp_dout;
  46     end
  47     else
  48     begin
  49         pwr_hi <= ck_1356megb & ssp_dout;
  50         pwr_oe1 <= 1'b0;
  51         pwr_oe3 <= 1'b0;
  52         pwr_oe4 <= 1'b0;
  53     end
  54 end
  55
  56
  57 // Then just divide the 13.56 MHz clock down to produce appropriate clocks
  58 // for the synchronous serial port.
  59
  60 reg [6:0] hi_div_by_128;
  61
  62 always @(posedge ck_1356meg)
  63     hi_div_by_128 <= hi_div_by_128 + 1;
  64
  65 assign ssp_clk = hi_div_by_128[6];
  66
  67 reg [2:0] hi_byte_div;
  68
  69 always @(negedge ssp_clk)
  70     hi_byte_div <= hi_byte_div + 1;
  71
  72 assign ssp_frame = (hi_byte_div == 3'b000);
  73
  74 // Implement a hysteresis to give out the received signal on
  75 // ssp_din. Sample at fc.
  76 assign adc_clk = ck_1356meg;
  77
  78 // ADC data appears on the rising edge, so sample it on the falling edge
  79 reg after_hysteresis;
  80 always @(negedge adc_clk)
  81 begin
  82     if(& adc_d[7:0]) after_hysteresis <= 1'b1;
  83     else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
  84 end
  85
  86
  87 assign ssp_din = after_hysteresis;
  88
  89 assign dbg = ssp_din;
  90
  91 endmodule