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Fixed (?) issues from PR #129
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "usb_cdc.h"
20
21
22 /**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
30 {
31
32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
34
35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
71
72 // now do the read
73 DoAcquisition_config(false);
74 }
75
76
77
78 /* blank r/w tag data stream
79 ...0000000000000000 01111111
80 1010101010101010101010101010101010101010101010101010101010101010
81 0011010010100001
82 01111111
83 101010101010101[0]000...
84
85 [5555fe852c5555555555555555fe0000]
86 */
87 void ReadTItag(void)
88 {
89 // some hardcoded initial params
90 // when we read a TI tag we sample the zerocross line at 2Mhz
91 // TI tags modulate a 1 as 16 cycles of 123.2Khz
92 // TI tags modulate a 0 as 16 cycles of 134.2Khz
93 #define FSAMPLE 2000000
94 #define FREQLO 123200
95 #define FREQHI 134200
96
97 signed char *dest = (signed char *)BigBuf_get_addr();
98 uint16_t n = BigBuf_max_traceLen();
99 // 128 bit shift register [shift3:shift2:shift1:shift0]
100 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
101
102 int i, cycles=0, samples=0;
103 // how many sample points fit in 16 cycles of each frequency
104 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
105 // when to tell if we're close enough to one freq or another
106 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
107
108 // TI tags charge at 134.2Khz
109 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
110 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
111
112 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
113 // connects to SSP_DIN and the SSP_DOUT logic level controls
114 // whether we're modulating the antenna (high)
115 // or listening to the antenna (low)
116 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
117
118 // get TI tag data into the buffer
119 AcquireTiType();
120
121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
122
123 for (i=0; i<n-1; i++) {
124 // count cycles by looking for lo to hi zero crossings
125 if ( (dest[i]<0) && (dest[i+1]>0) ) {
126 cycles++;
127 // after 16 cycles, measure the frequency
128 if (cycles>15) {
129 cycles=0;
130 samples=i-samples; // number of samples in these 16 cycles
131
132 // TI bits are coming to us lsb first so shift them
133 // right through our 128 bit right shift register
134 shift0 = (shift0>>1) | (shift1 << 31);
135 shift1 = (shift1>>1) | (shift2 << 31);
136 shift2 = (shift2>>1) | (shift3 << 31);
137 shift3 >>= 1;
138
139 // check if the cycles fall close to the number
140 // expected for either the low or high frequency
141 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
142 // low frequency represents a 1
143 shift3 |= (1<<31);
144 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
145 // high frequency represents a 0
146 } else {
147 // probably detected a gay waveform or noise
148 // use this as gaydar or discard shift register and start again
149 shift3 = shift2 = shift1 = shift0 = 0;
150 }
151 samples = i;
152
153 // for each bit we receive, test if we've detected a valid tag
154
155 // if we see 17 zeroes followed by 6 ones, we might have a tag
156 // remember the bits are backwards
157 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
158 // if start and end bytes match, we have a tag so break out of the loop
159 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
160 cycles = 0xF0B; //use this as a flag (ugly but whatever)
161 break;
162 }
163 }
164 }
165 }
166 }
167
168 // if flag is set we have a tag
169 if (cycles!=0xF0B) {
170 DbpString("Info: No valid tag detected.");
171 } else {
172 // put 64 bit data into shift1 and shift0
173 shift0 = (shift0>>24) | (shift1 << 8);
174 shift1 = (shift1>>24) | (shift2 << 8);
175
176 // align 16 bit crc into lower half of shift2
177 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
178
179 // if r/w tag, check ident match
180 if (shift3 & (1<<15) ) {
181 DbpString("Info: TI tag is rewriteable");
182 // only 15 bits compare, last bit of ident is not valid
183 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
184 DbpString("Error: Ident mismatch!");
185 } else {
186 DbpString("Info: TI tag ident is valid");
187 }
188 } else {
189 DbpString("Info: TI tag is readonly");
190 }
191
192 // WARNING the order of the bytes in which we calc crc below needs checking
193 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
194 // bytes in reverse or something
195 // calculate CRC
196 uint32_t crc=0;
197
198 crc = update_crc16(crc, (shift0)&0xff);
199 crc = update_crc16(crc, (shift0>>8)&0xff);
200 crc = update_crc16(crc, (shift0>>16)&0xff);
201 crc = update_crc16(crc, (shift0>>24)&0xff);
202 crc = update_crc16(crc, (shift1)&0xff);
203 crc = update_crc16(crc, (shift1>>8)&0xff);
204 crc = update_crc16(crc, (shift1>>16)&0xff);
205 crc = update_crc16(crc, (shift1>>24)&0xff);
206
207 Dbprintf("Info: Tag data: %x%08x, crc=%x",
208 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
209 if (crc != (shift2&0xffff)) {
210 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
211 } else {
212 DbpString("Info: CRC is good");
213 }
214 }
215 }
216
217 void WriteTIbyte(uint8_t b)
218 {
219 int i = 0;
220
221 // modulate 8 bits out to the antenna
222 for (i=0; i<8; i++)
223 {
224 if (b&(1<<i)) {
225 // stop modulating antenna
226 LOW(GPIO_SSC_DOUT);
227 SpinDelayUs(1000);
228 // modulate antenna
229 HIGH(GPIO_SSC_DOUT);
230 SpinDelayUs(1000);
231 } else {
232 // stop modulating antenna
233 LOW(GPIO_SSC_DOUT);
234 SpinDelayUs(300);
235 // modulate antenna
236 HIGH(GPIO_SSC_DOUT);
237 SpinDelayUs(1700);
238 }
239 }
240 }
241
242 void AcquireTiType(void)
243 {
244 int i, j, n;
245 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
246 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
247 #define TIBUFLEN 1250
248
249 // clear buffer
250 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
251 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
252
253 // Set up the synchronous serial port
254 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
255 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
256
257 // steal this pin from the SSP and use it to control the modulation
258 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
259 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
260
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
262 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
263
264 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
265 // 48/2 = 24 MHz clock must be divided by 12
266 AT91C_BASE_SSC->SSC_CMR = 12;
267
268 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
269 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
270 AT91C_BASE_SSC->SSC_TCMR = 0;
271 AT91C_BASE_SSC->SSC_TFMR = 0;
272
273 LED_D_ON();
274
275 // modulate antenna
276 HIGH(GPIO_SSC_DOUT);
277
278 // Charge TI tag for 50ms.
279 SpinDelay(50);
280
281 // stop modulating antenna and listen
282 LOW(GPIO_SSC_DOUT);
283
284 LED_D_OFF();
285
286 i = 0;
287 for(;;) {
288 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
289 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
290 i++; if(i >= TIBUFLEN) break;
291 }
292 WDT_HIT();
293 }
294
295 // return stolen pin to SSP
296 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
297 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
298
299 char *dest = (char *)BigBuf_get_addr();
300 n = TIBUFLEN*32;
301 // unpack buffer
302 for (i=TIBUFLEN-1; i>=0; i--) {
303 for (j=0; j<32; j++) {
304 if(BigBuf[i] & (1 << j)) {
305 dest[--n] = 1;
306 } else {
307 dest[--n] = -1;
308 }
309 }
310 }
311 }
312
313 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
314 // if crc provided, it will be written with the data verbatim (even if bogus)
315 // if not provided a valid crc will be computed from the data and written.
316 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
317 {
318 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
319 if(crc == 0) {
320 crc = update_crc16(crc, (idlo)&0xff);
321 crc = update_crc16(crc, (idlo>>8)&0xff);
322 crc = update_crc16(crc, (idlo>>16)&0xff);
323 crc = update_crc16(crc, (idlo>>24)&0xff);
324 crc = update_crc16(crc, (idhi)&0xff);
325 crc = update_crc16(crc, (idhi>>8)&0xff);
326 crc = update_crc16(crc, (idhi>>16)&0xff);
327 crc = update_crc16(crc, (idhi>>24)&0xff);
328 }
329 Dbprintf("Writing to tag: %x%08x, crc=%x",
330 (unsigned int) idhi, (unsigned int) idlo, crc);
331
332 // TI tags charge at 134.2Khz
333 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
334 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
335 // connects to SSP_DIN and the SSP_DOUT logic level controls
336 // whether we're modulating the antenna (high)
337 // or listening to the antenna (low)
338 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
339 LED_A_ON();
340
341 // steal this pin from the SSP and use it to control the modulation
342 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
343 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
344
345 // writing algorithm:
346 // a high bit consists of a field off for 1ms and field on for 1ms
347 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
348 // initiate a charge time of 50ms (field on) then immediately start writing bits
349 // start by writing 0xBB (keyword) and 0xEB (password)
350 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
351 // finally end with 0x0300 (write frame)
352 // all data is sent lsb firts
353 // finish with 15ms programming time
354
355 // modulate antenna
356 HIGH(GPIO_SSC_DOUT);
357 SpinDelay(50); // charge time
358
359 WriteTIbyte(0xbb); // keyword
360 WriteTIbyte(0xeb); // password
361 WriteTIbyte( (idlo )&0xff );
362 WriteTIbyte( (idlo>>8 )&0xff );
363 WriteTIbyte( (idlo>>16)&0xff );
364 WriteTIbyte( (idlo>>24)&0xff );
365 WriteTIbyte( (idhi )&0xff );
366 WriteTIbyte( (idhi>>8 )&0xff );
367 WriteTIbyte( (idhi>>16)&0xff );
368 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
369 WriteTIbyte( (crc )&0xff ); // crc lo
370 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
371 WriteTIbyte(0x00); // write frame lo
372 WriteTIbyte(0x03); // write frame hi
373 HIGH(GPIO_SSC_DOUT);
374 SpinDelay(50); // programming time
375
376 LED_A_OFF();
377
378 // get TI tag data into the buffer
379 AcquireTiType();
380
381 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
382 DbpString("Now use tiread to check");
383 }
384
385 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
386 {
387 int i;
388 uint8_t *tab = BigBuf_get_addr();
389
390 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
391 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
392
393 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
394
395 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
396 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
397
398 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
399 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
400
401 i = 0;
402 byte_t rx[sizeof(UsbCommand)]; // Storage for usb_read call in loop
403 for(;;) {
404 //wait until SSC_CLK goes HIGH
405 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
406 // Craig Young - Adding a usb_read() here to avoid abort on empty UsbCommand
407 // My OS X client does this preventing simulation.
408 // Performance hit should be non-existent since the read is only performed if usb_poll is true
409 if(BUTTON_PRESS() || (usb_poll() && usb_read(rx,sizeof(UsbCommand)))) {
410 DbpString("Stopped");
411 return;
412 }
413 WDT_HIT();
414 }
415 if (ledcontrol)
416 LED_D_ON();
417
418 if(tab[i])
419 OPEN_COIL();
420 else
421 SHORT_COIL();
422
423 if (ledcontrol)
424 LED_D_OFF();
425 //wait until SSC_CLK goes LOW
426 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
427 if(BUTTON_PRESS()) {
428 DbpString("Stopped");
429 return;
430 }
431 WDT_HIT();
432 }
433
434 i++;
435 if(i == period) {
436
437 i = 0;
438 if (gap) {
439 SHORT_COIL();
440 SpinDelayUs(gap);
441 }
442 }
443 }
444 }
445
446 #define DEBUG_FRAME_CONTENTS 1
447 void SimulateTagLowFrequencyBidir(int divisor, int t0)
448 {
449 }
450
451 // compose fc/8 fc/10 waveform (FSK2)
452 static void fc(int c, int *n)
453 {
454 uint8_t *dest = BigBuf_get_addr();
455 int idx;
456
457 // for when we want an fc8 pattern every 4 logical bits
458 if(c==0) {
459 dest[((*n)++)]=1;
460 dest[((*n)++)]=1;
461 dest[((*n)++)]=1;
462 dest[((*n)++)]=1;
463 dest[((*n)++)]=0;
464 dest[((*n)++)]=0;
465 dest[((*n)++)]=0;
466 dest[((*n)++)]=0;
467 }
468
469 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
470 if(c==8) {
471 for (idx=0; idx<6; idx++) {
472 dest[((*n)++)]=1;
473 dest[((*n)++)]=1;
474 dest[((*n)++)]=1;
475 dest[((*n)++)]=1;
476 dest[((*n)++)]=0;
477 dest[((*n)++)]=0;
478 dest[((*n)++)]=0;
479 dest[((*n)++)]=0;
480 }
481 }
482
483 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
484 if(c==10) {
485 for (idx=0; idx<5; idx++) {
486 dest[((*n)++)]=1;
487 dest[((*n)++)]=1;
488 dest[((*n)++)]=1;
489 dest[((*n)++)]=1;
490 dest[((*n)++)]=1;
491 dest[((*n)++)]=0;
492 dest[((*n)++)]=0;
493 dest[((*n)++)]=0;
494 dest[((*n)++)]=0;
495 dest[((*n)++)]=0;
496 }
497 }
498 }
499 // compose fc/X fc/Y waveform (FSKx)
500 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
501 {
502 uint8_t *dest = BigBuf_get_addr();
503 uint8_t halfFC = fc/2;
504 uint8_t wavesPerClock = clock/fc;
505 uint8_t mod = clock % fc; //modifier
506 uint8_t modAdj = fc/mod; //how often to apply modifier
507 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
508 // loop through clock - step field clock
509 for (uint8_t idx=0; idx < wavesPerClock; idx++){
510 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
511 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
512 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
513 *n += fc;
514 }
515 if (mod>0) (*modCnt)++;
516 if ((mod>0) && modAdjOk){ //fsk2
517 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
518 memset(dest+(*n), 0, fc-halfFC);
519 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
520 *n += fc;
521 }
522 }
523 if (mod>0 && !modAdjOk){ //fsk1
524 memset(dest+(*n), 0, mod-(mod/2));
525 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
526 *n += mod;
527 }
528 }
529
530 // prepare a waveform pattern in the buffer based on the ID given then
531 // simulate a HID tag until the button is pressed
532 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
533 {
534 int n=0, i=0;
535 /*
536 HID tag bitstream format
537 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
538 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
539 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
540 A fc8 is inserted before every 4 bits
541 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
542 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
543 */
544
545 if (hi>0xFFF) {
546 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
547 return;
548 }
549 fc(0,&n);
550 // special start of frame marker containing invalid bit sequences
551 fc(8, &n); fc(8, &n); // invalid
552 fc(8, &n); fc(10, &n); // logical 0
553 fc(10, &n); fc(10, &n); // invalid
554 fc(8, &n); fc(10, &n); // logical 0
555
556 WDT_HIT();
557 // manchester encode bits 43 to 32
558 for (i=11; i>=0; i--) {
559 if ((i%4)==3) fc(0,&n);
560 if ((hi>>i)&1) {
561 fc(10, &n); fc(8, &n); // low-high transition
562 } else {
563 fc(8, &n); fc(10, &n); // high-low transition
564 }
565 }
566
567 WDT_HIT();
568 // manchester encode bits 31 to 0
569 for (i=31; i>=0; i--) {
570 if ((i%4)==3) fc(0,&n);
571 if ((lo>>i)&1) {
572 fc(10, &n); fc(8, &n); // low-high transition
573 } else {
574 fc(8, &n); fc(10, &n); // high-low transition
575 }
576 }
577
578 if (ledcontrol)
579 LED_A_ON();
580 SimulateTagLowFrequency(n, 0, ledcontrol);
581
582 if (ledcontrol)
583 LED_A_OFF();
584 }
585
586 // prepare a waveform pattern in the buffer based on the ID given then
587 // simulate a FSK tag until the button is pressed
588 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
589 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
590 {
591 int ledcontrol=1;
592 int n=0, i=0;
593 uint8_t fcHigh = arg1 >> 8;
594 uint8_t fcLow = arg1 & 0xFF;
595 uint16_t modCnt = 0;
596 uint8_t clk = arg2 & 0xFF;
597 uint8_t invert = (arg2 >> 8) & 1;
598
599 for (i=0; i<size; i++){
600 if (BitStream[i] == invert){
601 fcAll(fcLow, &n, clk, &modCnt);
602 } else {
603 fcAll(fcHigh, &n, clk, &modCnt);
604 }
605 }
606 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
607 /*Dbprintf("DEBUG: First 32:");
608 uint8_t *dest = BigBuf_get_addr();
609 i=0;
610 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
611 i+=16;
612 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
613 */
614 if (ledcontrol)
615 LED_A_ON();
616
617 SimulateTagLowFrequency(n, 0, ledcontrol);
618
619 if (ledcontrol)
620 LED_A_OFF();
621 }
622
623 // compose ask waveform for one bit(ASK)
624 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
625 {
626 uint8_t *dest = BigBuf_get_addr();
627 uint8_t halfClk = clock/2;
628 // c = current bit 1 or 0
629 if (manchester==1){
630 memset(dest+(*n), c, halfClk);
631 memset(dest+(*n) + halfClk, c^1, halfClk);
632 } else {
633 memset(dest+(*n), c, clock);
634 }
635 *n += clock;
636 }
637
638 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
639 {
640 uint8_t *dest = BigBuf_get_addr();
641 uint8_t halfClk = clock/2;
642 if (c){
643 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
644 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
645 } else {
646 memset(dest+(*n), c ^ *phase, clock);
647 *phase ^= 1;
648 }
649
650 }
651
652 // args clock, ask/man or askraw, invert, transmission separator
653 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
654 {
655 int ledcontrol = 1;
656 int n=0, i=0;
657 uint8_t clk = (arg1 >> 8) & 0xFF;
658 uint8_t encoding = arg1 & 0xFF;
659 uint8_t separator = arg2 & 1;
660 uint8_t invert = (arg2 >> 8) & 1;
661
662 if (encoding==2){ //biphase
663 uint8_t phase=0;
664 for (i=0; i<size; i++){
665 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
666 }
667 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
668 for (i=0; i<size; i++){
669 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
670 }
671 }
672 } else { // ask/manchester || ask/raw
673 for (i=0; i<size; i++){
674 askSimBit(BitStream[i]^invert, &n, clk, encoding);
675 }
676 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
677 for (i=0; i<size; i++){
678 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
679 }
680 }
681 }
682
683 if (separator==1) Dbprintf("sorry but separator option not yet available");
684
685 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
686 //DEBUG
687 //Dbprintf("First 32:");
688 //uint8_t *dest = BigBuf_get_addr();
689 //i=0;
690 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
691 //i+=16;
692 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
693
694 if (ledcontrol)
695 LED_A_ON();
696
697 SimulateTagLowFrequency(n, 0, ledcontrol);
698
699 if (ledcontrol)
700 LED_A_OFF();
701 }
702
703 //carrier can be 2,4 or 8
704 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
705 {
706 uint8_t *dest = BigBuf_get_addr();
707 uint8_t halfWave = waveLen/2;
708 //uint8_t idx;
709 int i = 0;
710 if (phaseChg){
711 // write phase change
712 memset(dest+(*n), *curPhase^1, halfWave);
713 memset(dest+(*n) + halfWave, *curPhase, halfWave);
714 *n += waveLen;
715 *curPhase ^= 1;
716 i += waveLen;
717 }
718 //write each normal clock wave for the clock duration
719 for (; i < clk; i+=waveLen){
720 memset(dest+(*n), *curPhase, halfWave);
721 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
722 *n += waveLen;
723 }
724 }
725
726 // args clock, carrier, invert,
727 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
728 {
729 int ledcontrol=1;
730 int n=0, i=0;
731 uint8_t clk = arg1 >> 8;
732 uint8_t carrier = arg1 & 0xFF;
733 uint8_t invert = arg2 & 0xFF;
734 uint8_t curPhase = 0;
735 for (i=0; i<size; i++){
736 if (BitStream[i] == curPhase){
737 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
738 } else {
739 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
740 }
741 }
742 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
743 //Dbprintf("DEBUG: First 32:");
744 //uint8_t *dest = BigBuf_get_addr();
745 //i=0;
746 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
747 //i+=16;
748 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
749
750 if (ledcontrol)
751 LED_A_ON();
752 SimulateTagLowFrequency(n, 0, ledcontrol);
753
754 if (ledcontrol)
755 LED_A_OFF();
756 }
757
758 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
759 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
760 {
761 uint8_t *dest = BigBuf_get_addr();
762 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
763 size_t size;
764 uint32_t hi2=0, hi=0, lo=0;
765 int idx=0;
766 // Configure to go in 125Khz listen mode
767 LFSetupFPGAForADC(95, true);
768
769 while(!BUTTON_PRESS()) {
770
771 WDT_HIT();
772 if (ledcontrol) LED_A_ON();
773
774 DoAcquisition_default(-1,true);
775 // FSK demodulator
776 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
777 size = 50*128*2; //big enough to catch 2 sequences of largest format
778 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
779
780 if (idx>0 && lo>0 && (size==96 || size==192)){
781 // go over previously decoded manchester data and decode into usable tag ID
782 if (hi2 != 0){ //extra large HID tags 88/192 bits
783 Dbprintf("TAG ID: %x%08x%08x (%d)",
784 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
785 }else { //standard HID tags 44/96 bits
786 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
787 uint8_t bitlen = 0;
788 uint32_t fc = 0;
789 uint32_t cardnum = 0;
790 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
791 uint32_t lo2=0;
792 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
793 uint8_t idx3 = 1;
794 while(lo2 > 1){ //find last bit set to 1 (format len bit)
795 lo2=lo2 >> 1;
796 idx3++;
797 }
798 bitlen = idx3+19;
799 fc =0;
800 cardnum=0;
801 if(bitlen == 26){
802 cardnum = (lo>>1)&0xFFFF;
803 fc = (lo>>17)&0xFF;
804 }
805 if(bitlen == 37){
806 cardnum = (lo>>1)&0x7FFFF;
807 fc = ((hi&0xF)<<12)|(lo>>20);
808 }
809 if(bitlen == 34){
810 cardnum = (lo>>1)&0xFFFF;
811 fc= ((hi&1)<<15)|(lo>>17);
812 }
813 if(bitlen == 35){
814 cardnum = (lo>>1)&0xFFFFF;
815 fc = ((hi&1)<<11)|(lo>>21);
816 }
817 }
818 else { //if bit 38 is not set then 37 bit format is used
819 bitlen= 37;
820 fc =0;
821 cardnum=0;
822 if(bitlen==37){
823 cardnum = (lo>>1)&0x7FFFF;
824 fc = ((hi&0xF)<<12)|(lo>>20);
825 }
826 }
827 //Dbprintf("TAG ID: %x%08x (%d)",
828 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
829 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
830 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
831 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
832 }
833 if (findone){
834 if (ledcontrol) LED_A_OFF();
835 *high = hi;
836 *low = lo;
837 return;
838 }
839 // reset
840 }
841 hi2 = hi = lo = idx = 0;
842 WDT_HIT();
843 }
844 DbpString("Stopped");
845 if (ledcontrol) LED_A_OFF();
846 }
847
848 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
849 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
850 {
851 uint8_t *dest = BigBuf_get_addr();
852 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
853 size_t size;
854 int idx=0;
855 // Configure to go in 125Khz listen mode
856 LFSetupFPGAForADC(95, true);
857
858 while(!BUTTON_PRESS()) {
859
860 WDT_HIT();
861 if (ledcontrol) LED_A_ON();
862
863 DoAcquisition_default(-1,true);
864 // FSK demodulator
865 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
866 size = 50*128*2; //big enough to catch 2 sequences of largest format
867 idx = AWIDdemodFSK(dest, &size);
868
869 if (idx>0 && size==96){
870 // Index map
871 // 0 10 20 30 40 50 60
872 // | | | | | | |
873 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
874 // -----------------------------------------------------------------------------
875 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
876 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
877 // |---26 bit---| |-----117----||-------------142-------------|
878 // b = format bit len, o = odd parity of last 3 bits
879 // f = facility code, c = card number
880 // w = wiegand parity
881 // (26 bit format shown)
882
883 //get raw ID before removing parities
884 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
885 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
886 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
887
888 size = removeParity(dest, idx+8, 4, 1, 88);
889 // ok valid card found!
890
891 // Index map
892 // 0 10 20 30 40 50 60
893 // | | | | | | |
894 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
895 // -----------------------------------------------------------------------------
896 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
897 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
898 // |26 bit| |-117--| |-----142------|
899 // b = format bit len, o = odd parity of last 3 bits
900 // f = facility code, c = card number
901 // w = wiegand parity
902 // (26 bit format shown)
903
904 uint32_t fc = 0;
905 uint32_t cardnum = 0;
906 uint32_t code1 = 0;
907 uint32_t code2 = 0;
908 uint8_t fmtLen = bytebits_to_byte(dest,8);
909 if (fmtLen==26){
910 fc = bytebits_to_byte(dest+9, 8);
911 cardnum = bytebits_to_byte(dest+17, 16);
912 code1 = bytebits_to_byte(dest+8,fmtLen);
913 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
914 } else {
915 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
916 if (fmtLen>32){
917 code1 = bytebits_to_byte(dest+8,fmtLen-32);
918 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
919 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
920 } else{
921 code1 = bytebits_to_byte(dest+8,fmtLen);
922 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
923 }
924 }
925 if (findone){
926 if (ledcontrol) LED_A_OFF();
927 return;
928 }
929 // reset
930 }
931 idx = 0;
932 WDT_HIT();
933 }
934 DbpString("Stopped");
935 if (ledcontrol) LED_A_OFF();
936 }
937
938 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
939 {
940 uint8_t *dest = BigBuf_get_addr();
941
942 size_t size=0, idx=0;
943 int clk=0, invert=0, errCnt=0, maxErr=20;
944 uint32_t hi=0;
945 uint64_t lo=0;
946 // Configure to go in 125Khz listen mode
947 LFSetupFPGAForADC(95, true);
948
949 while(!BUTTON_PRESS()) {
950
951 WDT_HIT();
952 if (ledcontrol) LED_A_ON();
953
954 DoAcquisition_default(-1,true);
955 size = BigBuf_max_traceLen();
956 //askdemod and manchester decode
957 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
958 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
959 WDT_HIT();
960
961 if (errCnt<0) continue;
962
963 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
964 if (errCnt){
965 if (size>64){
966 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
967 hi,
968 (uint32_t)(lo>>32),
969 (uint32_t)lo,
970 (uint32_t)(lo&0xFFFF),
971 (uint32_t)((lo>>16LL) & 0xFF),
972 (uint32_t)(lo & 0xFFFFFF));
973 } else {
974 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
975 (uint32_t)(lo>>32),
976 (uint32_t)lo,
977 (uint32_t)(lo&0xFFFF),
978 (uint32_t)((lo>>16LL) & 0xFF),
979 (uint32_t)(lo & 0xFFFFFF));
980 }
981
982 if (findone){
983 if (ledcontrol) LED_A_OFF();
984 *high=lo>>32;
985 *low=lo & 0xFFFFFFFF;
986 return;
987 }
988 }
989 WDT_HIT();
990 hi = lo = size = idx = 0;
991 clk = invert = errCnt = 0;
992 }
993 DbpString("Stopped");
994 if (ledcontrol) LED_A_OFF();
995 }
996
997 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
998 {
999 uint8_t *dest = BigBuf_get_addr();
1000 int idx=0;
1001 uint32_t code=0, code2=0;
1002 uint8_t version=0;
1003 uint8_t facilitycode=0;
1004 uint16_t number=0;
1005 // Configure to go in 125Khz listen mode
1006 LFSetupFPGAForADC(95, true);
1007
1008 while(!BUTTON_PRESS()) {
1009 WDT_HIT();
1010 if (ledcontrol) LED_A_ON();
1011 DoAcquisition_default(-1,true);
1012 //fskdemod and get start index
1013 WDT_HIT();
1014 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
1015 if (idx<0) continue;
1016 //valid tag found
1017
1018 //Index map
1019 //0 10 20 30 40 50 60
1020 //| | | | | | |
1021 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1022 //-----------------------------------------------------------------------------
1023 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
1024 //
1025 //XSF(version)facility:codeone+codetwo
1026 //Handle the data
1027 if(findone){ //only print binary if we are doing one
1028 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1029 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1030 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1031 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1032 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1033 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1034 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1035 }
1036 code = bytebits_to_byte(dest+idx,32);
1037 code2 = bytebits_to_byte(dest+idx+32,32);
1038 version = bytebits_to_byte(dest+idx+27,8); //14,4
1039 facilitycode = bytebits_to_byte(dest+idx+18,8);
1040 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1041
1042 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
1043 // if we're only looking for one tag
1044 if (findone){
1045 if (ledcontrol) LED_A_OFF();
1046 //LED_A_OFF();
1047 *high=code;
1048 *low=code2;
1049 return;
1050 }
1051 code=code2=0;
1052 version=facilitycode=0;
1053 number=0;
1054 idx=0;
1055
1056 WDT_HIT();
1057 }
1058 DbpString("Stopped");
1059 if (ledcontrol) LED_A_OFF();
1060 }
1061
1062 /*------------------------------
1063 * T5555/T5557/T5567 routines
1064 *------------------------------
1065 */
1066
1067 /* T55x7 configuration register definitions */
1068 #define T55x7_POR_DELAY 0x00000001
1069 #define T55x7_ST_TERMINATOR 0x00000008
1070 #define T55x7_PWD 0x00000010
1071 #define T55x7_MAXBLOCK_SHIFT 5
1072 #define T55x7_AOR 0x00000200
1073 #define T55x7_PSKCF_RF_2 0
1074 #define T55x7_PSKCF_RF_4 0x00000400
1075 #define T55x7_PSKCF_RF_8 0x00000800
1076 #define T55x7_MODULATION_DIRECT 0
1077 #define T55x7_MODULATION_PSK1 0x00001000
1078 #define T55x7_MODULATION_PSK2 0x00002000
1079 #define T55x7_MODULATION_PSK3 0x00003000
1080 #define T55x7_MODULATION_FSK1 0x00004000
1081 #define T55x7_MODULATION_FSK2 0x00005000
1082 #define T55x7_MODULATION_FSK1a 0x00006000
1083 #define T55x7_MODULATION_FSK2a 0x00007000
1084 #define T55x7_MODULATION_MANCHESTER 0x00008000
1085 #define T55x7_MODULATION_BIPHASE 0x00010000
1086 #define T55x7_BITRATE_RF_8 0
1087 #define T55x7_BITRATE_RF_16 0x00040000
1088 #define T55x7_BITRATE_RF_32 0x00080000
1089 #define T55x7_BITRATE_RF_40 0x000C0000
1090 #define T55x7_BITRATE_RF_50 0x00100000
1091 #define T55x7_BITRATE_RF_64 0x00140000
1092 #define T55x7_BITRATE_RF_100 0x00180000
1093 #define T55x7_BITRATE_RF_128 0x001C0000
1094
1095 /* T5555 (Q5) configuration register definitions */
1096 #define T5555_ST_TERMINATOR 0x00000001
1097 #define T5555_MAXBLOCK_SHIFT 0x00000001
1098 #define T5555_MODULATION_MANCHESTER 0
1099 #define T5555_MODULATION_PSK1 0x00000010
1100 #define T5555_MODULATION_PSK2 0x00000020
1101 #define T5555_MODULATION_PSK3 0x00000030
1102 #define T5555_MODULATION_FSK1 0x00000040
1103 #define T5555_MODULATION_FSK2 0x00000050
1104 #define T5555_MODULATION_BIPHASE 0x00000060
1105 #define T5555_MODULATION_DIRECT 0x00000070
1106 #define T5555_INVERT_OUTPUT 0x00000080
1107 #define T5555_PSK_RF_2 0
1108 #define T5555_PSK_RF_4 0x00000100
1109 #define T5555_PSK_RF_8 0x00000200
1110 #define T5555_USE_PWD 0x00000400
1111 #define T5555_USE_AOR 0x00000800
1112 #define T5555_BITRATE_SHIFT 12
1113 #define T5555_FAST_WRITE 0x00004000
1114 #define T5555_PAGE_SELECT 0x00008000
1115
1116 /*
1117 * Relevant times in microsecond
1118 * To compensate antenna falling times shorten the write times
1119 * and enlarge the gap ones.
1120 */
1121 #define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
1122 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
1123 #define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
1124 #define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
1125
1126 #define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
1127
1128 // Write one bit to card
1129 void T55xxWriteBit(int bit)
1130 {
1131 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1132 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1133 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1134 if (bit == 0)
1135 SpinDelayUs(WRITE_0);
1136 else
1137 SpinDelayUs(WRITE_1);
1138 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1139 SpinDelayUs(WRITE_GAP);
1140 }
1141
1142 // Write one card block in page 0, no lock
1143 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1144 {
1145 uint32_t i = 0;
1146
1147 // Set up FPGA, 125kHz
1148 // Wait for config.. (192+8190xPOW)x8 == 67ms
1149 LFSetupFPGAForADC(0, true);
1150
1151 // Now start writting
1152 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1153 SpinDelayUs(START_GAP);
1154
1155 // Opcode
1156 T55xxWriteBit(1);
1157 T55xxWriteBit(0); //Page 0
1158 if (PwdMode == 1){
1159 // Pwd
1160 for (i = 0x80000000; i != 0; i >>= 1)
1161 T55xxWriteBit(Pwd & i);
1162 }
1163 // Lock bit
1164 T55xxWriteBit(0);
1165
1166 // Data
1167 for (i = 0x80000000; i != 0; i >>= 1)
1168 T55xxWriteBit(Data & i);
1169
1170 // Block
1171 for (i = 0x04; i != 0; i >>= 1)
1172 T55xxWriteBit(Block & i);
1173
1174 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1175 // so wait a little more)
1176 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1177 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1178 SpinDelay(20);
1179 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1180 }
1181
1182 void TurnReadLFOn(){
1183 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1184 // Give it a bit of time for the resonant antenna to settle.
1185 SpinDelayUs(8*150);
1186 }
1187
1188
1189 // Read one card block in page 0
1190 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1191 {
1192 uint32_t i = 0;
1193 uint8_t *dest = BigBuf_get_addr();
1194 uint16_t bufferlength = BigBuf_max_traceLen();
1195 if ( bufferlength > T55xx_SAMPLES_SIZE )
1196 bufferlength = T55xx_SAMPLES_SIZE;
1197
1198 // Clear destination buffer before sending the command
1199 memset(dest, 0x80, bufferlength);
1200
1201 // Set up FPGA, 125kHz
1202 // Wait for config.. (192+8190xPOW)x8 == 67ms
1203 LFSetupFPGAForADC(0, true);
1204 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1205 SpinDelayUs(START_GAP);
1206
1207 // Opcode
1208 T55xxWriteBit(1);
1209 T55xxWriteBit(0); //Page 0
1210 if (PwdMode == 1){
1211 // Pwd
1212 for (i = 0x80000000; i != 0; i >>= 1)
1213 T55xxWriteBit(Pwd & i);
1214 }
1215 // Lock bit
1216 T55xxWriteBit(0);
1217 // Block
1218 for (i = 0x04; i != 0; i >>= 1)
1219 T55xxWriteBit(Block & i);
1220
1221 // Turn field on to read the response
1222 TurnReadLFOn();
1223 // Now do the acquisition
1224 i = 0;
1225 for(;;) {
1226 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1227 AT91C_BASE_SSC->SSC_THR = 0x43;
1228 LED_D_ON();
1229 }
1230 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1231 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1232 i++;
1233 LED_D_OFF();
1234 if (i >= bufferlength) break;
1235 }
1236 }
1237
1238 cmd_send(CMD_ACK,0,0,0,0,0);
1239 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1240 LED_D_OFF();
1241 }
1242
1243 // Read card traceability data (page 1)
1244 void T55xxReadTrace(void){
1245
1246 uint32_t i = 0;
1247 uint8_t *dest = BigBuf_get_addr();
1248 uint16_t bufferlength = BigBuf_max_traceLen();
1249 if ( bufferlength > T55xx_SAMPLES_SIZE )
1250 bufferlength= T55xx_SAMPLES_SIZE;
1251
1252 // Clear destination buffer before sending the command
1253 memset(dest, 0x80, bufferlength);
1254
1255 LFSetupFPGAForADC(0, true);
1256 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1257 SpinDelayUs(START_GAP);
1258
1259 // Opcode
1260 T55xxWriteBit(1);
1261 T55xxWriteBit(1); //Page 1
1262
1263 // Turn field on to read the response
1264 TurnReadLFOn();
1265
1266 // Now do the acquisition
1267 for(;;) {
1268 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1269 AT91C_BASE_SSC->SSC_THR = 0x43;
1270 LED_D_ON();
1271 }
1272 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1273 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1274 i++;
1275 LED_D_OFF();
1276
1277 if (i >= bufferlength) break;
1278 }
1279 }
1280
1281 cmd_send(CMD_ACK,0,0,0,0,0);
1282 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1283 LED_D_OFF();
1284 }
1285
1286 /*-------------- Cloning routines -----------*/
1287 // Copy HID id to card and setup block 0 config
1288 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1289 {
1290 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1291 int last_block = 0;
1292
1293 if (longFMT){
1294 // Ensure no more than 84 bits supplied
1295 if (hi2>0xFFFFF) {
1296 DbpString("Tags can only have 84 bits.");
1297 return;
1298 }
1299 // Build the 6 data blocks for supplied 84bit ID
1300 last_block = 6;
1301 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1302 for (int i=0;i<4;i++) {
1303 if (hi2 & (1<<(19-i)))
1304 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1305 else
1306 data1 |= (1<<((3-i)*2)); // 0 -> 01
1307 }
1308
1309 data2 = 0;
1310 for (int i=0;i<16;i++) {
1311 if (hi2 & (1<<(15-i)))
1312 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1313 else
1314 data2 |= (1<<((15-i)*2)); // 0 -> 01
1315 }
1316
1317 data3 = 0;
1318 for (int i=0;i<16;i++) {
1319 if (hi & (1<<(31-i)))
1320 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1321 else
1322 data3 |= (1<<((15-i)*2)); // 0 -> 01
1323 }
1324
1325 data4 = 0;
1326 for (int i=0;i<16;i++) {
1327 if (hi & (1<<(15-i)))
1328 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1329 else
1330 data4 |= (1<<((15-i)*2)); // 0 -> 01
1331 }
1332
1333 data5 = 0;
1334 for (int i=0;i<16;i++) {
1335 if (lo & (1<<(31-i)))
1336 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1337 else
1338 data5 |= (1<<((15-i)*2)); // 0 -> 01
1339 }
1340
1341 data6 = 0;
1342 for (int i=0;i<16;i++) {
1343 if (lo & (1<<(15-i)))
1344 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1345 else
1346 data6 |= (1<<((15-i)*2)); // 0 -> 01
1347 }
1348 }
1349 else {
1350 // Ensure no more than 44 bits supplied
1351 if (hi>0xFFF) {
1352 DbpString("Tags can only have 44 bits.");
1353 return;
1354 }
1355
1356 // Build the 3 data blocks for supplied 44bit ID
1357 last_block = 3;
1358
1359 data1 = 0x1D000000; // load preamble
1360
1361 for (int i=0;i<12;i++) {
1362 if (hi & (1<<(11-i)))
1363 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1364 else
1365 data1 |= (1<<((11-i)*2)); // 0 -> 01
1366 }
1367
1368 data2 = 0;
1369 for (int i=0;i<16;i++) {
1370 if (lo & (1<<(31-i)))
1371 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1372 else
1373 data2 |= (1<<((15-i)*2)); // 0 -> 01
1374 }
1375
1376 data3 = 0;
1377 for (int i=0;i<16;i++) {
1378 if (lo & (1<<(15-i)))
1379 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1380 else
1381 data3 |= (1<<((15-i)*2)); // 0 -> 01
1382 }
1383 }
1384
1385 LED_D_ON();
1386 // Program the data blocks for supplied ID
1387 // and the block 0 for HID format
1388 T55xxWriteBlock(data1,1,0,0);
1389 T55xxWriteBlock(data2,2,0,0);
1390 T55xxWriteBlock(data3,3,0,0);
1391
1392 if (longFMT) { // if long format there are 6 blocks
1393 T55xxWriteBlock(data4,4,0,0);
1394 T55xxWriteBlock(data5,5,0,0);
1395 T55xxWriteBlock(data6,6,0,0);
1396 }
1397
1398 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1399 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1400 T55x7_MODULATION_FSK2a |
1401 last_block << T55x7_MAXBLOCK_SHIFT,
1402 0,0,0);
1403
1404 LED_D_OFF();
1405
1406 DbpString("DONE!");
1407 }
1408
1409 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1410 {
1411 int data1=0, data2=0; //up to six blocks for long format
1412
1413 data1 = hi; // load preamble
1414 data2 = lo;
1415
1416 LED_D_ON();
1417 // Program the data blocks for supplied ID
1418 // and the block 0 for HID format
1419 T55xxWriteBlock(data1,1,0,0);
1420 T55xxWriteBlock(data2,2,0,0);
1421
1422 //Config Block
1423 T55xxWriteBlock(0x00147040,0,0,0);
1424 LED_D_OFF();
1425
1426 DbpString("DONE!");
1427 }
1428
1429 // Define 9bit header for EM410x tags
1430 #define EM410X_HEADER 0x1FF
1431 #define EM410X_ID_LENGTH 40
1432
1433 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1434 {
1435 int i, id_bit;
1436 uint64_t id = EM410X_HEADER;
1437 uint64_t rev_id = 0; // reversed ID
1438 int c_parity[4]; // column parity
1439 int r_parity = 0; // row parity
1440 uint32_t clock = 0;
1441
1442 // Reverse ID bits given as parameter (for simpler operations)
1443 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1444 if (i < 32) {
1445 rev_id = (rev_id << 1) | (id_lo & 1);
1446 id_lo >>= 1;
1447 } else {
1448 rev_id = (rev_id << 1) | (id_hi & 1);
1449 id_hi >>= 1;
1450 }
1451 }
1452
1453 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1454 id_bit = rev_id & 1;
1455
1456 if (i % 4 == 0) {
1457 // Don't write row parity bit at start of parsing
1458 if (i)
1459 id = (id << 1) | r_parity;
1460 // Start counting parity for new row
1461 r_parity = id_bit;
1462 } else {
1463 // Count row parity
1464 r_parity ^= id_bit;
1465 }
1466
1467 // First elements in column?
1468 if (i < 4)
1469 // Fill out first elements
1470 c_parity[i] = id_bit;
1471 else
1472 // Count column parity
1473 c_parity[i % 4] ^= id_bit;
1474
1475 // Insert ID bit
1476 id = (id << 1) | id_bit;
1477 rev_id >>= 1;
1478 }
1479
1480 // Insert parity bit of last row
1481 id = (id << 1) | r_parity;
1482
1483 // Fill out column parity at the end of tag
1484 for (i = 0; i < 4; ++i)
1485 id = (id << 1) | c_parity[i];
1486
1487 // Add stop bit
1488 id <<= 1;
1489
1490 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1491 LED_D_ON();
1492
1493 // Write EM410x ID
1494 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1495 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1496
1497 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1498 if (card) {
1499 // Clock rate is stored in bits 8-15 of the card value
1500 clock = (card & 0xFF00) >> 8;
1501 Dbprintf("Clock rate: %d", clock);
1502 switch (clock)
1503 {
1504 case 32:
1505 clock = T55x7_BITRATE_RF_32;
1506 break;
1507 case 16:
1508 clock = T55x7_BITRATE_RF_16;
1509 break;
1510 case 0:
1511 // A value of 0 is assumed to be 64 for backwards-compatibility
1512 // Fall through...
1513 case 64:
1514 clock = T55x7_BITRATE_RF_64;
1515 break;
1516 default:
1517 Dbprintf("Invalid clock rate: %d", clock);
1518 return;
1519 }
1520
1521 // Writing configuration for T55x7 tag
1522 T55xxWriteBlock(clock |
1523 T55x7_MODULATION_MANCHESTER |
1524 2 << T55x7_MAXBLOCK_SHIFT,
1525 0, 0, 0);
1526 }
1527 else
1528 // Writing configuration for T5555(Q5) tag
1529 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1530 T5555_MODULATION_MANCHESTER |
1531 2 << T5555_MAXBLOCK_SHIFT,
1532 0, 0, 0);
1533
1534 LED_D_OFF();
1535 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1536 (uint32_t)(id >> 32), (uint32_t)id);
1537 }
1538
1539 // Clone Indala 64-bit tag by UID to T55x7
1540 void CopyIndala64toT55x7(int hi, int lo)
1541 {
1542
1543 //Program the 2 data blocks for supplied 64bit UID
1544 // and the block 0 for Indala64 format
1545 T55xxWriteBlock(hi,1,0,0);
1546 T55xxWriteBlock(lo,2,0,0);
1547 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1548 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1549 T55x7_MODULATION_PSK1 |
1550 2 << T55x7_MAXBLOCK_SHIFT,
1551 0, 0, 0);
1552 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1553 // T5567WriteBlock(0x603E1042,0);
1554
1555 DbpString("DONE!");
1556
1557 }
1558
1559 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1560 {
1561
1562 //Program the 7 data blocks for supplied 224bit UID
1563 // and the block 0 for Indala224 format
1564 T55xxWriteBlock(uid1,1,0,0);
1565 T55xxWriteBlock(uid2,2,0,0);
1566 T55xxWriteBlock(uid3,3,0,0);
1567 T55xxWriteBlock(uid4,4,0,0);
1568 T55xxWriteBlock(uid5,5,0,0);
1569 T55xxWriteBlock(uid6,6,0,0);
1570 T55xxWriteBlock(uid7,7,0,0);
1571 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1572 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1573 T55x7_MODULATION_PSK1 |
1574 7 << T55x7_MAXBLOCK_SHIFT,
1575 0,0,0);
1576 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1577 // T5567WriteBlock(0x603E10E2,0);
1578
1579 DbpString("DONE!");
1580
1581 }
1582
1583
1584 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1585 #define max(x,y) ( x<y ? y:x)
1586
1587 int DemodPCF7931(uint8_t **outBlocks) {
1588 uint8_t BitStream[256];
1589 uint8_t Blocks[8][16];
1590 uint8_t *GraphBuffer = BigBuf_get_addr();
1591 int GraphTraceLen = BigBuf_max_traceLen();
1592 int i, j, lastval, bitidx, half_switch;
1593 int clock = 64;
1594 int tolerance = clock / 8;
1595 int pmc, block_done;
1596 int lc, warnings = 0;
1597 int num_blocks = 0;
1598 int lmin=128, lmax=128;
1599 uint8_t dir;
1600
1601 LFSetupFPGAForADC(95, true);
1602 DoAcquisition_default(0, 0);
1603
1604
1605 lmin = 64;
1606 lmax = 192;
1607
1608 i = 2;
1609
1610 /* Find first local max/min */
1611 if(GraphBuffer[1] > GraphBuffer[0]) {
1612 while(i < GraphTraceLen) {
1613 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1614 break;
1615 i++;
1616 }
1617 dir = 0;
1618 }
1619 else {
1620 while(i < GraphTraceLen) {
1621 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1622 break;
1623 i++;
1624 }
1625 dir = 1;
1626 }
1627
1628 lastval = i++;
1629 half_switch = 0;
1630 pmc = 0;
1631 block_done = 0;
1632
1633 for (bitidx = 0; i < GraphTraceLen; i++)
1634 {
1635 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1636 {
1637 lc = i - lastval;
1638 lastval = i;
1639
1640 // Switch depending on lc length:
1641 // Tolerance is 1/8 of clock rate (arbitrary)
1642 if (abs(lc-clock/4) < tolerance) {
1643 // 16T0
1644 if((i - pmc) == lc) { /* 16T0 was previous one */
1645 /* It's a PMC ! */
1646 i += (128+127+16+32+33+16)-1;
1647 lastval = i;
1648 pmc = 0;
1649 block_done = 1;
1650 }
1651 else {
1652 pmc = i;
1653 }
1654 } else if (abs(lc-clock/2) < tolerance) {
1655 // 32TO
1656 if((i - pmc) == lc) { /* 16T0 was previous one */
1657 /* It's a PMC ! */
1658 i += (128+127+16+32+33)-1;
1659 lastval = i;
1660 pmc = 0;
1661 block_done = 1;
1662 }
1663 else if(half_switch == 1) {
1664 BitStream[bitidx++] = 0;
1665 half_switch = 0;
1666 }
1667 else
1668 half_switch++;
1669 } else if (abs(lc-clock) < tolerance) {
1670 // 64TO
1671 BitStream[bitidx++] = 1;
1672 } else {
1673 // Error
1674 warnings++;
1675 if (warnings > 10)
1676 {
1677 Dbprintf("Error: too many detection errors, aborting.");
1678 return 0;
1679 }
1680 }
1681
1682 if(block_done == 1) {
1683 if(bitidx == 128) {
1684 for(j=0; j<16; j++) {
1685 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1686 64*BitStream[j*8+6]+
1687 32*BitStream[j*8+5]+
1688 16*BitStream[j*8+4]+
1689 8*BitStream[j*8+3]+
1690 4*BitStream[j*8+2]+
1691 2*BitStream[j*8+1]+
1692 BitStream[j*8];
1693 }
1694 num_blocks++;
1695 }
1696 bitidx = 0;
1697 block_done = 0;
1698 half_switch = 0;
1699 }
1700 if(i < GraphTraceLen)
1701 {
1702 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1703 else dir = 1;
1704 }
1705 }
1706 if(bitidx==255)
1707 bitidx=0;
1708 warnings = 0;
1709 if(num_blocks == 4) break;
1710 }
1711 memcpy(outBlocks, Blocks, 16*num_blocks);
1712 return num_blocks;
1713 }
1714
1715 int IsBlock0PCF7931(uint8_t *Block) {
1716 // Assume RFU means 0 :)
1717 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1718 return 1;
1719 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1720 return 1;
1721 return 0;
1722 }
1723
1724 int IsBlock1PCF7931(uint8_t *Block) {
1725 // Assume RFU means 0 :)
1726 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1727 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1728 return 1;
1729
1730 return 0;
1731 }
1732
1733 #define ALLOC 16
1734
1735 void ReadPCF7931() {
1736 uint8_t Blocks[8][17];
1737 uint8_t tmpBlocks[4][16];
1738 int i, j, ind, ind2, n;
1739 int num_blocks = 0;
1740 int max_blocks = 8;
1741 int ident = 0;
1742 int error = 0;
1743 int tries = 0;
1744
1745 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1746
1747 do {
1748 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1749 n = DemodPCF7931((uint8_t**)tmpBlocks);
1750 if(!n)
1751 error++;
1752 if(error==10 && num_blocks == 0) {
1753 Dbprintf("Error, no tag or bad tag");
1754 return;
1755 }
1756 else if (tries==20 || error==10) {
1757 Dbprintf("Error reading the tag");
1758 Dbprintf("Here is the partial content");
1759 goto end;
1760 }
1761
1762 for(i=0; i<n; i++)
1763 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1764 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1765 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1766 if(!ident) {
1767 for(i=0; i<n; i++) {
1768 if(IsBlock0PCF7931(tmpBlocks[i])) {
1769 // Found block 0 ?
1770 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1771 // Found block 1!
1772 // \o/
1773 ident = 1;
1774 memcpy(Blocks[0], tmpBlocks[i], 16);
1775 Blocks[0][ALLOC] = 1;
1776 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1777 Blocks[1][ALLOC] = 1;
1778 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1779 // Debug print
1780 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1781 num_blocks = 2;
1782 // Handle following blocks
1783 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1784 if(j==n) j=0;
1785 if(j==i) break;
1786 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1787 Blocks[ind2][ALLOC] = 1;
1788 }
1789 break;
1790 }
1791 }
1792 }
1793 }
1794 else {
1795 for(i=0; i<n; i++) { // Look for identical block in known blocks
1796 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1797 for(j=0; j<max_blocks; j++) {
1798 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1799 // Found an identical block
1800 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1801 if(ind2 < 0)
1802 ind2 = max_blocks;
1803 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1804 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1805 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1806 Blocks[ind2][ALLOC] = 1;
1807 num_blocks++;
1808 if(num_blocks == max_blocks) goto end;
1809 }
1810 }
1811 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1812 if(ind2 > max_blocks)
1813 ind2 = 0;
1814 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1815 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1816 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1817 Blocks[ind2][ALLOC] = 1;
1818 num_blocks++;
1819 if(num_blocks == max_blocks) goto end;
1820 }
1821 }
1822 }
1823 }
1824 }
1825 }
1826 }
1827 tries++;
1828 if (BUTTON_PRESS()) return;
1829 } while (num_blocks != max_blocks);
1830 end:
1831 Dbprintf("-----------------------------------------");
1832 Dbprintf("Memory content:");
1833 Dbprintf("-----------------------------------------");
1834 for(i=0; i<max_blocks; i++) {
1835 if(Blocks[i][ALLOC]==1)
1836 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1837 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1838 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1839 else
1840 Dbprintf("<missing block %d>", i);
1841 }
1842 Dbprintf("-----------------------------------------");
1843
1844 return ;
1845 }
1846
1847
1848 //-----------------------------------
1849 // EM4469 / EM4305 routines
1850 //-----------------------------------
1851 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1852 #define FWD_CMD_WRITE 0xA
1853 #define FWD_CMD_READ 0x9
1854 #define FWD_CMD_DISABLE 0x5
1855
1856
1857 uint8_t forwardLink_data[64]; //array of forwarded bits
1858 uint8_t * forward_ptr; //ptr for forward message preparation
1859 uint8_t fwd_bit_sz; //forwardlink bit counter
1860 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1861
1862 //====================================================================
1863 // prepares command bits
1864 // see EM4469 spec
1865 //====================================================================
1866 //--------------------------------------------------------------------
1867 uint8_t Prepare_Cmd( uint8_t cmd ) {
1868 //--------------------------------------------------------------------
1869
1870 *forward_ptr++ = 0; //start bit
1871 *forward_ptr++ = 0; //second pause for 4050 code
1872
1873 *forward_ptr++ = cmd;
1874 cmd >>= 1;
1875 *forward_ptr++ = cmd;
1876 cmd >>= 1;
1877 *forward_ptr++ = cmd;
1878 cmd >>= 1;
1879 *forward_ptr++ = cmd;
1880
1881 return 6; //return number of emited bits
1882 }
1883
1884 //====================================================================
1885 // prepares address bits
1886 // see EM4469 spec
1887 //====================================================================
1888
1889 //--------------------------------------------------------------------
1890 uint8_t Prepare_Addr( uint8_t addr ) {
1891 //--------------------------------------------------------------------
1892
1893 register uint8_t line_parity;
1894
1895 uint8_t i;
1896 line_parity = 0;
1897 for(i=0;i<6;i++) {
1898 *forward_ptr++ = addr;
1899 line_parity ^= addr;
1900 addr >>= 1;
1901 }
1902
1903 *forward_ptr++ = (line_parity & 1);
1904
1905 return 7; //return number of emited bits
1906 }
1907
1908 //====================================================================
1909 // prepares data bits intreleaved with parity bits
1910 // see EM4469 spec
1911 //====================================================================
1912
1913 //--------------------------------------------------------------------
1914 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1915 //--------------------------------------------------------------------
1916
1917 register uint8_t line_parity;
1918 register uint8_t column_parity;
1919 register uint8_t i, j;
1920 register uint16_t data;
1921
1922 data = data_low;
1923 column_parity = 0;
1924
1925 for(i=0; i<4; i++) {
1926 line_parity = 0;
1927 for(j=0; j<8; j++) {
1928 line_parity ^= data;
1929 column_parity ^= (data & 1) << j;
1930 *forward_ptr++ = data;
1931 data >>= 1;
1932 }
1933 *forward_ptr++ = line_parity;
1934 if(i == 1)
1935 data = data_hi;
1936 }
1937
1938 for(j=0; j<8; j++) {
1939 *forward_ptr++ = column_parity;
1940 column_parity >>= 1;
1941 }
1942 *forward_ptr = 0;
1943
1944 return 45; //return number of emited bits
1945 }
1946
1947 //====================================================================
1948 // Forward Link send function
1949 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1950 // fwd_bit_count set with number of bits to be sent
1951 //====================================================================
1952 void SendForward(uint8_t fwd_bit_count) {
1953
1954 fwd_write_ptr = forwardLink_data;
1955 fwd_bit_sz = fwd_bit_count;
1956
1957 LED_D_ON();
1958
1959 //Field on
1960 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1961 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1962 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1963
1964 // Give it a bit of time for the resonant antenna to settle.
1965 // And for the tag to fully power up
1966 SpinDelay(150);
1967
1968 // force 1st mod pulse (start gap must be longer for 4305)
1969 fwd_bit_sz--; //prepare next bit modulation
1970 fwd_write_ptr++;
1971 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1972 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1973 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1974 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1975 SpinDelayUs(16*8); //16 cycles on (8us each)
1976
1977 // now start writting
1978 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1979 if(((*fwd_write_ptr++) & 1) == 1)
1980 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1981 else {
1982 //These timings work for 4469/4269/4305 (with the 55*8 above)
1983 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1984 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1985 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1986 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1987 SpinDelayUs(9*8); //16 cycles on (8us each)
1988 }
1989 }
1990 }
1991
1992 void EM4xLogin(uint32_t Password) {
1993
1994 uint8_t fwd_bit_count;
1995
1996 forward_ptr = forwardLink_data;
1997 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1998 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1999
2000 SendForward(fwd_bit_count);
2001
2002 //Wait for command to complete
2003 SpinDelay(20);
2004
2005 }
2006
2007 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
2008
2009 uint8_t fwd_bit_count;
2010 uint8_t *dest = BigBuf_get_addr();
2011 int m=0, i=0;
2012
2013 //If password mode do login
2014 if (PwdMode == 1) EM4xLogin(Pwd);
2015
2016 forward_ptr = forwardLink_data;
2017 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
2018 fwd_bit_count += Prepare_Addr( Address );
2019
2020 m = BigBuf_max_traceLen();
2021 // Clear destination buffer before sending the command
2022 memset(dest, 128, m);
2023 // Connect the A/D to the peak-detected low-frequency path.
2024 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
2025 // Now set up the SSC to get the ADC samples that are now streaming at us.
2026 FpgaSetupSsc();
2027
2028 SendForward(fwd_bit_count);
2029
2030 // Now do the acquisition
2031 i = 0;
2032 for(;;) {
2033 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
2034 AT91C_BASE_SSC->SSC_THR = 0x43;
2035 }
2036 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
2037 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
2038 i++;
2039 if (i >= m) break;
2040 }
2041 }
2042 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2043 LED_D_OFF();
2044 }
2045
2046 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
2047
2048 uint8_t fwd_bit_count;
2049
2050 //If password mode do login
2051 if (PwdMode == 1) EM4xLogin(Pwd);
2052
2053 forward_ptr = forwardLink_data;
2054 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
2055 fwd_bit_count += Prepare_Addr( Address );
2056 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
2057
2058 SendForward(fwd_bit_count);
2059
2060 //Wait for write to complete
2061 SpinDelay(20);
2062 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2063 LED_D_OFF();
2064 }
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