cvs.zerfleddert.de Git - proxmark3-svn/blob - fpga/lo_edge_detect.v

   1 //-----------------------------------------------------------------------------
   2 // The way that we connect things in low-frequency simulation mode. In this
   3 // case just pass everything through to the ARM, which can bit-bang this
   4 // (because it is so slow).
   5 //
   6 // Jonathan Westhues, April 2006
   7 //-----------------------------------------------------------------------------
   8
   9 module lo_edge_detect(
  10     pck0, ck_1356meg, ck_1356megb,
  11     pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
  12     adc_d, adc_clk,
  13     ssp_frame, ssp_din, ssp_dout, ssp_clk,
  14     cross_hi, cross_lo,
  15     dbg,
  16           divisor,
  17                 lf_field
  18 );
  19     input pck0, ck_1356meg, ck_1356megb;
  20     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
  21     input [7:0] adc_d;
  22     output adc_clk;
  23     input ssp_dout;
  24     output ssp_frame, ssp_din, ssp_clk;
  25     input cross_hi, cross_lo;
  26     output dbg;
  27           input [7:0] divisor;
  28                 input lf_field;
  29
  30 // Divide the clock to be used for the ADC
  31 reg [7:0] pck_divider;
  32 reg clk_state;
  33
  34 wire tag_modulation;
  35 assign tag_modulation = ssp_dout & !lf_field;
  36 wire reader_modulation;
  37 assign reader_modulation = !ssp_dout & lf_field & clk_state;
  38
  39 // No logic, straight through.
  40 assign pwr_oe1 = 1'b0; // not used in LF mode
  41 assign pwr_oe2 = tag_modulation;
  42 assign pwr_oe3 = tag_modulation;
  43 assign pwr_oe4 = tag_modulation;
  44 assign ssp_clk = cross_lo;
  45 assign pwr_lo = reader_modulation;
  46 assign pwr_hi = 1'b0;
  47 assign dbg = ssp_frame;
  48
  49 always @(posedge pck0)
  50 begin
  51         if(pck_divider == divisor[7:0])
  52                 begin
  53                         pck_divider <= 8'd0;
  54                         clk_state = !clk_state;
  55                 end
  56         else
  57         begin
  58                 pck_divider <= pck_divider + 1;
  59         end
  60 end
  61
  62 assign adc_clk = ~clk_state;
  63
  64 // Toggle the output with hysteresis
  65 //  Set to high if the ADC value is above 200
  66 //  Set to low if the ADC value is below 64
  67 reg is_high;
  68 reg is_low;
  69 reg output_state;
  70
  71 always @(posedge pck0)
  72 begin
  73         if((pck_divider == 8'd7) && !clk_state) begin
  74                 is_high = (adc_d >= 8'd190);
  75                 is_low = (adc_d <= 8'd70);
  76         end
  77 end
  78
  79 always @(posedge is_high or posedge is_low)
  80 begin
  81         if(is_high)
  82                 output_state <= 1'd1;
  83         else if(is_low)
  84                 output_state <= 1'd0;
  85 end
  86
  87 assign ssp_frame = output_state;
  88
  89 endmodule
  90