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clear char array with each call
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "protocols.h"
20 #include "usb_cdc.h" // for usb_poll_validate_length
21
22 /**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint32_t period_1, uint8_t *command)
30 {
31
32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
34
35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
71
72 // now do the read
73 DoAcquisition_config(false);
74 }
75
76 /* blank r/w tag data stream
77 ...0000000000000000 01111111
78 1010101010101010101010101010101010101010101010101010101010101010
79 0011010010100001
80 01111111
81 101010101010101[0]000...
82
83 [5555fe852c5555555555555555fe0000]
84 */
85 void ReadTItag(void)
86 {
87 // some hardcoded initial params
88 // when we read a TI tag we sample the zerocross line at 2Mhz
89 // TI tags modulate a 1 as 16 cycles of 123.2Khz
90 // TI tags modulate a 0 as 16 cycles of 134.2Khz
91 #define FSAMPLE 2000000
92 #define FREQLO 123200
93 #define FREQHI 134200
94
95 signed char *dest = (signed char *)BigBuf_get_addr();
96 uint16_t n = BigBuf_max_traceLen();
97 // 128 bit shift register [shift3:shift2:shift1:shift0]
98 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
99
100 int i, cycles=0, samples=0;
101 // how many sample points fit in 16 cycles of each frequency
102 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
103 // when to tell if we're close enough to one freq or another
104 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
105
106 // TI tags charge at 134.2Khz
107 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
108 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
109
110 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
111 // connects to SSP_DIN and the SSP_DOUT logic level controls
112 // whether we're modulating the antenna (high)
113 // or listening to the antenna (low)
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
115
116 // get TI tag data into the buffer
117 AcquireTiType();
118
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
120
121 for (i=0; i<n-1; i++) {
122 // count cycles by looking for lo to hi zero crossings
123 if ( (dest[i]<0) && (dest[i+1]>0) ) {
124 cycles++;
125 // after 16 cycles, measure the frequency
126 if (cycles>15) {
127 cycles=0;
128 samples=i-samples; // number of samples in these 16 cycles
129
130 // TI bits are coming to us lsb first so shift them
131 // right through our 128 bit right shift register
132 shift0 = (shift0>>1) | (shift1 << 31);
133 shift1 = (shift1>>1) | (shift2 << 31);
134 shift2 = (shift2>>1) | (shift3 << 31);
135 shift3 >>= 1;
136
137 // check if the cycles fall close to the number
138 // expected for either the low or high frequency
139 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
140 // low frequency represents a 1
141 shift3 |= (1<<31);
142 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
143 // high frequency represents a 0
144 } else {
145 // probably detected a gay waveform or noise
146 // use this as gaydar or discard shift register and start again
147 shift3 = shift2 = shift1 = shift0 = 0;
148 }
149 samples = i;
150
151 // for each bit we receive, test if we've detected a valid tag
152
153 // if we see 17 zeroes followed by 6 ones, we might have a tag
154 // remember the bits are backwards
155 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
156 // if start and end bytes match, we have a tag so break out of the loop
157 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
158 cycles = 0xF0B; //use this as a flag (ugly but whatever)
159 break;
160 }
161 }
162 }
163 }
164 }
165
166 // if flag is set we have a tag
167 if (cycles!=0xF0B) {
168 DbpString("Info: No valid tag detected.");
169 } else {
170 // put 64 bit data into shift1 and shift0
171 shift0 = (shift0>>24) | (shift1 << 8);
172 shift1 = (shift1>>24) | (shift2 << 8);
173
174 // align 16 bit crc into lower half of shift2
175 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
176
177 // if r/w tag, check ident match
178 if (shift3 & (1<<15) ) {
179 DbpString("Info: TI tag is rewriteable");
180 // only 15 bits compare, last bit of ident is not valid
181 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
182 DbpString("Error: Ident mismatch!");
183 } else {
184 DbpString("Info: TI tag ident is valid");
185 }
186 } else {
187 DbpString("Info: TI tag is readonly");
188 }
189
190 // WARNING the order of the bytes in which we calc crc below needs checking
191 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
192 // bytes in reverse or something
193 // calculate CRC
194 uint32_t crc=0;
195
196 crc = update_crc16(crc, (shift0)&0xff);
197 crc = update_crc16(crc, (shift0>>8)&0xff);
198 crc = update_crc16(crc, (shift0>>16)&0xff);
199 crc = update_crc16(crc, (shift0>>24)&0xff);
200 crc = update_crc16(crc, (shift1)&0xff);
201 crc = update_crc16(crc, (shift1>>8)&0xff);
202 crc = update_crc16(crc, (shift1>>16)&0xff);
203 crc = update_crc16(crc, (shift1>>24)&0xff);
204
205 Dbprintf("Info: Tag data: %x%08x, crc=%x",
206 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
207 if (crc != (shift2&0xffff)) {
208 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
209 } else {
210 DbpString("Info: CRC is good");
211 }
212 }
213 }
214
215 void WriteTIbyte(uint8_t b)
216 {
217 int i = 0;
218
219 // modulate 8 bits out to the antenna
220 for (i=0; i<8; i++)
221 {
222 if (b&(1<<i)) {
223 // stop modulating antenna
224 LOW(GPIO_SSC_DOUT);
225 SpinDelayUs(1000);
226 // modulate antenna
227 HIGH(GPIO_SSC_DOUT);
228 SpinDelayUs(1000);
229 } else {
230 // stop modulating antenna
231 LOW(GPIO_SSC_DOUT);
232 SpinDelayUs(300);
233 // modulate antenna
234 HIGH(GPIO_SSC_DOUT);
235 SpinDelayUs(1700);
236 }
237 }
238 }
239
240 void AcquireTiType(void)
241 {
242 int i, j, n;
243 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
244 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
245 #define TIBUFLEN 1250
246
247 // clear buffer
248 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
249 BigBuf_Clear_ext(false);
250
251 // Set up the synchronous serial port
252 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
253 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
254
255 // steal this pin from the SSP and use it to control the modulation
256 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
257 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
258
259 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
260 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
261
262 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
263 // 48/2 = 24 MHz clock must be divided by 12
264 AT91C_BASE_SSC->SSC_CMR = 12;
265
266 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
267 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
268 AT91C_BASE_SSC->SSC_TCMR = 0;
269 AT91C_BASE_SSC->SSC_TFMR = 0;
270
271 LED_D_ON();
272
273 // modulate antenna
274 HIGH(GPIO_SSC_DOUT);
275
276 // Charge TI tag for 50ms.
277 SpinDelay(50);
278
279 // stop modulating antenna and listen
280 LOW(GPIO_SSC_DOUT);
281
282 LED_D_OFF();
283
284 i = 0;
285 for(;;) {
286 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
287 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
288 i++; if(i >= TIBUFLEN) break;
289 }
290 WDT_HIT();
291 }
292
293 // return stolen pin to SSP
294 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
295 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
296
297 char *dest = (char *)BigBuf_get_addr();
298 n = TIBUFLEN*32;
299 // unpack buffer
300 for (i=TIBUFLEN-1; i>=0; i--) {
301 for (j=0; j<32; j++) {
302 if(BigBuf[i] & (1 << j)) {
303 dest[--n] = 1;
304 } else {
305 dest[--n] = -1;
306 }
307 }
308 }
309 }
310
311 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
312 // if crc provided, it will be written with the data verbatim (even if bogus)
313 // if not provided a valid crc will be computed from the data and written.
314 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
315 {
316 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
317 if(crc == 0) {
318 crc = update_crc16(crc, (idlo)&0xff);
319 crc = update_crc16(crc, (idlo>>8)&0xff);
320 crc = update_crc16(crc, (idlo>>16)&0xff);
321 crc = update_crc16(crc, (idlo>>24)&0xff);
322 crc = update_crc16(crc, (idhi)&0xff);
323 crc = update_crc16(crc, (idhi>>8)&0xff);
324 crc = update_crc16(crc, (idhi>>16)&0xff);
325 crc = update_crc16(crc, (idhi>>24)&0xff);
326 }
327 Dbprintf("Writing to tag: %x%08x, crc=%x",
328 (unsigned int) idhi, (unsigned int) idlo, crc);
329
330 // TI tags charge at 134.2Khz
331 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
332 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
333 // connects to SSP_DIN and the SSP_DOUT logic level controls
334 // whether we're modulating the antenna (high)
335 // or listening to the antenna (low)
336 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
337 LED_A_ON();
338
339 // steal this pin from the SSP and use it to control the modulation
340 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
341 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
342
343 // writing algorithm:
344 // a high bit consists of a field off for 1ms and field on for 1ms
345 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
346 // initiate a charge time of 50ms (field on) then immediately start writing bits
347 // start by writing 0xBB (keyword) and 0xEB (password)
348 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
349 // finally end with 0x0300 (write frame)
350 // all data is sent lsb firts
351 // finish with 15ms programming time
352
353 // modulate antenna
354 HIGH(GPIO_SSC_DOUT);
355 SpinDelay(50); // charge time
356
357 WriteTIbyte(0xbb); // keyword
358 WriteTIbyte(0xeb); // password
359 WriteTIbyte( (idlo )&0xff );
360 WriteTIbyte( (idlo>>8 )&0xff );
361 WriteTIbyte( (idlo>>16)&0xff );
362 WriteTIbyte( (idlo>>24)&0xff );
363 WriteTIbyte( (idhi )&0xff );
364 WriteTIbyte( (idhi>>8 )&0xff );
365 WriteTIbyte( (idhi>>16)&0xff );
366 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
367 WriteTIbyte( (crc )&0xff ); // crc lo
368 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
369 WriteTIbyte(0x00); // write frame lo
370 WriteTIbyte(0x03); // write frame hi
371 HIGH(GPIO_SSC_DOUT);
372 SpinDelay(50); // programming time
373
374 LED_A_OFF();
375
376 // get TI tag data into the buffer
377 AcquireTiType();
378
379 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
380 DbpString("Now use tiread to check");
381 }
382
383 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
384 {
385 int i;
386 uint8_t *tab = BigBuf_get_addr();
387
388 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
389 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
390
391 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
392
393 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
394 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
395
396 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
397 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
398
399 i = 0;
400 for(;;) {
401 //wait until SSC_CLK goes HIGH
402 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
403 if(BUTTON_PRESS() || (usb_poll_validate_length() )) {
404 DbpString("Stopped");
405 return;
406 }
407 WDT_HIT();
408 }
409 if (ledcontrol)
410 LED_D_ON();
411
412 if(tab[i])
413 OPEN_COIL();
414 else
415 SHORT_COIL();
416
417 if (ledcontrol)
418 LED_D_OFF();
419 //wait until SSC_CLK goes LOW
420 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
421 if(BUTTON_PRESS()) {
422 DbpString("Stopped");
423 return;
424 }
425 WDT_HIT();
426 }
427
428 i++;
429 if(i == period) {
430
431 i = 0;
432 if (gap) {
433 SHORT_COIL();
434 SpinDelayUs(gap);
435 }
436 }
437 }
438 }
439
440 #define DEBUG_FRAME_CONTENTS 1
441 void SimulateTagLowFrequencyBidir(int divisor, int t0)
442 {
443 }
444
445 // compose fc/8 fc/10 waveform (FSK2)
446 static void fc(int c, int *n)
447 {
448 uint8_t *dest = BigBuf_get_addr();
449 int idx;
450
451 // for when we want an fc8 pattern every 4 logical bits
452 if(c==0) {
453 dest[((*n)++)]=1;
454 dest[((*n)++)]=1;
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=0;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 }
462
463 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
464 if(c==8) {
465 for (idx=0; idx<6; idx++) {
466 dest[((*n)++)]=1;
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=0;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 }
475 }
476
477 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
478 if(c==10) {
479 for (idx=0; idx<5; idx++) {
480 dest[((*n)++)]=1;
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 }
491 }
492 }
493 // compose fc/X fc/Y waveform (FSKx)
494 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
495 {
496 uint8_t *dest = BigBuf_get_addr();
497 uint8_t halfFC = fc/2;
498 uint8_t wavesPerClock = clock/fc;
499 uint8_t mod = clock % fc; //modifier
500 uint8_t modAdj = fc/mod; //how often to apply modifier
501 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
502 // loop through clock - step field clock
503 for (uint8_t idx=0; idx < wavesPerClock; idx++){
504 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
505 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
506 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
507 *n += fc;
508 }
509 if (mod>0) (*modCnt)++;
510 if ((mod>0) && modAdjOk){ //fsk2
511 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
512 memset(dest+(*n), 0, fc-halfFC);
513 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
514 *n += fc;
515 }
516 }
517 if (mod>0 && !modAdjOk){ //fsk1
518 memset(dest+(*n), 0, mod-(mod/2));
519 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
520 *n += mod;
521 }
522 }
523
524 // prepare a waveform pattern in the buffer based on the ID given then
525 // simulate a HID tag until the button is pressed
526 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
527 {
528 int n=0, i=0;
529 /*
530 HID tag bitstream format
531 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
532 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
533 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
534 A fc8 is inserted before every 4 bits
535 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
536 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
537 */
538
539 if (hi>0xFFF) {
540 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
541 return;
542 }
543 fc(0,&n);
544 // special start of frame marker containing invalid bit sequences
545 fc(8, &n); fc(8, &n); // invalid
546 fc(8, &n); fc(10, &n); // logical 0
547 fc(10, &n); fc(10, &n); // invalid
548 fc(8, &n); fc(10, &n); // logical 0
549
550 WDT_HIT();
551 // manchester encode bits 43 to 32
552 for (i=11; i>=0; i--) {
553 if ((i%4)==3) fc(0,&n);
554 if ((hi>>i)&1) {
555 fc(10, &n); fc(8, &n); // low-high transition
556 } else {
557 fc(8, &n); fc(10, &n); // high-low transition
558 }
559 }
560
561 WDT_HIT();
562 // manchester encode bits 31 to 0
563 for (i=31; i>=0; i--) {
564 if ((i%4)==3) fc(0,&n);
565 if ((lo>>i)&1) {
566 fc(10, &n); fc(8, &n); // low-high transition
567 } else {
568 fc(8, &n); fc(10, &n); // high-low transition
569 }
570 }
571
572 if (ledcontrol)
573 LED_A_ON();
574 SimulateTagLowFrequency(n, 0, ledcontrol);
575
576 if (ledcontrol)
577 LED_A_OFF();
578 }
579
580 // prepare a waveform pattern in the buffer based on the ID given then
581 // simulate a FSK tag until the button is pressed
582 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
583 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
584 {
585 int ledcontrol=1;
586 int n=0, i=0;
587 uint8_t fcHigh = arg1 >> 8;
588 uint8_t fcLow = arg1 & 0xFF;
589 uint16_t modCnt = 0;
590 uint8_t clk = arg2 & 0xFF;
591 uint8_t invert = (arg2 >> 8) & 1;
592
593 for (i=0; i<size; i++){
594 if (BitStream[i] == invert){
595 fcAll(fcLow, &n, clk, &modCnt);
596 } else {
597 fcAll(fcHigh, &n, clk, &modCnt);
598 }
599 }
600 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
601 /*Dbprintf("DEBUG: First 32:");
602 uint8_t *dest = BigBuf_get_addr();
603 i=0;
604 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
605 i+=16;
606 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
607 */
608 if (ledcontrol)
609 LED_A_ON();
610
611 SimulateTagLowFrequency(n, 0, ledcontrol);
612
613 if (ledcontrol)
614 LED_A_OFF();
615 }
616
617 // compose ask waveform for one bit(ASK)
618 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
619 {
620 uint8_t *dest = BigBuf_get_addr();
621 uint8_t halfClk = clock/2;
622 // c = current bit 1 or 0
623 if (manchester==1){
624 memset(dest+(*n), c, halfClk);
625 memset(dest+(*n) + halfClk, c^1, halfClk);
626 } else {
627 memset(dest+(*n), c, clock);
628 }
629 *n += clock;
630 }
631
632 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
633 {
634 uint8_t *dest = BigBuf_get_addr();
635 uint8_t halfClk = clock/2;
636 if (c){
637 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
638 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
639 } else {
640 memset(dest+(*n), c ^ *phase, clock);
641 *phase ^= 1;
642 }
643 }
644
645 // args clock, ask/man or askraw, invert, transmission separator
646 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
647 {
648 int ledcontrol = 1;
649 int n=0, i=0;
650 uint8_t clk = (arg1 >> 8) & 0xFF;
651 uint8_t encoding = arg1 & 0xFF;
652 uint8_t separator = arg2 & 1;
653 uint8_t invert = (arg2 >> 8) & 1;
654
655 if (encoding==2){ //biphase
656 uint8_t phase=0;
657 for (i=0; i<size; i++){
658 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
659 }
660 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
661 for (i=0; i<size; i++){
662 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
663 }
664 }
665 } else { // ask/manchester || ask/raw
666 for (i=0; i<size; i++){
667 askSimBit(BitStream[i]^invert, &n, clk, encoding);
668 }
669 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
670 for (i=0; i<size; i++){
671 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
672 }
673 }
674 }
675
676 if (separator==1) Dbprintf("sorry but separator option not yet available");
677
678 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
679 //DEBUG
680 //Dbprintf("First 32:");
681 //uint8_t *dest = BigBuf_get_addr();
682 //i=0;
683 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
684 //i+=16;
685 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
686
687 if (ledcontrol) LED_A_ON();
688 SimulateTagLowFrequency(n, 0, ledcontrol);
689 if (ledcontrol) LED_A_OFF();
690 }
691
692 //carrier can be 2,4 or 8
693 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
694 {
695 uint8_t *dest = BigBuf_get_addr();
696 uint8_t halfWave = waveLen/2;
697 //uint8_t idx;
698 int i = 0;
699 if (phaseChg){
700 // write phase change
701 memset(dest+(*n), *curPhase^1, halfWave);
702 memset(dest+(*n) + halfWave, *curPhase, halfWave);
703 *n += waveLen;
704 *curPhase ^= 1;
705 i += waveLen;
706 }
707 //write each normal clock wave for the clock duration
708 for (; i < clk; i+=waveLen){
709 memset(dest+(*n), *curPhase, halfWave);
710 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
711 *n += waveLen;
712 }
713 }
714
715 // args clock, carrier, invert,
716 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
717 {
718 int ledcontrol=1;
719 int n=0, i=0;
720 uint8_t clk = arg1 >> 8;
721 uint8_t carrier = arg1 & 0xFF;
722 uint8_t invert = arg2 & 0xFF;
723 uint8_t curPhase = 0;
724 for (i=0; i<size; i++){
725 if (BitStream[i] == curPhase){
726 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
727 } else {
728 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
729 }
730 }
731 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
732 //Dbprintf("DEBUG: First 32:");
733 //uint8_t *dest = BigBuf_get_addr();
734 //i=0;
735 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
736 //i+=16;
737 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
738
739 if (ledcontrol) LED_A_ON();
740 SimulateTagLowFrequency(n, 0, ledcontrol);
741 if (ledcontrol) LED_A_OFF();
742 }
743
744 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
745 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
746 {
747 uint8_t *dest = BigBuf_get_addr();
748 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
749 size_t size;
750 uint32_t hi2=0, hi=0, lo=0;
751 int idx=0;
752 // Configure to go in 125Khz listen mode
753 LFSetupFPGAForADC(95, true);
754
755 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
756
757 WDT_HIT();
758 if (ledcontrol) LED_A_ON();
759
760 DoAcquisition_default(-1,true);
761 // FSK demodulator
762 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
763 size = 50*128*2; //big enough to catch 2 sequences of largest format
764 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
765
766 if (idx>0 && lo>0 && (size==96 || size==192)){
767 // go over previously decoded manchester data and decode into usable tag ID
768 if (hi2 != 0){ //extra large HID tags 88/192 bits
769 Dbprintf("TAG ID: %x%08x%08x (%d)",
770 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
771 }else { //standard HID tags 44/96 bits
772 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
773 uint8_t bitlen = 0;
774 uint32_t fc = 0;
775 uint32_t cardnum = 0;
776 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
777 uint32_t lo2=0;
778 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
779 uint8_t idx3 = 1;
780 while(lo2 > 1){ //find last bit set to 1 (format len bit)
781 lo2=lo2 >> 1;
782 idx3++;
783 }
784 bitlen = idx3+19;
785 fc =0;
786 cardnum=0;
787 if(bitlen == 26){
788 cardnum = (lo>>1)&0xFFFF;
789 fc = (lo>>17)&0xFF;
790 }
791 if(bitlen == 37){
792 cardnum = (lo>>1)&0x7FFFF;
793 fc = ((hi&0xF)<<12)|(lo>>20);
794 }
795 if(bitlen == 34){
796 cardnum = (lo>>1)&0xFFFF;
797 fc= ((hi&1)<<15)|(lo>>17);
798 }
799 if(bitlen == 35){
800 cardnum = (lo>>1)&0xFFFFF;
801 fc = ((hi&1)<<11)|(lo>>21);
802 }
803 }
804 else { //if bit 38 is not set then 37 bit format is used
805 bitlen= 37;
806 fc =0;
807 cardnum=0;
808 if(bitlen==37){
809 cardnum = (lo>>1)&0x7FFFF;
810 fc = ((hi&0xF)<<12)|(lo>>20);
811 }
812 }
813 //Dbprintf("TAG ID: %x%08x (%d)",
814 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
815 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
816 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
817 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
818 }
819 if (findone){
820 if (ledcontrol) LED_A_OFF();
821 *high = hi;
822 *low = lo;
823 return;
824 }
825 // reset
826 }
827 hi2 = hi = lo = idx = 0;
828 WDT_HIT();
829 }
830 DbpString("Stopped");
831 if (ledcontrol) LED_A_OFF();
832 }
833
834 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
835 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
836 {
837 uint8_t *dest = BigBuf_get_addr();
838 size_t size;
839 int idx=0;
840 // Configure to go in 125Khz listen mode
841 LFSetupFPGAForADC(95, true);
842
843 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
844
845 WDT_HIT();
846 if (ledcontrol) LED_A_ON();
847
848 DoAcquisition_default(-1,true);
849 // FSK demodulator
850 size = 50*128*2; //big enough to catch 2 sequences of largest format
851 idx = AWIDdemodFSK(dest, &size);
852
853 if (idx<=0 || size!=96) continue;
854 // Index map
855 // 0 10 20 30 40 50 60
856 // | | | | | | |
857 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
858 // -----------------------------------------------------------------------------
859 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
860 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
861 // |---26 bit---| |-----117----||-------------142-------------|
862 // b = format bit len, o = odd parity of last 3 bits
863 // f = facility code, c = card number
864 // w = wiegand parity
865 // (26 bit format shown)
866
867 //get raw ID before removing parities
868 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
869 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
870 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
871
872 size = removeParity(dest, idx+8, 4, 1, 88);
873 if (size != 66) continue;
874 // ok valid card found!
875
876 // Index map
877 // 0 10 20 30 40 50 60
878 // | | | | | | |
879 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
880 // -----------------------------------------------------------------------------
881 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
882 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
883 // |26 bit| |-117--| |-----142------|
884 // b = format bit len, o = odd parity of last 3 bits
885 // f = facility code, c = card number
886 // w = wiegand parity
887 // (26 bit format shown)
888
889 uint32_t fc = 0;
890 uint32_t cardnum = 0;
891 uint32_t code1 = 0;
892 uint32_t code2 = 0;
893 uint8_t fmtLen = bytebits_to_byte(dest,8);
894 if (fmtLen==26){
895 fc = bytebits_to_byte(dest+9, 8);
896 cardnum = bytebits_to_byte(dest+17, 16);
897 code1 = bytebits_to_byte(dest+8,fmtLen);
898 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
899 } else {
900 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
901 if (fmtLen>32){
902 code1 = bytebits_to_byte(dest+8,fmtLen-32);
903 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
904 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
905 } else{
906 code1 = bytebits_to_byte(dest+8,fmtLen);
907 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
908 }
909 }
910 if (findone){
911 if (ledcontrol) LED_A_OFF();
912 return;
913 }
914 // reset
915 idx = 0;
916 WDT_HIT();
917 }
918 DbpString("Stopped");
919 if (ledcontrol) LED_A_OFF();
920 }
921
922 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
923 {
924 uint8_t *dest = BigBuf_get_addr();
925
926 size_t size=0, idx=0;
927 int clk=0, invert=0, errCnt=0, maxErr=20;
928 uint32_t hi=0;
929 uint64_t lo=0;
930 // Configure to go in 125Khz listen mode
931 LFSetupFPGAForADC(95, true);
932
933 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
934
935 WDT_HIT();
936 if (ledcontrol) LED_A_ON();
937
938 DoAcquisition_default(-1,true);
939 size = BigBuf_max_traceLen();
940 //askdemod and manchester decode
941 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
942 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
943 WDT_HIT();
944
945 if (errCnt<0) continue;
946
947 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
948 if (errCnt){
949 if (size>64){
950 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
951 hi,
952 (uint32_t)(lo>>32),
953 (uint32_t)lo,
954 (uint32_t)(lo&0xFFFF),
955 (uint32_t)((lo>>16LL) & 0xFF),
956 (uint32_t)(lo & 0xFFFFFF));
957 } else {
958 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
959 (uint32_t)(lo>>32),
960 (uint32_t)lo,
961 (uint32_t)(lo&0xFFFF),
962 (uint32_t)((lo>>16LL) & 0xFF),
963 (uint32_t)(lo & 0xFFFFFF));
964 }
965
966 if (findone){
967 if (ledcontrol) LED_A_OFF();
968 *high=lo>>32;
969 *low=lo & 0xFFFFFFFF;
970 return;
971 }
972 }
973 WDT_HIT();
974 hi = lo = size = idx = 0;
975 clk = invert = errCnt = 0;
976 }
977 DbpString("Stopped");
978 if (ledcontrol) LED_A_OFF();
979 }
980
981 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
982 {
983 uint8_t *dest = BigBuf_get_addr();
984 int idx=0;
985 uint32_t code=0, code2=0;
986 uint8_t version=0;
987 uint8_t facilitycode=0;
988 uint16_t number=0;
989 // Configure to go in 125Khz listen mode
990 LFSetupFPGAForADC(95, true);
991
992 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
993 WDT_HIT();
994 if (ledcontrol) LED_A_ON();
995 DoAcquisition_default(-1,true);
996 //fskdemod and get start index
997 WDT_HIT();
998 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
999 if (idx<0) continue;
1000 //valid tag found
1001
1002 //Index map
1003 //0 10 20 30 40 50 60
1004 //| | | | | | |
1005 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1006 //-----------------------------------------------------------------------------
1007 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
1008 //
1009 //XSF(version)facility:codeone+codetwo
1010 //Handle the data
1011 if(findone){ //only print binary if we are doing one
1012 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1013 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1014 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1015 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1016 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1017 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1018 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1019 }
1020 code = bytebits_to_byte(dest+idx,32);
1021 code2 = bytebits_to_byte(dest+idx+32,32);
1022 version = bytebits_to_byte(dest+idx+27,8); //14,4
1023 facilitycode = bytebits_to_byte(dest+idx+18,8);
1024 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1025
1026 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
1027 // if we're only looking for one tag
1028 if (findone){
1029 if (ledcontrol) LED_A_OFF();
1030 //LED_A_OFF();
1031 *high=code;
1032 *low=code2;
1033 return;
1034 }
1035 code=code2=0;
1036 version=facilitycode=0;
1037 number=0;
1038 idx=0;
1039
1040 WDT_HIT();
1041 }
1042 DbpString("Stopped");
1043 if (ledcontrol) LED_A_OFF();
1044 }
1045
1046 /*------------------------------
1047 * T5555/T5557/T5567/T5577 routines
1048 *------------------------------
1049 * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
1050 *
1051 * Relevant communication times in microsecond
1052 * To compensate antenna falling times shorten the write times
1053 * and enlarge the gap ones.
1054 * Q5 tags seems to have issues when these values changes.
1055 */
1056 #define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
1057 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
1058 #define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
1059 #define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
1060 #define READ_GAP 15*8
1061
1062 void TurnReadLFOn(int delay) {
1063 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1064 // Give it a bit of time for the resonant antenna to settle.
1065 SpinDelayUs(delay); //155*8 //50*8
1066 }
1067
1068 // Write one bit to card
1069 void T55xxWriteBit(int bit) {
1070 if (!bit)
1071 TurnReadLFOn(WRITE_0);
1072 else
1073 TurnReadLFOn(WRITE_1);
1074 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1075 SpinDelayUs(WRITE_GAP);
1076 }
1077
1078 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
1079 void T55xxResetRead(void) {
1080 LED_A_ON();
1081 //clear buffer now so it does not interfere with timing later
1082 BigBuf_Clear_ext(false);
1083
1084 // Set up FPGA, 125kHz
1085 LFSetupFPGAForADC(95, true);
1086
1087 // Trigger T55x7 in mode.
1088 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1089 SpinDelayUs(START_GAP);
1090
1091 // reset tag - op code 00
1092 T55xxWriteBit(0);
1093 T55xxWriteBit(0);
1094
1095 // Turn field on to read the response
1096 TurnReadLFOn(READ_GAP);
1097
1098 // Acquisition
1099 doT55x7Acquisition(BigBuf_max_traceLen());
1100
1101 // Turn the field off
1102 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1103 cmd_send(CMD_ACK,0,0,0,0,0);
1104 LED_A_OFF();
1105 }
1106
1107 // Write one card block in page 0, no lock
1108 void T55xxWriteBlockExt(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
1109 LED_A_ON();
1110 bool PwdMode = arg & 0x1;
1111 uint8_t Page = (arg & 0x2)>>1;
1112 uint32_t i = 0;
1113
1114 // Set up FPGA, 125kHz
1115 LFSetupFPGAForADC(95, true);
1116
1117 // Trigger T55x7 in mode.
1118 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1119 SpinDelayUs(START_GAP);
1120
1121 // Opcode 10
1122 T55xxWriteBit(1);
1123 T55xxWriteBit(Page); //Page 0
1124 if (PwdMode){
1125 // Send Pwd
1126 for (i = 0x80000000; i != 0; i >>= 1)
1127 T55xxWriteBit(Pwd & i);
1128 }
1129 // Send Lock bit
1130 T55xxWriteBit(0);
1131
1132 // Send Data
1133 for (i = 0x80000000; i != 0; i >>= 1)
1134 T55xxWriteBit(Data & i);
1135
1136 // Send Block number
1137 for (i = 0x04; i != 0; i >>= 1)
1138 T55xxWriteBit(Block & i);
1139
1140 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1141 // so wait a little more)
1142 TurnReadLFOn(20 * 1000);
1143 //could attempt to do a read to confirm write took
1144 // as the tag should repeat back the new block
1145 // until it is reset, but to confirm it we would
1146 // need to know the current block 0 config mode
1147
1148 // turn field off
1149 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1150 LED_A_OFF();
1151 }
1152
1153 // Write one card block in page 0, no lock
1154 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
1155 T55xxWriteBlockExt(Data, Block, Pwd, arg);
1156 cmd_send(CMD_ACK,0,0,0,0,0);
1157 }
1158
1159 // Read one card block in page [page]
1160 void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
1161 LED_A_ON();
1162 bool PwdMode = arg0 & 0x1;
1163 uint8_t Page = (arg0 & 0x2) >> 1;
1164 uint32_t i = 0;
1165 bool RegReadMode = (Block == 0xFF);
1166
1167 //clear buffer now so it does not interfere with timing later
1168 BigBuf_Clear_ext(false);
1169
1170 //make sure block is at max 7
1171 Block &= 0x7;
1172
1173 // Set up FPGA, 125kHz to power up the tag
1174 LFSetupFPGAForADC(95, true);
1175
1176 // Trigger T55x7 Direct Access Mode with start gap
1177 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1178 SpinDelayUs(START_GAP);
1179
1180 // Opcode 1[page]
1181 T55xxWriteBit(1);
1182 T55xxWriteBit(Page); //Page 0
1183
1184 if (PwdMode){
1185 // Send Pwd
1186 for (i = 0x80000000; i != 0; i >>= 1)
1187 T55xxWriteBit(Pwd & i);
1188 }
1189 // Send a zero bit separation
1190 T55xxWriteBit(0);
1191
1192 // Send Block number (if direct access mode)
1193 if (!RegReadMode)
1194 for (i = 0x04; i != 0; i >>= 1)
1195 T55xxWriteBit(Block & i);
1196
1197 // Turn field on to read the response
1198 TurnReadLFOn(READ_GAP);
1199
1200 // Acquisition
1201 doT55x7Acquisition(12000);
1202
1203 // Turn the field off
1204 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1205 cmd_send(CMD_ACK,0,0,0,0,0);
1206 LED_A_OFF();
1207 }
1208
1209 void T55xxWakeUp(uint32_t Pwd){
1210 LED_B_ON();
1211 uint32_t i = 0;
1212
1213 // Set up FPGA, 125kHz
1214 LFSetupFPGAForADC(95, true);
1215
1216 // Trigger T55x7 Direct Access Mode
1217 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1218 SpinDelayUs(START_GAP);
1219
1220 // Opcode 10
1221 T55xxWriteBit(1);
1222 T55xxWriteBit(0); //Page 0
1223
1224 // Send Pwd
1225 for (i = 0x80000000; i != 0; i >>= 1)
1226 T55xxWriteBit(Pwd & i);
1227
1228 // Turn and leave field on to let the begin repeating transmission
1229 TurnReadLFOn(20*1000);
1230 }
1231
1232 /*-------------- Cloning routines -----------*/
1233
1234 void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1235 // write last block first and config block last (if included)
1236 for (uint8_t i = numblocks+startblock; i > startblock; i--) {
1237 T55xxWriteBlockExt(blockdata[i-1],i-1,0,0);
1238 }
1239 }
1240
1241 // Copy HID id to card and setup block 0 config
1242 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
1243 uint32_t data[] = {0,0,0,0,0,0,0};
1244 uint8_t last_block = 0;
1245
1246 if (longFMT) {
1247 // Ensure no more than 84 bits supplied
1248 if (hi2>0xFFFFF) {
1249 DbpString("Tags can only have 84 bits.");
1250 return;
1251 }
1252 // Build the 6 data blocks for supplied 84bit ID
1253 last_block = 6;
1254 // load preamble (1D) & long format identifier (9E manchester encoded)
1255 data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
1256 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1257 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1258 data[3] = manchesterEncode2Bytes(hi >> 16);
1259 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1260 data[5] = manchesterEncode2Bytes(lo >> 16);
1261 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
1262 } else {
1263 // Ensure no more than 44 bits supplied
1264 if (hi>0xFFF) {
1265 DbpString("Tags can only have 44 bits.");
1266 return;
1267 }
1268 // Build the 3 data blocks for supplied 44bit ID
1269 last_block = 3;
1270 // load preamble
1271 data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
1272 data[2] = manchesterEncode2Bytes(lo >> 16);
1273 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
1274 }
1275 // load chip config block
1276 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
1277
1278 //TODO add selection of chip for Q5 or T55x7
1279 // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
1280
1281 LED_D_ON();
1282 // Program the data blocks for supplied ID
1283 // and the block 0 for HID format
1284 WriteT55xx(data, 0, last_block+1);
1285
1286 LED_D_OFF();
1287
1288 DbpString("DONE!");
1289 }
1290
1291 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
1292 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1293 //TODO add selection of chip for Q5 or T55x7
1294 // data[0] = (((64-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
1295
1296 LED_D_ON();
1297 // Program the data blocks for supplied ID
1298 // and the block 0 config
1299 WriteT55xx(data, 0, 3);
1300
1301 LED_D_OFF();
1302
1303 DbpString("DONE!");
1304 }
1305
1306 // Clone Indala 64-bit tag by UID to T55x7
1307 void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1308 //Program the 2 data blocks for supplied 64bit UID
1309 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1310 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1311 //TODO add selection of chip for Q5 or T55x7
1312 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
1313
1314 WriteT55xx(data, 0, 3);
1315 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1316 // T5567WriteBlock(0x603E1042,0);
1317 DbpString("DONE!");
1318 }
1319 // Clone Indala 224-bit tag by UID to T55x7
1320 void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
1321 //Program the 7 data blocks for supplied 224bit UID
1322 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1323 // and the block 0 for Indala224 format
1324 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1325 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
1326 //TODO add selection of chip for Q5 or T55x7
1327 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
1328 WriteT55xx(data, 0, 8);
1329 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1330 // T5567WriteBlock(0x603E10E2,0);
1331 DbpString("DONE!");
1332 }
1333 // clone viking tag to T55xx
1334 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
1335 uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
1336 if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
1337 // Program the data blocks for supplied ID and the block 0 config
1338 WriteT55xx(data, 0, 3);
1339 LED_D_OFF();
1340 cmd_send(CMD_ACK,0,0,0,0,0);
1341 }
1342
1343 // Define 9bit header for EM410x tags
1344 #define EM410X_HEADER 0x1FF
1345 #define EM410X_ID_LENGTH 40
1346
1347 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
1348 int i, id_bit;
1349 uint64_t id = EM410X_HEADER;
1350 uint64_t rev_id = 0; // reversed ID
1351 int c_parity[4]; // column parity
1352 int r_parity = 0; // row parity
1353 uint32_t clock = 0;
1354
1355 // Reverse ID bits given as parameter (for simpler operations)
1356 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1357 if (i < 32) {
1358 rev_id = (rev_id << 1) | (id_lo & 1);
1359 id_lo >>= 1;
1360 } else {
1361 rev_id = (rev_id << 1) | (id_hi & 1);
1362 id_hi >>= 1;
1363 }
1364 }
1365
1366 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1367 id_bit = rev_id & 1;
1368
1369 if (i % 4 == 0) {
1370 // Don't write row parity bit at start of parsing
1371 if (i)
1372 id = (id << 1) | r_parity;
1373 // Start counting parity for new row
1374 r_parity = id_bit;
1375 } else {
1376 // Count row parity
1377 r_parity ^= id_bit;
1378 }
1379
1380 // First elements in column?
1381 if (i < 4)
1382 // Fill out first elements
1383 c_parity[i] = id_bit;
1384 else
1385 // Count column parity
1386 c_parity[i % 4] ^= id_bit;
1387
1388 // Insert ID bit
1389 id = (id << 1) | id_bit;
1390 rev_id >>= 1;
1391 }
1392
1393 // Insert parity bit of last row
1394 id = (id << 1) | r_parity;
1395
1396 // Fill out column parity at the end of tag
1397 for (i = 0; i < 4; ++i)
1398 id = (id << 1) | c_parity[i];
1399
1400 // Add stop bit
1401 id <<= 1;
1402
1403 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1404 LED_D_ON();
1405
1406 // Write EM410x ID
1407 uint32_t data[] = {0, id>>32, id & 0xFFFFFFFF};
1408
1409 clock = (card & 0xFF00) >> 8;
1410 clock = (clock == 0) ? 64 : clock;
1411 Dbprintf("Clock rate: %d", clock);
1412 if (card & 0xFF) { //t55x7
1413 clock = GetT55xxClockBit(clock);
1414 if (clock == 0) {
1415 Dbprintf("Invalid clock rate: %d", clock);
1416 return;
1417 }
1418 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
1419 } else { //t5555 (Q5)
1420 clock = (clock-2)>>1; //n = (RF-2)/2
1421 data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
1422 }
1423
1424 WriteT55xx(data, 0, 3);
1425
1426 LED_D_OFF();
1427 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1428 (uint32_t)(id >> 32), (uint32_t)id);
1429 }
1430
1431 //-----------------------------------
1432 // EM4469 / EM4305 routines
1433 //-----------------------------------
1434 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1435 #define FWD_CMD_WRITE 0xA
1436 #define FWD_CMD_READ 0x9
1437 #define FWD_CMD_DISABLE 0x5
1438
1439 uint8_t forwardLink_data[64]; //array of forwarded bits
1440 uint8_t * forward_ptr; //ptr for forward message preparation
1441 uint8_t fwd_bit_sz; //forwardlink bit counter
1442 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1443
1444 //====================================================================
1445 // prepares command bits
1446 // see EM4469 spec
1447 //====================================================================
1448 //--------------------------------------------------------------------
1449 // VALUES TAKEN FROM EM4x function: SendForward
1450 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1451 // WRITE_GAP = 128; (16*8)
1452 // WRITE_1 = 256 32*8; (32*8)
1453
1454 // These timings work for 4469/4269/4305 (with the 55*8 above)
1455 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1456
1457 uint8_t Prepare_Cmd( uint8_t cmd ) {
1458
1459 *forward_ptr++ = 0; //start bit
1460 *forward_ptr++ = 0; //second pause for 4050 code
1461
1462 *forward_ptr++ = cmd;
1463 cmd >>= 1;
1464 *forward_ptr++ = cmd;
1465 cmd >>= 1;
1466 *forward_ptr++ = cmd;
1467 cmd >>= 1;
1468 *forward_ptr++ = cmd;
1469
1470 return 6; //return number of emited bits
1471 }
1472
1473 //====================================================================
1474 // prepares address bits
1475 // see EM4469 spec
1476 //====================================================================
1477 uint8_t Prepare_Addr( uint8_t addr ) {
1478
1479 register uint8_t line_parity;
1480
1481 uint8_t i;
1482 line_parity = 0;
1483 for(i=0;i<6;i++) {
1484 *forward_ptr++ = addr;
1485 line_parity ^= addr;
1486 addr >>= 1;
1487 }
1488
1489 *forward_ptr++ = (line_parity & 1);
1490
1491 return 7; //return number of emited bits
1492 }
1493
1494 //====================================================================
1495 // prepares data bits intreleaved with parity bits
1496 // see EM4469 spec
1497 //====================================================================
1498 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1499
1500 register uint8_t line_parity;
1501 register uint8_t column_parity;
1502 register uint8_t i, j;
1503 register uint16_t data;
1504
1505 data = data_low;
1506 column_parity = 0;
1507
1508 for(i=0; i<4; i++) {
1509 line_parity = 0;
1510 for(j=0; j<8; j++) {
1511 line_parity ^= data;
1512 column_parity ^= (data & 1) << j;
1513 *forward_ptr++ = data;
1514 data >>= 1;
1515 }
1516 *forward_ptr++ = line_parity;
1517 if(i == 1)
1518 data = data_hi;
1519 }
1520
1521 for(j=0; j<8; j++) {
1522 *forward_ptr++ = column_parity;
1523 column_parity >>= 1;
1524 }
1525 *forward_ptr = 0;
1526
1527 return 45; //return number of emited bits
1528 }
1529
1530 //====================================================================
1531 // Forward Link send function
1532 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1533 // fwd_bit_count set with number of bits to be sent
1534 //====================================================================
1535 void SendForward(uint8_t fwd_bit_count) {
1536
1537 fwd_write_ptr = forwardLink_data;
1538 fwd_bit_sz = fwd_bit_count;
1539
1540 LED_D_ON();
1541
1542 // Set up FPGA, 125kHz
1543 LFSetupFPGAForADC(95, true);
1544
1545 // force 1st mod pulse (start gap must be longer for 4305)
1546 fwd_bit_sz--; //prepare next bit modulation
1547 fwd_write_ptr++;
1548 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1549 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1550 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1551 SpinDelayUs(16*8); //16 cycles on (8us each)
1552
1553 // now start writting
1554 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1555 if(((*fwd_write_ptr++) & 1) == 1)
1556 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1557 else {
1558 //These timings work for 4469/4269/4305 (with the 55*8 above)
1559 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1560 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1561 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1562 SpinDelayUs(9*8); //16 cycles on (8us each)
1563 }
1564 }
1565 }
1566
1567 void EM4xLogin(uint32_t Password) {
1568
1569 uint8_t fwd_bit_count;
1570
1571 forward_ptr = forwardLink_data;
1572 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1573 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1574
1575 SendForward(fwd_bit_count);
1576
1577 //Wait for command to complete
1578 SpinDelay(20);
1579 }
1580
1581 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1582
1583 uint8_t fwd_bit_count;
1584 uint8_t *dest = BigBuf_get_addr();
1585 uint16_t bufferlength = BigBuf_max_traceLen();
1586 uint32_t i = 0;
1587
1588 // Clear destination buffer before sending the command
1589 BigBuf_Clear_ext(false);
1590
1591 //If password mode do login
1592 if (PwdMode == 1) EM4xLogin(Pwd);
1593
1594 forward_ptr = forwardLink_data;
1595 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1596 fwd_bit_count += Prepare_Addr( Address );
1597
1598 // Connect the A/D to the peak-detected low-frequency path.
1599 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1600 // Now set up the SSC to get the ADC samples that are now streaming at us.
1601 FpgaSetupSsc();
1602
1603 SendForward(fwd_bit_count);
1604
1605 // Now do the acquisition
1606 i = 0;
1607 for(;;) {
1608 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1609 AT91C_BASE_SSC->SSC_THR = 0x43;
1610 }
1611 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1612 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1613 i++;
1614 if (i >= bufferlength) break;
1615 }
1616 }
1617 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1618 cmd_send(CMD_ACK,0,0,0,0,0);
1619 LED_D_OFF();
1620 }
1621
1622 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1623
1624 uint8_t fwd_bit_count;
1625
1626 //If password mode do login
1627 if (PwdMode == 1) EM4xLogin(Pwd);
1628
1629 forward_ptr = forwardLink_data;
1630 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1631 fwd_bit_count += Prepare_Addr( Address );
1632 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1633
1634 SendForward(fwd_bit_count);
1635
1636 //Wait for write to complete
1637 SpinDelay(20);
1638 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1639 LED_D_OFF();
1640 }
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