cvs.zerfleddert.de Git - proxmark3-svn/blob - fpga/fpga.mpf

   1 ;
   2 ; Copyright Model Technology, a  Mentor Graphics
   3 ;  Corporation company 2003, - All rights reserved.
   4 ;
   5 [Library]
   6 std = $MODEL_TECH/../std
   7 ieee = $MODEL_TECH/../ieee
   8 verilog = $MODEL_TECH/../verilog
   9 vital2000 = $MODEL_TECH/../vital2000
  10 std_developerskit = $MODEL_TECH/../std_developerskit
  11 synopsys = $MODEL_TECH/../synopsys
  12 modelsim_lib = $MODEL_TECH/../modelsim_lib
  13
  14
  15 ; VHDL Section
  16 unisim = $MODEL_TECH/../xilinx/vhdl/unisim
  17 simprim = $MODEL_TECH/../xilinx/vhdl/simprim
  18 xilinxcorelib = $MODEL_TECH/../xilinx/vhdl/xilinxcorelib
  19 aim = $MODEL_TECH/../xilinx/vhdl/aim
  20 pls = $MODEL_TECH/../xilinx/vhdl/pls
  21 cpld = $MODEL_TECH/../xilinx/vhdl/cpld
  22
  23 ; Verilog Section
  24 unisims_ver = $MODEL_TECH/../xilinx/verilog/unisims_ver
  25 uni9000_ver = $MODEL_TECH/../xilinx/verilog/uni9000_ver
  26 simprims_ver = $MODEL_TECH/../xilinx/verilog/simprims_ver
  27 xilinxcorelib_ver = $MODEL_TECH/../xilinx/verilog/xilinxcorelib_ver
  28 aim_ver = $MODEL_TECH/../xilinx/verilog/aim_ver
  29 cpld_ver = $MODEL_TECH/../xilinx/verilog/cpld_ver
  30
  31 work = work
  32 [vcom]
  33 ; Turn on VHDL-1993 as the default. Normally is off.
  34 VHDL93 = 1
  35
  36 ; Show source line containing error. Default is off.
  37 ; Show_source = 1
  38
  39 ; Turn off unbound-component warnings. Default is on.
  40 ; Show_Warning1 = 0
  41
  42 ; Turn off process-without-a-wait-statement warnings. Default is on.
  43 ; Show_Warning2 = 0
  44
  45 ; Turn off null-range warnings. Default is on.
  46 ; Show_Warning3 = 0
  47
  48 ; Turn off no-space-in-time-literal warnings. Default is on.
  49 ; Show_Warning4 = 0
  50
  51 ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
  52 ; Show_Warning5 = 0
  53
  54 ; Turn off optimization for IEEE std_logic_1164 package. Default is on.
  55 ; Optimize_1164 = 0
  56
  57 ; Turn on resolving of ambiguous function overloading in favor of the
  58 ; "explicit" function declaration (not the one automatically created by
  59 ; the compiler for each type declaration). Default is off.
  60  Explicit = 1
  61
  62 ; Turn off VITAL compliance checking. Default is checking on.
  63 ; NoVitalCheck = 1
  64
  65 ; Ignore VITAL compliance checking errors. Default is to not ignore.
  66 ; IgnoreVitalErrors = 1
  67
  68 ; Turn off VITAL compliance checking warnings. Default is to show warnings.
  69 ; Show_VitalChecksWarnings = false
  70
  71 ; Turn off "loading..." messages. Default is messages on.
  72 ; Quiet = 1
  73
  74 ; Turn on some limited synthesis rule compliance checking. Checks only:
  75 ;       -- signals used (read) by a process must be in the sensitivity list
  76 ; CheckSynthesis = 1
  77
  78 [vlog]
  79
  80 ; Turn off "loading..." messages. Default is messages on.
  81 ; Quiet = 1
  82
  83 ; Turn on Verilog hazard checking (order-dependent accessing of global vars).
  84 ; Default is off.
  85 ; Hazard = 1
  86
  87 ; Turn on converting regular Verilog identifiers to uppercase. Allows case
  88 ; insensitivity for module names. Default is no conversion.
  89 ; UpCase = 1
  90
  91 ; Turns on incremental compilation of modules
  92 ; Incremental = 1
  93
  94 [vsim]
  95 ; Simulator resolution
  96 ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
  97 Resolution = ps
  98
  99 ; User time unit for run commands
 100 ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
 101 ; unit specified for Resolution. For example, if Resolution is 100ps,
 102 ; then UserTimeUnit defaults to ps.
 103 UserTimeUnit = default
 104
 105 ; Default run length
 106 RunLength = 100
 107
 108 ; Maximum iterations that can be run without advancing simulation time
 109 IterationLimit = 5000
 110
 111 ; Directive to license manager:
 112 ; vhdl          Immediately reserve a VHDL license
 113 ; vlog          Immediately reserve a Verilog license
 114 ; plus          Immediately reserve a VHDL and Verilog license
 115 ; nomgc         Do not look for Mentor Graphics Licenses
 116 ; nomti         Do not look for Model Technology Licenses
 117 ; noqueue       Do not wait in the license queue when a license isn't available
 118 ; License = plus
 119
 120 ; Stop the simulator after an assertion message
 121 ; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
 122 BreakOnAssertion = 3
 123
 124 ; Assertion Message Format
 125 ; %S - Severity Level
 126 ; %R - Report Message
 127 ; %T - Time of assertion
 128 ; %D - Delta
 129 ; %I - Instance or Region pathname (if available)
 130 ; %% - print '%' character
 131 ; AssertionFormat = "** %S: %R\n   Timf: %T  Iteration: %D%I\n"
 132
 133 ; Assertion File - alternate file for storing assertion messages
 134 ; AssertFile = assert.log
 135
 136 ; Default radix for all windows and commands...
 137 ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
 138 DefaultRadix = symbolic
 139
 140 ; VSIM Startup command
 141 ; Startup = do startup.do
 142
 143 ; File for saving command transcript
 144 TranscriptFile = transcript
 145
 146 ; File for saving command history
 147 ;CommandHistory = cmdhist.log
 148
 149 ; Specify whether paths in simulator commands should be described
 150 ; in VHDL or Verilog format. For VHDL, PathSeparator = /
 151 ; for Verilog, PathSeparator = .
 152 PathSeparator = /
 153
 154 ; Specify the dataset separator for fully rooted contexts.
 155 ; The default is ':'. For example, sim:/top
 156 ; Must not be the same character as PathSeparator.
 157 DatasetSeparator = :
 158
 159 ; Disable assertion messages
 160 ; IgnoreNote = 1
 161 ; IgnoreWarning = 1
 162 ; IgnoreError = 1
 163 ; IgnoreFailure = 1
 164
 165 ; Default force kind. May be freeze, drive, or deposit
 166 ; or in other terms, fixed, wired or charged.
 167 ; DefaultForceKind = freeze
 168
 169 ; If zero, open files when elaborated
 170 ; else open files on first read or write
 171 ; DelayFileOpen = 0
 172
 173 ; Control VHDL files opened for write
 174 ;   0 = Buffered, 1 = Unbuffered
 175 UnbufferedOutput = 0
 176
 177 ; Control number of VHDL files open concurrently
 178 ;   This number should always be less then the
 179 ;   current ulimit setting for max file descriptors
 180 ;   0 = unlimited
 181 ConcurrentFileLimit = 40
 182
 183 ; This controls the number of hierarchical regions displayed as
 184 ; part of a signal name shown in the waveform window.  The default
 185 ; value or a value of zero tells VSIM to display the full name.
 186 ; WaveSignalNameWidth = 0
 187
 188 ; Turn off warnings from the std_logic_arith, std_logic_unsigned
 189 ; and std_logic_signed packages.
 190 ; StdArithNoWarnings = 1
 191
 192 ; Turn off warnings from the IEEE numeric_std and numeric_bit
 193 ; packages.
 194 ; NumericStdNoWarnings = 1
 195
 196 ; Control the format of a generate statement label. Don't quote it.
 197 ; GenerateFormat = %s__%d
 198
 199 ; Specify whether checkpoint files should be compressed.
 200 ; The default is to be compressed.
 201 ; CheckpointCompressMode = 0
 202
 203 ; List of dynamically loaded objects for Verilog PLI applications
 204 ; Veriuser = veriuser.sl
 205
 206 [lmc]
 207 [Project]
 208 Project_Version = 5
 209 Project_DefaultLib = work
 210 Project_SortMethod = unused
 211 Project_Files_Count = 13
 212 Project_File_0 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/fpga_tb.v
 213 Project_File_P_0 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1179836462 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 2 dont_compile 0
 214 Project_File_1 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/hi_simulate.v
 215 Project_File_P_1 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1225963633 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 6 dont_compile 0
 216 Project_File_2 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/testbed_hi_simulate.v
 217 Project_File_P_2 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1225964050 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 12 dont_compile 0
 218 Project_File_3 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/fpga.v
 219 Project_File_P_3 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1207888760 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 1 dont_compile 0
 220 Project_File_4 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/hi_read_tx.v
 221 Project_File_P_4 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1225960972 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 5 dont_compile 0
 222 Project_File_5 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/testbed_hi_read_tx.v
 223 Project_File_P_5 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1225962515 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 11 dont_compile 0
 224 Project_File_6 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/hi_iso14443a.v
 225 Project_File_P_6 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1207889732 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 3 dont_compile 0
 226 Project_File_7 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/lo_simulate.v
 227 Project_File_P_7 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1179836462 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 8 dont_compile 0
 228 Project_File_8 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/lo_read.v
 229 Project_File_P_8 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1225797126 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 7 dont_compile 0
 230 Project_File_9 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/util.v
 231 Project_File_P_9 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1179836462 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 0 dont_compile 0
 232 Project_File_10 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/testbed_lo_read.v
 233 Project_File_P_10 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1225960239 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 9 dont_compile 0
 234 Project_File_11 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/testbed_lo_simulate.v
 235 Project_File_P_11 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1225960231 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 10 dont_compile 0
 236 Project_File_12 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/hi_read_rx_xcorr.v
 237 Project_File_P_12 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1179836462 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 4 dont_compile 0
 238 Project_Sim_Count = 0
 239 Project_Folder_Count = 0