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[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "../include/proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "../common/crc16.h"
15 #include "../common/lfdemod.h"
16 #include "string.h"
17 #include "crapto1.h"
18 #include "mifareutil.h"
19 #include "../include/hitag2.h"
20
21 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
22 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
23 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
24 // T0 = TIMER_CLOCK1 / 125000 = 192
25 #define T0 192
26
27 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
28 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
29
30 void LFSetupFPGAForADC(int divisor, bool lf_field)
31 {
32 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
33 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
34 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
35 else if (divisor == 0)
36 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
37 else
38 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
39
40 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
41
42 // Connect the A/D to the peak-detected low-frequency path.
43 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
44
45 // Give it a bit of time for the resonant antenna to settle.
46 SpinDelay(150);
47
48 // Now set up the SSC to get the ADC samples that are now streaming at us.
49 FpgaSetupSsc();
50 }
51
52 void AcquireRawAdcSamples125k(int divisor)
53 {
54 LFSetupFPGAForADC(divisor, true);
55 DoAcquisition125k();
56 }
57
58 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
59 {
60 LFSetupFPGAForADC(divisor, false);
61 DoAcquisition125k_threshold(trigger_threshold);
62 }
63
64 // split into two routines so we can avoid timing issues after sending commands //
65 void DoAcquisition125k_internal(int trigger_threshold, bool silent)
66 {
67 uint8_t *dest = get_bigbufptr_recvrespbuf();
68 uint16_t i = 0;
69 memset(dest, 0x00, FREE_BUFFER_SIZE);
70
71 for(;;) {
72 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
73 AT91C_BASE_SSC->SSC_THR = 0x43;
74 LED_D_ON();
75 }
76 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
77 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
78 LED_D_OFF();
79 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
80 continue;
81 else
82 trigger_threshold = -1;
83 if (++i >= FREE_BUFFER_SIZE) break;
84 }
85 }
86 if (!silent){
87 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
88 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
89 }
90 }
91 void DoAcquisition125k_threshold(int trigger_threshold) {
92 DoAcquisition125k_internal(trigger_threshold, true);
93 }
94 void DoAcquisition125k() {
95 DoAcquisition125k_internal(-1, true);
96 }
97
98 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
99 {
100 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
101
102 /* Make sure the tag is reset */
103 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
104 SpinDelay(2500);
105
106 int divisor = 95; // 125 KHz
107 // see if 'h' was specified
108 if (command[strlen((char *) command) - 1] == 'h')
109 divisor = 88; // 134.8 KHz
110
111 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
112 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
113 // Give it a bit of time for the resonant antenna to settle.
114 SpinDelay(2000);
115
116 // Now set up the SSC to get the ADC samples that are now streaming at us.
117 FpgaSetupSsc();
118
119 // now modulate the reader field
120 while(*command != '\0' && *command != ' ') {
121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
122 LED_D_OFF();
123 SpinDelayUs(delay_off);
124 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
125
126 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
127 LED_D_ON();
128 if(*(command++) == '0')
129 SpinDelayUs(period_0);
130 else
131 SpinDelayUs(period_1);
132 }
133 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
134 LED_D_OFF();
135 SpinDelayUs(delay_off);
136 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
137 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
138
139 // now do the read
140 DoAcquisition125k(-1);
141 }
142
143 /* blank r/w tag data stream
144 ...0000000000000000 01111111
145 1010101010101010101010101010101010101010101010101010101010101010
146 0011010010100001
147 01111111
148 101010101010101[0]000...
149
150 [5555fe852c5555555555555555fe0000]
151 */
152 void ReadTItag(void)
153 {
154 // some hardcoded initial params
155 // when we read a TI tag we sample the zerocross line at 2Mhz
156 // TI tags modulate a 1 as 16 cycles of 123.2Khz
157 // TI tags modulate a 0 as 16 cycles of 134.2Khz
158 #define FSAMPLE 2000000
159 #define FREQLO 123200
160 #define FREQHI 134200
161
162 signed char *dest = (signed char *)BigBuf;
163 int n = sizeof(BigBuf);
164 // int *dest = GraphBuffer;
165 // int n = GraphTraceLen;
166
167 // 128 bit shift register [shift3:shift2:shift1:shift0]
168 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
169
170 int i, cycles=0, samples=0;
171 // how many sample points fit in 16 cycles of each frequency
172 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
173 // when to tell if we're close enough to one freq or another
174 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
175
176 // TI tags charge at 134.2Khz
177 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
178 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
179
180 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
181 // connects to SSP_DIN and the SSP_DOUT logic level controls
182 // whether we're modulating the antenna (high)
183 // or listening to the antenna (low)
184 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
185
186 // get TI tag data into the buffer
187 AcquireTiType();
188
189 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
190
191 for (i=0; i<n-1; i++) {
192 // count cycles by looking for lo to hi zero crossings
193 if ( (dest[i]<0) && (dest[i+1]>0) ) {
194 cycles++;
195 // after 16 cycles, measure the frequency
196 if (cycles>15) {
197 cycles=0;
198 samples=i-samples; // number of samples in these 16 cycles
199
200 // TI bits are coming to us lsb first so shift them
201 // right through our 128 bit right shift register
202 shift0 = (shift0>>1) | (shift1 << 31);
203 shift1 = (shift1>>1) | (shift2 << 31);
204 shift2 = (shift2>>1) | (shift3 << 31);
205 shift3 >>= 1;
206
207 // check if the cycles fall close to the number
208 // expected for either the low or high frequency
209 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
210 // low frequency represents a 1
211 shift3 |= (1<<31);
212 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
213 // high frequency represents a 0
214 } else {
215 // probably detected a gay waveform or noise
216 // use this as gaydar or discard shift register and start again
217 shift3 = shift2 = shift1 = shift0 = 0;
218 }
219 samples = i;
220
221 // for each bit we receive, test if we've detected a valid tag
222
223 // if we see 17 zeroes followed by 6 ones, we might have a tag
224 // remember the bits are backwards
225 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
226 // if start and end bytes match, we have a tag so break out of the loop
227 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
228 cycles = 0xF0B; //use this as a flag (ugly but whatever)
229 break;
230 }
231 }
232 }
233 }
234 }
235
236 // if flag is set we have a tag
237 if (cycles!=0xF0B) {
238 DbpString("Info: No valid tag detected.");
239 } else {
240 // put 64 bit data into shift1 and shift0
241 shift0 = (shift0>>24) | (shift1 << 8);
242 shift1 = (shift1>>24) | (shift2 << 8);
243
244 // align 16 bit crc into lower half of shift2
245 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
246
247 // if r/w tag, check ident match
248 if ( shift3&(1<<15) ) {
249 DbpString("Info: TI tag is rewriteable");
250 // only 15 bits compare, last bit of ident is not valid
251 if ( ((shift3>>16)^shift0)&0x7fff ) {
252 DbpString("Error: Ident mismatch!");
253 } else {
254 DbpString("Info: TI tag ident is valid");
255 }
256 } else {
257 DbpString("Info: TI tag is readonly");
258 }
259
260 // WARNING the order of the bytes in which we calc crc below needs checking
261 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
262 // bytes in reverse or something
263 // calculate CRC
264 uint32_t crc=0;
265
266 crc = update_crc16(crc, (shift0)&0xff);
267 crc = update_crc16(crc, (shift0>>8)&0xff);
268 crc = update_crc16(crc, (shift0>>16)&0xff);
269 crc = update_crc16(crc, (shift0>>24)&0xff);
270 crc = update_crc16(crc, (shift1)&0xff);
271 crc = update_crc16(crc, (shift1>>8)&0xff);
272 crc = update_crc16(crc, (shift1>>16)&0xff);
273 crc = update_crc16(crc, (shift1>>24)&0xff);
274
275 Dbprintf("Info: Tag data: %x%08x, crc=%x",
276 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
277 if (crc != (shift2&0xffff)) {
278 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
279 } else {
280 DbpString("Info: CRC is good");
281 }
282 }
283 }
284
285 void WriteTIbyte(uint8_t b)
286 {
287 int i = 0;
288
289 // modulate 8 bits out to the antenna
290 for (i=0; i<8; i++)
291 {
292 if (b&(1<<i)) {
293 // stop modulating antenna
294 SHORT_COIL();
295 SpinDelayUs(1000);
296 // modulate antenna
297 OPEN_COIL();
298 SpinDelayUs(1000);
299 } else {
300 // stop modulating antenna
301 SHORT_COIL();
302 SpinDelayUs(300);
303 // modulate antenna
304 OPEN_COIL();
305 SpinDelayUs(1700);
306 }
307 }
308 }
309
310 void AcquireTiType(void)
311 {
312 int i, j, n;
313 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
314 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
315 #define TIBUFLEN 1250
316
317 // clear buffer
318 memset(BigBuf,0,sizeof(BigBuf));
319
320 // Set up the synchronous serial port
321 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
322 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
323
324 // steal this pin from the SSP and use it to control the modulation
325 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
326 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
327
328 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
329 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
330
331 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
332 // 48/2 = 24 MHz clock must be divided by 12
333 AT91C_BASE_SSC->SSC_CMR = 12;
334
335 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
336 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
337 AT91C_BASE_SSC->SSC_TCMR = 0;
338 AT91C_BASE_SSC->SSC_TFMR = 0;
339
340 LED_D_ON();
341
342 // modulate antenna
343 HIGH(GPIO_SSC_DOUT);
344
345 // Charge TI tag for 50ms.
346 SpinDelay(50);
347
348 // stop modulating antenna and listen
349 LOW(GPIO_SSC_DOUT);
350
351 LED_D_OFF();
352
353 i = 0;
354 for(;;) {
355 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
356 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
357 i++; if(i >= TIBUFLEN) break;
358 }
359 WDT_HIT();
360 }
361
362 // return stolen pin to SSP
363 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
364 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
365
366 char *dest = (char *)BigBuf;
367 n = TIBUFLEN*32;
368 // unpack buffer
369 for (i=TIBUFLEN-1; i>=0; i--) {
370 for (j=0; j<32; j++) {
371 if(BigBuf[i] & (1 << j)) {
372 dest[--n] = 1;
373 } else {
374 dest[--n] = -1;
375 }
376 }
377 }
378 }
379
380 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
381 // if crc provided, it will be written with the data verbatim (even if bogus)
382 // if not provided a valid crc will be computed from the data and written.
383 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
384 {
385 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
386 if(crc == 0) {
387 crc = update_crc16(crc, (idlo)&0xff);
388 crc = update_crc16(crc, (idlo>>8)&0xff);
389 crc = update_crc16(crc, (idlo>>16)&0xff);
390 crc = update_crc16(crc, (idlo>>24)&0xff);
391 crc = update_crc16(crc, (idhi)&0xff);
392 crc = update_crc16(crc, (idhi>>8)&0xff);
393 crc = update_crc16(crc, (idhi>>16)&0xff);
394 crc = update_crc16(crc, (idhi>>24)&0xff);
395 }
396 Dbprintf("Writing to tag: %x%08x, crc=%x",
397 (unsigned int) idhi, (unsigned int) idlo, crc);
398
399 // TI tags charge at 134.2Khz
400 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
401 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
402 // connects to SSP_DIN and the SSP_DOUT logic level controls
403 // whether we're modulating the antenna (high)
404 // or listening to the antenna (low)
405 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
406 LED_A_ON();
407
408 // steal this pin from the SSP and use it to control the modulation
409 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
410 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
411
412 // writing algorithm:
413 // a high bit consists of a field off for 1ms and field on for 1ms
414 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
415 // initiate a charge time of 50ms (field on) then immediately start writing bits
416 // start by writing 0xBB (keyword) and 0xEB (password)
417 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
418 // finally end with 0x0300 (write frame)
419 // all data is sent lsb firts
420 // finish with 15ms programming time
421
422 // modulate antenna
423 HIGH(GPIO_SSC_DOUT);
424 SpinDelay(50); // charge time
425
426 WriteTIbyte(0xbb); // keyword
427 WriteTIbyte(0xeb); // password
428 WriteTIbyte( (idlo )&0xff );
429 WriteTIbyte( (idlo>>8 )&0xff );
430 WriteTIbyte( (idlo>>16)&0xff );
431 WriteTIbyte( (idlo>>24)&0xff );
432 WriteTIbyte( (idhi )&0xff );
433 WriteTIbyte( (idhi>>8 )&0xff );
434 WriteTIbyte( (idhi>>16)&0xff );
435 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
436 WriteTIbyte( (crc )&0xff ); // crc lo
437 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
438 WriteTIbyte(0x00); // write frame lo
439 WriteTIbyte(0x03); // write frame hi
440 HIGH(GPIO_SSC_DOUT);
441 SpinDelay(50); // programming time
442
443 LED_A_OFF();
444
445 // get TI tag data into the buffer
446 AcquireTiType();
447
448 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
449 DbpString("Now use tiread to check");
450 }
451
452
453
454 // PIO_CODR = Clear Output Data Register
455 // PIO_SODR = Set Output Data Register
456 //#define LOW(x) AT91C_BASE_PIOA->PIO_CODR = (x)
457 //#define HIGH(x) AT91C_BASE_PIOA->PIO_SODR = (x)
458 void SimulateTagLowFrequency( uint16_t period, uint32_t gap, uint8_t ledcontrol)
459 {
460 LED_D_ON();
461
462 uint16_t i = 0;
463 uint8_t send = 0;
464
465 //int overflow = 0;
466 uint8_t *buf = (uint8_t *)BigBuf;
467
468 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
469 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
470 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
471 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
472 RELAY_OFF();
473
474 // Configure output pin that is connected to the FPGA (for modulating)
475 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
476 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
477
478 SHORT_COIL();
479
480 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
481 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
482
483 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames
484 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
485 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
486
487 // Disable timer during configuration
488 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
489
490 // Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
491 // external trigger rising edge, load RA on rising edge of TIOA.
492 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_RISING | AT91C_TC_ABETRG | AT91C_TC_LDRA_RISING;
493
494 // Enable and reset counter
495 //AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
496 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
497
498 while(!BUTTON_PRESS()) {
499 WDT_HIT();
500
501 // Receive frame, watch for at most T0*EOF periods
502 while (AT91C_BASE_TC1->TC_CV < T0 * 55) {
503
504 // Check if rising edge in modulation is detected
505 if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
506 // Retrieve the new timing values
507 //int ra = (AT91C_BASE_TC1->TC_RA/T0) + overflow;
508 //Dbprintf("Timing value - %d %d", ra, overflow);
509 //overflow = 0;
510
511 // Reset timer every frame, we have to capture the last edge for timing
512 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
513 send = 1;
514
515 LED_B_ON();
516 }
517 }
518
519 if ( send ) {
520 // Disable timer 1 with external trigger to avoid triggers during our own modulation
521 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
522
523 // Wait for HITAG_T_WAIT_1 carrier periods after the last reader bit,
524 // not that since the clock counts since the rising edge, but T_Wait1 is
525 // with respect to the falling edge, we need to wait actually (T_Wait1 - T_Low)
526 // periods. The gap time T_Low varies (4..10). All timer values are in
527 // terms of T0 units
528 while(AT91C_BASE_TC0->TC_CV < T0 * 16 );
529
530 // datat kommer in som 1 bit för varje position i arrayn
531 for(i = 0; i < period; ++i) {
532
533 // Reset clock for the next bit
534 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
535
536 if ( buf[i] > 0 )
537 HIGH(GPIO_SSC_DOUT);
538 else
539 LOW(GPIO_SSC_DOUT);
540
541 while(AT91C_BASE_TC0->TC_CV < T0 * 1 );
542 }
543 // Drop modulation
544 LOW(GPIO_SSC_DOUT);
545
546 // Enable and reset external trigger in timer for capturing future frames
547 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
548 LED_B_OFF();
549 }
550
551 send = 0;
552
553 // Save the timer overflow, will be 0 when frame was received
554 //overflow += (AT91C_BASE_TC1->TC_CV/T0);
555
556 // Reset the timer to restart while-loop that receives frames
557 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
558 }
559
560 LED_B_OFF();
561 LED_D_OFF();
562 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
563 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
564 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
565
566 DbpString("Sim Stopped");
567 }
568
569
570 void SimulateTagLowFrequencyA(int len, int gap)
571 {
572 //Dbprintf("LEN %d || Gap %d",len, gap);
573
574 uint8_t *buf = (uint8_t *)BigBuf;
575
576 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
577 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
578 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_TOGGLE_MODE); // new izsh toggle mode!
579
580 // Connect the A/D to the peak-detected low-frequency path.
581 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
582
583 // Now set up the SSC to get the ADC samples that are now streaming at us.
584 FpgaSetupSsc();
585 SpinDelay(5);
586
587 AT91C_BASE_SSC->SSC_THR = 0x00;
588
589 int i = 0;
590 while(!BUTTON_PRESS()) {
591 WDT_HIT();
592 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
593
594 if ( buf[i] > 0 )
595 AT91C_BASE_SSC->SSC_THR = 0x43;
596 else
597 AT91C_BASE_SSC->SSC_THR = 0x00;
598
599 ++i;
600 LED_A_ON();
601 if (i >= len){
602 i = 0;
603 }
604 }
605
606 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
607 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
608 (void)r;
609 LED_A_OFF();
610 }
611 }
612 DbpString("lf simulate stopped");
613 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
614 }
615
616 #define DEBUG_FRAME_CONTENTS 1
617 void SimulateTagLowFrequencyBidir(int divisor, int t0)
618 {
619 }
620
621 // compose fc/8 fc/10 waveform
622 static void fc(int c, uint16_t *n) {
623 uint8_t *dest = (uint8_t *)BigBuf;
624 int idx;
625
626 // for when we want an fc8 pattern every 4 logical bits
627 if(c==0) {
628 dest[((*n)++)]=1;
629 dest[((*n)++)]=1;
630 dest[((*n)++)]=0;
631 dest[((*n)++)]=0;
632 dest[((*n)++)]=0;
633 dest[((*n)++)]=0;
634 dest[((*n)++)]=0;
635 dest[((*n)++)]=0;
636 }
637 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
638 if(c==8) {
639 for (idx=0; idx<6; idx++) {
640 dest[((*n)++)]=1;
641 dest[((*n)++)]=1;
642 dest[((*n)++)]=0;
643 dest[((*n)++)]=0;
644 dest[((*n)++)]=0;
645 dest[((*n)++)]=0;
646 dest[((*n)++)]=0;
647 dest[((*n)++)]=0;
648 }
649 }
650
651 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
652 if(c==10) {
653 for (idx=0; idx<5; idx++) {
654 dest[((*n)++)]=1;
655 dest[((*n)++)]=1;
656 dest[((*n)++)]=1;
657 dest[((*n)++)]=0;
658 dest[((*n)++)]=0;
659 dest[((*n)++)]=0;
660 dest[((*n)++)]=0;
661 dest[((*n)++)]=0;
662 dest[((*n)++)]=0;
663 dest[((*n)++)]=0;
664 }
665 }
666 }
667
668 // prepare a waveform pattern in the buffer based on the ID given then
669 // simulate a HID tag until the button is pressed
670 void CmdHIDsimTAG(int hi, int lo, uint8_t ledcontrol)
671 {
672 uint16_t n=0, i=0;
673 /*
674 HID tag bitstream format
675 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
676 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
677 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
678 A fc8 is inserted before every 4 bits
679 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
680 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
681 */
682
683 if (hi>0xFFF) {
684 DbpString("Tags can only have 44 bits.");
685 return;
686 }
687 fc(0,&n);
688 // special start of frame marker containing invalid bit sequences
689 fc(8, &n); fc(8, &n); // invalid
690 fc(8, &n); fc(10, &n); // logical 0
691 fc(10, &n); fc(10, &n); // invalid
692 fc(8, &n); fc(10, &n); // logical 0
693
694 WDT_HIT();
695 // manchester encode bits 43 to 32
696 for (i=11; i>=0; i--) {
697 if ((i%4)==3) fc(0,&n);
698 if ((hi>>i)&1) {
699 fc(10, &n); fc(8, &n); // low-high transition
700 } else {
701 fc(8, &n); fc(10, &n); // high-low transition
702 }
703 }
704
705 WDT_HIT();
706 // manchester encode bits 31 to 0
707 for (i=31; i>=0; i--) {
708 if ((i%4)==3) fc(0,&n);
709 if ((lo>>i)&1) {
710 fc(10, &n); fc(8, &n); // low-high transition
711 } else {
712 fc(8, &n); fc(10, &n); // high-low transition
713 }
714 }
715
716 if (ledcontrol)
717 LED_A_ON();
718
719 SimulateTagLowFrequency(n, 0, ledcontrol);
720
721 if (ledcontrol)
722 LED_A_OFF();
723 }
724
725 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
726 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
727 {
728 uint8_t *dest = get_bigbufptr_recvrespbuf();
729
730 size_t size=0; //, found=0;
731 uint32_t hi2=0, hi=0, lo=0;
732
733 // Configure to go in 125Khz listen mode
734 LFSetupFPGAForADC(0, true);
735
736 while(!BUTTON_PRESS()) {
737
738 WDT_HIT();
739 if (ledcontrol) LED_A_ON();
740
741 DoAcquisition125k_internal(-1,true);
742 size = sizeof(BigBuf);
743 if (size < 2000) continue;
744 // FSK demodulator
745
746 int bitLen = HIDdemodFSK(dest,size,&hi2,&hi,&lo);
747
748 WDT_HIT();
749
750 if (bitLen>0 && lo>0){
751 // final loop, go over previously decoded manchester data and decode into usable tag ID
752 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
753 if (hi2 != 0){ //extra large HID tags
754 Dbprintf("TAG ID: %x%08x%08x (%d)",
755 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
756 }else { //standard HID tags <38 bits
757 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
758 uint8_t bitlen = 0;
759 uint32_t fc = 0;
760 uint32_t cardnum = 0;
761 if (((hi>>5)&1)==1){//if bit 38 is set then < 37 bit format is used
762 uint32_t lo2=0;
763 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
764 uint8_t idx3 = 1;
765 while(lo2>1){ //find last bit set to 1 (format len bit)
766 lo2=lo2>>1;
767 idx3++;
768 }
769 bitlen =idx3+19;
770 fc =0;
771 cardnum=0;
772 if(bitlen==26){
773 cardnum = (lo>>1)&0xFFFF;
774 fc = (lo>>17)&0xFF;
775 }
776 if(bitlen==37){
777 cardnum = (lo>>1)&0x7FFFF;
778 fc = ((hi&0xF)<<12)|(lo>>20);
779 }
780 if(bitlen==34){
781 cardnum = (lo>>1)&0xFFFF;
782 fc= ((hi&1)<<15)|(lo>>17);
783 }
784 if(bitlen==35){
785 cardnum = (lo>>1)&0xFFFFF;
786 fc = ((hi&1)<<11)|(lo>>21);
787 }
788 }
789 else { //if bit 38 is not set then 37 bit format is used
790 bitlen= 37;
791 fc =0;
792 cardnum=0;
793 if(bitlen==37){
794 cardnum = (lo>>1)&0x7FFFF;
795 fc = ((hi&0xF)<<12)|(lo>>20);
796 }
797 }
798 //Dbprintf("TAG ID: %x%08x (%d)",
799 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
800 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
801 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
802 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
803 }
804 if (findone){
805 if (ledcontrol) LED_A_OFF();
806 return;
807 }
808 // reset
809 hi2 = hi = lo = 0;
810 }
811 WDT_HIT();
812 //SpinDelay(50);
813 }
814 DbpString("Stopped");
815 if (ledcontrol) LED_A_OFF();
816 }
817
818 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
819 {
820 uint8_t *dest = (uint8_t *)BigBuf;
821
822 size_t size=0; //, found=0;
823 uint32_t bitLen=0;
824 int clk=0, invert=0, errCnt=0;
825 uint64_t lo=0;
826 // Configure to go in 125Khz listen mode
827 LFSetupFPGAForADC(95, true);
828
829 while(!BUTTON_PRESS()) {
830
831 WDT_HIT();
832 if (ledcontrol) LED_A_ON();
833
834 DoAcquisition125k_internal(-1,true);
835 size = sizeof(BigBuf);
836 if (size < 2000) continue;
837 // FSK demodulator
838 //int askmandemod(uint8_t *BinStream,uint32_t *BitLen,int *clk, int *invert);
839 bitLen=size;
840 //Dbprintf("DEBUG: Buffer got");
841 errCnt = askmandemod(dest,&bitLen,&clk,&invert); //HIDdemodFSK(dest,size,&hi2,&hi,&lo);
842 //Dbprintf("DEBUG: ASK Got");
843 WDT_HIT();
844
845 if (errCnt>=0){
846 lo = Em410xDecode(dest,bitLen);
847 //Dbprintf("DEBUG: EM GOT");
848 //printEM410x(lo);
849 if (lo>0){
850 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",(uint32_t)(lo>>32),(uint32_t)lo,(uint32_t)(lo&0xFFFF),(uint32_t)((lo>>16LL) & 0xFF),(uint32_t)(lo & 0xFFFFFF));
851 }
852 if (findone){
853 if (ledcontrol) LED_A_OFF();
854 return;
855 }
856 } else {
857 //Dbprintf("DEBUG: No Tag");
858 }
859 WDT_HIT();
860 lo = 0;
861 clk=0;
862 invert=0;
863 errCnt=0;
864 size=0;
865 //SpinDelay(50);
866 }
867 DbpString("Stopped");
868 if (ledcontrol) LED_A_OFF();
869 }
870
871 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
872 {
873 uint8_t *dest = (uint8_t *)BigBuf;
874 size_t size=0;
875 int idx=0;
876 uint32_t code=0, code2=0;
877 uint8_t version=0;
878 uint8_t facilitycode=0;
879 uint16_t number=0;
880 // Configure to go in 125Khz listen mode
881 LFSetupFPGAForADC(0, true);
882
883 while(!BUTTON_PRESS()) {
884
885 WDT_HIT();
886
887 if (ledcontrol) LED_A_ON();
888
889 DoAcquisition125k_internal(-1,true);
890 size = sizeof(BigBuf);
891 //make sure buffer has data
892 if (size < 2000) continue;
893 //fskdemod and get start index
894 WDT_HIT();
895 idx = IOdemodFSK(dest,size);
896 if (idx>0){
897 //valid tag found
898
899 //Index map
900 //0 10 20 30 40 50 60
901 //| | | | | | |
902 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
903 //-----------------------------------------------------------------------------
904 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
905 //
906 //XSF(version)facility:codeone+codetwo
907 //Handle the data
908 if(findone){ //only print binary if we are doing one
909 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
910 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
911 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
912 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
913 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
914 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
915 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
916 }
917 code = bytebits_to_byte(dest+idx,32);
918 code2 = bytebits_to_byte(dest+idx+32,32);
919 version = bytebits_to_byte(dest+idx+27,8); //14,4
920 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
921 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
922
923 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
924 // if we're only looking for one tag
925 if (findone){
926 if (ledcontrol) LED_A_OFF();
927 return;
928 }
929 code=code2=0;
930 version=facilitycode=0;
931 number=0;
932 idx=0;
933 }
934 WDT_HIT();
935 }
936 DbpString("Stopped");
937 if (ledcontrol) LED_A_OFF();
938 }
939
940 /*------------------------------
941 * T5555/T5557/T5567 routines
942 *------------------------------
943 */
944
945 /* T55x7 configuration register definitions */
946 #define T55x7_POR_DELAY 0x00000001
947 #define T55x7_ST_TERMINATOR 0x00000008
948 #define T55x7_PWD 0x00000010
949 #define T55x7_MAXBLOCK_SHIFT 5
950 #define T55x7_AOR 0x00000200
951 #define T55x7_PSKCF_RF_2 0
952 #define T55x7_PSKCF_RF_4 0x00000400
953 #define T55x7_PSKCF_RF_8 0x00000800
954 #define T55x7_MODULATION_DIRECT 0
955 #define T55x7_MODULATION_PSK1 0x00001000
956 #define T55x7_MODULATION_PSK2 0x00002000
957 #define T55x7_MODULATION_PSK3 0x00003000
958 #define T55x7_MODULATION_FSK1 0x00004000
959 #define T55x7_MODULATION_FSK2 0x00005000
960 #define T55x7_MODULATION_FSK1a 0x00006000
961 #define T55x7_MODULATION_FSK2a 0x00007000
962 #define T55x7_MODULATION_MANCHESTER 0x00008000
963 #define T55x7_MODULATION_BIPHASE 0x00010000
964 #define T55x7_BITRATE_RF_8 0
965 #define T55x7_BITRATE_RF_16 0x00040000
966 #define T55x7_BITRATE_RF_32 0x00080000
967 #define T55x7_BITRATE_RF_40 0x000C0000
968 #define T55x7_BITRATE_RF_50 0x00100000
969 #define T55x7_BITRATE_RF_64 0x00140000
970 #define T55x7_BITRATE_RF_100 0x00180000
971 #define T55x7_BITRATE_RF_128 0x001C0000
972
973 /* T5555 (Q5) configuration register definitions */
974 #define T5555_ST_TERMINATOR 0x00000001
975 #define T5555_MAXBLOCK_SHIFT 0x00000001
976 #define T5555_MODULATION_MANCHESTER 0
977 #define T5555_MODULATION_PSK1 0x00000010
978 #define T5555_MODULATION_PSK2 0x00000020
979 #define T5555_MODULATION_PSK3 0x00000030
980 #define T5555_MODULATION_FSK1 0x00000040
981 #define T5555_MODULATION_FSK2 0x00000050
982 #define T5555_MODULATION_BIPHASE 0x00000060
983 #define T5555_MODULATION_DIRECT 0x00000070
984 #define T5555_INVERT_OUTPUT 0x00000080
985 #define T5555_PSK_RF_2 0
986 #define T5555_PSK_RF_4 0x00000100
987 #define T5555_PSK_RF_8 0x00000200
988 #define T5555_USE_PWD 0x00000400
989 #define T5555_USE_AOR 0x00000800
990 #define T5555_BITRATE_SHIFT 12
991 #define T5555_FAST_WRITE 0x00004000
992 #define T5555_PAGE_SELECT 0x00008000
993
994 /*
995 * Relevant times in microsecond
996 * To compensate antenna falling times shorten the write times
997 * and enlarge the gap ones.
998 */
999 #define START_GAP 30*8 // 10 - 50fc 250
1000 #define WRITE_GAP 20*8 // 8 - 30fc
1001 #define WRITE_0 24*8 // 16 - 31fc 24fc 192
1002 #define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
1003
1004 // VALUES TAKEN FROM EM4x function: SendForward
1005 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1006 // WRITE_GAP = 128; (16*8)
1007 // WRITE_1 = 256 32*8; (32*8)
1008
1009 // These timings work for 4469/4269/4305 (with the 55*8 above)
1010 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1011
1012 #define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
1013
1014 // Write one bit to card
1015 void T55xxWriteBit(int bit)
1016 {
1017 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1018 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1019 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1020 if (!bit)
1021 SpinDelayUs(WRITE_0);
1022 else
1023 SpinDelayUs(WRITE_1);
1024 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1025 SpinDelayUs(WRITE_GAP);
1026 }
1027
1028 // Write one card block in page 0, no lock
1029 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1030 {
1031 uint32_t i = 0;
1032
1033 // Set up FPGA, 125kHz
1034 // Wait for config.. (192+8190xPOW)x8 == 67ms
1035 LFSetupFPGAForADC(0, true);
1036
1037 // Now start writting
1038 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1039 SpinDelayUs(START_GAP);
1040
1041 // Opcode
1042 T55xxWriteBit(1);
1043 T55xxWriteBit(0); //Page 0
1044 if (PwdMode == 1){
1045 // Pwd
1046 for (i = 0x80000000; i != 0; i >>= 1)
1047 T55xxWriteBit(Pwd & i);
1048 }
1049 // Lock bit
1050 T55xxWriteBit(0);
1051
1052 // Data
1053 for (i = 0x80000000; i != 0; i >>= 1)
1054 T55xxWriteBit(Data & i);
1055
1056 // Block
1057 for (i = 0x04; i != 0; i >>= 1)
1058 T55xxWriteBit(Block & i);
1059
1060 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1061 // so wait a little more)
1062 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1063 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1064 SpinDelay(20);
1065 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1066 }
1067
1068 // Read one card block in page 0
1069 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1070 {
1071 uint8_t *dest = get_bigbufptr_recvrespbuf();
1072 uint16_t bufferlength = T55xx_SAMPLES_SIZE;
1073 uint32_t i = 0;
1074
1075 // Clear destination buffer before sending the command 0x80 = average.
1076 memset(dest, 0x80, bufferlength);
1077
1078 // Set up FPGA, 125kHz
1079 // Wait for config.. (192+8190xPOW)x8 == 67ms
1080 LFSetupFPGAForADC(0, true);
1081
1082 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1083 SpinDelayUs(START_GAP);
1084
1085 // Opcode
1086 T55xxWriteBit(1);
1087 T55xxWriteBit(0); //Page 0
1088 if (PwdMode == 1){
1089 // Pwd
1090 for (i = 0x80000000; i != 0; i >>= 1)
1091 T55xxWriteBit(Pwd & i);
1092 }
1093 // Lock bit
1094 T55xxWriteBit(0);
1095 // Block
1096 for (i = 0x04; i != 0; i >>= 1)
1097 T55xxWriteBit(Block & i);
1098
1099 // Turn field on to read the response
1100 TurnReadLFOn();
1101
1102 // Now do the acquisition
1103 i = 0;
1104 for(;;) {
1105 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1106 AT91C_BASE_SSC->SSC_THR = 0x43;
1107 //AT91C_BASE_SSC->SSC_THR = 0xff;
1108 LED_D_ON();
1109 }
1110 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1111 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1112 ++i;
1113 LED_D_OFF();
1114 if (i >= bufferlength) break;
1115 }
1116 }
1117
1118 cmd_send(CMD_ACK,0,0,0,0,0);
1119 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1120 LED_D_OFF();
1121 }
1122
1123 // Read card traceability data (page 1)
1124 void T55xxReadTrace(void){
1125 uint8_t *dest = get_bigbufptr_recvrespbuf();
1126 uint16_t bufferlength = T55xx_SAMPLES_SIZE;
1127 uint32_t i = 0;
1128
1129 // Clear destination buffer before sending the command 0x80 = average
1130 memset(dest, 0x80, bufferlength);
1131
1132 LFSetupFPGAForADC(0, true);
1133
1134 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1135 SpinDelayUs(START_GAP);
1136
1137 // Opcode
1138 T55xxWriteBit(1);
1139 T55xxWriteBit(1); //Page 1
1140
1141 // Turn field on to read the response
1142 TurnReadLFOn();
1143
1144 // Now do the acquisition
1145 for(;;) {
1146 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1147 AT91C_BASE_SSC->SSC_THR = 0x43;
1148 LED_D_ON();
1149 }
1150 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1151 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1152 ++i;
1153 LED_D_OFF();
1154
1155 if (i >= bufferlength) break;
1156 }
1157 }
1158
1159 cmd_send(CMD_ACK,0,0,0,0,0);
1160 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1161 LED_D_OFF();
1162 }
1163
1164 void TurnReadLFOn(){
1165 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1166 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1167 // Give it a bit of time for the resonant antenna to settle.
1168 //SpinDelay(30);
1169 SpinDelayUs(8*150);
1170 }
1171
1172 /*-------------- Cloning routines -----------*/
1173 // Copy HID id to card and setup block 0 config
1174 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1175 {
1176 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1177 int last_block = 0;
1178
1179 if (longFMT){
1180 // Ensure no more than 84 bits supplied
1181 if (hi2>0xFFFFF) {
1182 DbpString("Tags can only have 84 bits.");
1183 return;
1184 }
1185 // Build the 6 data blocks for supplied 84bit ID
1186 last_block = 6;
1187 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1188 for (int i=0;i<4;i++) {
1189 if (hi2 & (1<<(19-i)))
1190 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1191 else
1192 data1 |= (1<<((3-i)*2)); // 0 -> 01
1193 }
1194
1195 data2 = 0;
1196 for (int i=0;i<16;i++) {
1197 if (hi2 & (1<<(15-i)))
1198 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1199 else
1200 data2 |= (1<<((15-i)*2)); // 0 -> 01
1201 }
1202
1203 data3 = 0;
1204 for (int i=0;i<16;i++) {
1205 if (hi & (1<<(31-i)))
1206 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1207 else
1208 data3 |= (1<<((15-i)*2)); // 0 -> 01
1209 }
1210
1211 data4 = 0;
1212 for (int i=0;i<16;i++) {
1213 if (hi & (1<<(15-i)))
1214 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1215 else
1216 data4 |= (1<<((15-i)*2)); // 0 -> 01
1217 }
1218
1219 data5 = 0;
1220 for (int i=0;i<16;i++) {
1221 if (lo & (1<<(31-i)))
1222 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1223 else
1224 data5 |= (1<<((15-i)*2)); // 0 -> 01
1225 }
1226
1227 data6 = 0;
1228 for (int i=0;i<16;i++) {
1229 if (lo & (1<<(15-i)))
1230 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1231 else
1232 data6 |= (1<<((15-i)*2)); // 0 -> 01
1233 }
1234 }
1235 else {
1236 // Ensure no more than 44 bits supplied
1237 if (hi>0xFFF) {
1238 DbpString("Tags can only have 44 bits.");
1239 return;
1240 }
1241
1242 // Build the 3 data blocks for supplied 44bit ID
1243 last_block = 3;
1244
1245 data1 = 0x1D000000; // load preamble
1246
1247 for (int i=0;i<12;i++) {
1248 if (hi & (1<<(11-i)))
1249 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1250 else
1251 data1 |= (1<<((11-i)*2)); // 0 -> 01
1252 }
1253
1254 data2 = 0;
1255 for (int i=0;i<16;i++) {
1256 if (lo & (1<<(31-i)))
1257 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1258 else
1259 data2 |= (1<<((15-i)*2)); // 0 -> 01
1260 }
1261
1262 data3 = 0;
1263 for (int i=0;i<16;i++) {
1264 if (lo & (1<<(15-i)))
1265 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1266 else
1267 data3 |= (1<<((15-i)*2)); // 0 -> 01
1268 }
1269 }
1270
1271 LED_D_ON();
1272 // Program the data blocks for supplied ID
1273 // and the block 0 for HID format
1274 T55xxWriteBlock(data1,1,0,0);
1275 T55xxWriteBlock(data2,2,0,0);
1276 T55xxWriteBlock(data3,3,0,0);
1277
1278 if (longFMT) { // if long format there are 6 blocks
1279 T55xxWriteBlock(data4,4,0,0);
1280 T55xxWriteBlock(data5,5,0,0);
1281 T55xxWriteBlock(data6,6,0,0);
1282 }
1283
1284 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1285 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1286 T55x7_MODULATION_FSK2a |
1287 last_block << T55x7_MAXBLOCK_SHIFT,
1288 0,0,0);
1289
1290 LED_D_OFF();
1291
1292 DbpString("DONE!");
1293 }
1294
1295 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1296 {
1297 int data1=0, data2=0; //up to six blocks for long format
1298
1299 data1 = hi; // load preamble
1300 data2 = lo;
1301
1302 LED_D_ON();
1303 // Program the data blocks for supplied ID
1304 // and the block 0 for HID format
1305 T55xxWriteBlock(data1,1,0,0);
1306 T55xxWriteBlock(data2,2,0,0);
1307
1308 //Config Block
1309 T55xxWriteBlock(0x00147040,0,0,0);
1310 LED_D_OFF();
1311
1312 DbpString("DONE!");
1313 }
1314
1315 // Define 9bit header for EM410x tags
1316 #define EM410X_HEADER 0x1FF
1317 #define EM410X_ID_LENGTH 40
1318
1319 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1320 {
1321 int i, id_bit;
1322 uint64_t id = EM410X_HEADER;
1323 uint64_t rev_id = 0; // reversed ID
1324 int c_parity[4]; // column parity
1325 int r_parity = 0; // row parity
1326 uint32_t clock = 0;
1327
1328 // Reverse ID bits given as parameter (for simpler operations)
1329 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1330 if (i < 32) {
1331 rev_id = (rev_id << 1) | (id_lo & 1);
1332 id_lo >>= 1;
1333 } else {
1334 rev_id = (rev_id << 1) | (id_hi & 1);
1335 id_hi >>= 1;
1336 }
1337 }
1338
1339 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1340 id_bit = rev_id & 1;
1341
1342 if (i % 4 == 0) {
1343 // Don't write row parity bit at start of parsing
1344 if (i)
1345 id = (id << 1) | r_parity;
1346 // Start counting parity for new row
1347 r_parity = id_bit;
1348 } else {
1349 // Count row parity
1350 r_parity ^= id_bit;
1351 }
1352
1353 // First elements in column?
1354 if (i < 4)
1355 // Fill out first elements
1356 c_parity[i] = id_bit;
1357 else
1358 // Count column parity
1359 c_parity[i % 4] ^= id_bit;
1360
1361 // Insert ID bit
1362 id = (id << 1) | id_bit;
1363 rev_id >>= 1;
1364 }
1365
1366 // Insert parity bit of last row
1367 id = (id << 1) | r_parity;
1368
1369 // Fill out column parity at the end of tag
1370 for (i = 0; i < 4; ++i)
1371 id = (id << 1) | c_parity[i];
1372
1373 // Add stop bit
1374 id <<= 1;
1375
1376 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1377 LED_D_ON();
1378
1379 // Write EM410x ID
1380 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1381 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1382
1383 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1384 if (card) {
1385 // Clock rate is stored in bits 8-15 of the card value
1386 clock = (card & 0xFF00) >> 8;
1387 Dbprintf("Clock rate: %d", clock);
1388 switch (clock)
1389 {
1390 case 32:
1391 clock = T55x7_BITRATE_RF_32;
1392 break;
1393 case 16:
1394 clock = T55x7_BITRATE_RF_16;
1395 break;
1396 case 0:
1397 // A value of 0 is assumed to be 64 for backwards-compatibility
1398 // Fall through...
1399 case 64:
1400 clock = T55x7_BITRATE_RF_64;
1401 break;
1402 default:
1403 Dbprintf("Invalid clock rate: %d", clock);
1404 return;
1405 }
1406
1407 // Writing configuration for T55x7 tag
1408 T55xxWriteBlock(clock |
1409 T55x7_MODULATION_MANCHESTER |
1410 2 << T55x7_MAXBLOCK_SHIFT,
1411 0, 0, 0);
1412 }
1413 else
1414 // Writing configuration for T5555(Q5) tag
1415 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1416 T5555_MODULATION_MANCHESTER |
1417 2 << T5555_MAXBLOCK_SHIFT,
1418 0, 0, 0);
1419
1420 LED_D_OFF();
1421 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1422 (uint32_t)(id >> 32), (uint32_t)id);
1423 }
1424
1425 // Clone Indala 64-bit tag by UID to T55x7
1426 void CopyIndala64toT55x7(int hi, int lo)
1427 {
1428 //Program the 2 data blocks for supplied 64bit UID
1429 // and the block 0 for Indala64 format
1430 T55xxWriteBlock(hi,1,0,0);
1431 T55xxWriteBlock(lo,2,0,0);
1432 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1433 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1434 T55x7_MODULATION_PSK1 |
1435 2 << T55x7_MAXBLOCK_SHIFT,
1436 0, 0, 0);
1437 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1438 // T5567WriteBlock(0x603E1042,0);
1439
1440 DbpString("DONE!");
1441 }
1442
1443 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1444 {
1445 //Program the 7 data blocks for supplied 224bit UID
1446 // and the block 0 for Indala224 format
1447 T55xxWriteBlock(uid1,1,0,0);
1448 T55xxWriteBlock(uid2,2,0,0);
1449 T55xxWriteBlock(uid3,3,0,0);
1450 T55xxWriteBlock(uid4,4,0,0);
1451 T55xxWriteBlock(uid5,5,0,0);
1452 T55xxWriteBlock(uid6,6,0,0);
1453 T55xxWriteBlock(uid7,7,0,0);
1454 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1455 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1456 T55x7_MODULATION_PSK1 |
1457 7 << T55x7_MAXBLOCK_SHIFT,
1458 0,0,0);
1459 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1460 // T5567WriteBlock(0x603E10E2,0);
1461
1462 DbpString("DONE!");
1463 }
1464
1465
1466 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1467 #define max(x,y) ( x<y ? y:x)
1468
1469 int DemodPCF7931(uint8_t **outBlocks) {
1470 uint8_t BitStream[256];
1471 uint8_t Blocks[8][16];
1472 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1473 int GraphTraceLen = sizeof(BigBuf);
1474 int i, j, lastval, bitidx, half_switch;
1475 int clock = 64;
1476 int tolerance = clock / 8;
1477 int pmc, block_done;
1478 int lc, warnings = 0;
1479 int num_blocks = 0;
1480 int lmin=128, lmax=128;
1481 uint8_t dir;
1482
1483 AcquireRawAdcSamples125k(0);
1484
1485 lmin = 64;
1486 lmax = 192;
1487
1488 i = 2;
1489
1490 /* Find first local max/min */
1491 if(GraphBuffer[1] > GraphBuffer[0]) {
1492 while(i < GraphTraceLen) {
1493 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1494 break;
1495 i++;
1496 }
1497 dir = 0;
1498 }
1499 else {
1500 while(i < GraphTraceLen) {
1501 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1502 break;
1503 i++;
1504 }
1505 dir = 1;
1506 }
1507
1508 lastval = i++;
1509 half_switch = 0;
1510 pmc = 0;
1511 block_done = 0;
1512
1513 for (bitidx = 0; i < GraphTraceLen; i++)
1514 {
1515 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1516 {
1517 lc = i - lastval;
1518 lastval = i;
1519
1520 // Switch depending on lc length:
1521 // Tolerance is 1/8 of clock rate (arbitrary)
1522 if (abs(lc-clock/4) < tolerance) {
1523 // 16T0
1524 if((i - pmc) == lc) { /* 16T0 was previous one */
1525 /* It's a PMC ! */
1526 i += (128+127+16+32+33+16)-1;
1527 lastval = i;
1528 pmc = 0;
1529 block_done = 1;
1530 }
1531 else {
1532 pmc = i;
1533 }
1534 } else if (abs(lc-clock/2) < tolerance) {
1535 // 32TO
1536 if((i - pmc) == lc) { /* 16T0 was previous one */
1537 /* It's a PMC ! */
1538 i += (128+127+16+32+33)-1;
1539 lastval = i;
1540 pmc = 0;
1541 block_done = 1;
1542 }
1543 else if(half_switch == 1) {
1544 BitStream[bitidx++] = 0;
1545 half_switch = 0;
1546 }
1547 else
1548 half_switch++;
1549 } else if (abs(lc-clock) < tolerance) {
1550 // 64TO
1551 BitStream[bitidx++] = 1;
1552 } else {
1553 // Error
1554 warnings++;
1555 if (warnings > 10)
1556 {
1557 Dbprintf("Error: too many detection errors, aborting.");
1558 return 0;
1559 }
1560 }
1561
1562 if(block_done == 1) {
1563 if(bitidx == 128) {
1564 for(j=0; j<16; j++) {
1565 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1566 64*BitStream[j*8+6]+
1567 32*BitStream[j*8+5]+
1568 16*BitStream[j*8+4]+
1569 8*BitStream[j*8+3]+
1570 4*BitStream[j*8+2]+
1571 2*BitStream[j*8+1]+
1572 BitStream[j*8];
1573 }
1574 num_blocks++;
1575 }
1576 bitidx = 0;
1577 block_done = 0;
1578 half_switch = 0;
1579 }
1580 if(i < GraphTraceLen)
1581 {
1582 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1583 else dir = 1;
1584 }
1585 }
1586 if(bitidx==255)
1587 bitidx=0;
1588 warnings = 0;
1589 if(num_blocks == 4) break;
1590 }
1591 memcpy(outBlocks, Blocks, 16*num_blocks);
1592 return num_blocks;
1593 }
1594
1595 int IsBlock0PCF7931(uint8_t *Block) {
1596 // Assume RFU means 0 :)
1597 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1598 return 1;
1599 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1600 return 1;
1601 return 0;
1602 }
1603
1604 int IsBlock1PCF7931(uint8_t *Block) {
1605 // Assume RFU means 0 :)
1606 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1607 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1608 return 1;
1609
1610 return 0;
1611 }
1612 #define ALLOC 16
1613
1614 void ReadPCF7931() {
1615 uint8_t Blocks[8][17];
1616 uint8_t tmpBlocks[4][16];
1617 int i, j, ind, ind2, n;
1618 int num_blocks = 0;
1619 int max_blocks = 8;
1620 int ident = 0;
1621 int error = 0;
1622 int tries = 0;
1623
1624 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1625
1626 do {
1627 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1628 n = DemodPCF7931((uint8_t**)tmpBlocks);
1629 if(!n)
1630 error++;
1631 if(error==10 && num_blocks == 0) {
1632 Dbprintf("Error, no tag or bad tag");
1633 return;
1634 }
1635 else if (tries==20 || error==10) {
1636 Dbprintf("Error reading the tag");
1637 Dbprintf("Here is the partial content");
1638 goto end;
1639 }
1640
1641 for(i=0; i<n; i++)
1642 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1643 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1644 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1645 if(!ident) {
1646 for(i=0; i<n; i++) {
1647 if(IsBlock0PCF7931(tmpBlocks[i])) {
1648 // Found block 0 ?
1649 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1650 // Found block 1!
1651 // \o/
1652 ident = 1;
1653 memcpy(Blocks[0], tmpBlocks[i], 16);
1654 Blocks[0][ALLOC] = 1;
1655 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1656 Blocks[1][ALLOC] = 1;
1657 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1658 // Debug print
1659 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1660 num_blocks = 2;
1661 // Handle following blocks
1662 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1663 if(j==n) j=0;
1664 if(j==i) break;
1665 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1666 Blocks[ind2][ALLOC] = 1;
1667 }
1668 break;
1669 }
1670 }
1671 }
1672 }
1673 else {
1674 for(i=0; i<n; i++) { // Look for identical block in known blocks
1675 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1676 for(j=0; j<max_blocks; j++) {
1677 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1678 // Found an identical block
1679 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1680 if(ind2 < 0)
1681 ind2 = max_blocks;
1682 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1683 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1684 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1685 Blocks[ind2][ALLOC] = 1;
1686 num_blocks++;
1687 if(num_blocks == max_blocks) goto end;
1688 }
1689 }
1690 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1691 if(ind2 > max_blocks)
1692 ind2 = 0;
1693 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1694 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1695 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1696 Blocks[ind2][ALLOC] = 1;
1697 num_blocks++;
1698 if(num_blocks == max_blocks) goto end;
1699 }
1700 }
1701 }
1702 }
1703 }
1704 }
1705 }
1706 tries++;
1707 if (BUTTON_PRESS()) return;
1708 } while (num_blocks != max_blocks);
1709 end:
1710 Dbprintf("-----------------------------------------");
1711 Dbprintf("Memory content:");
1712 Dbprintf("-----------------------------------------");
1713 for(i=0; i<max_blocks; i++) {
1714 if(Blocks[i][ALLOC]==1)
1715 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1716 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1717 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1718 else
1719 Dbprintf("<missing block %d>", i);
1720 }
1721 Dbprintf("-----------------------------------------");
1722
1723 return ;
1724 }
1725
1726
1727 //-----------------------------------
1728 // EM4469 / EM4305 routines
1729 //-----------------------------------
1730 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1731 #define FWD_CMD_WRITE 0xA
1732 #define FWD_CMD_READ 0x9
1733 #define FWD_CMD_DISABLE 0x5
1734
1735
1736 uint8_t forwardLink_data[64]; //array of forwarded bits
1737 uint8_t * forward_ptr; //ptr for forward message preparation
1738 uint8_t fwd_bit_sz; //forwardlink bit counter
1739 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1740
1741 //====================================================================
1742 // prepares command bits
1743 // see EM4469 spec
1744 //====================================================================
1745 //--------------------------------------------------------------------
1746 uint8_t Prepare_Cmd( uint8_t cmd ) {
1747 //--------------------------------------------------------------------
1748
1749 *forward_ptr++ = 0; //start bit
1750 *forward_ptr++ = 0; //second pause for 4050 code
1751
1752 *forward_ptr++ = cmd;
1753 cmd >>= 1;
1754 *forward_ptr++ = cmd;
1755 cmd >>= 1;
1756 *forward_ptr++ = cmd;
1757 cmd >>= 1;
1758 *forward_ptr++ = cmd;
1759
1760 return 6; //return number of emited bits
1761 }
1762
1763 //====================================================================
1764 // prepares address bits
1765 // see EM4469 spec
1766 //====================================================================
1767
1768 //--------------------------------------------------------------------
1769 uint8_t Prepare_Addr( uint8_t addr ) {
1770 //--------------------------------------------------------------------
1771
1772 register uint8_t line_parity;
1773
1774 uint8_t i;
1775 line_parity = 0;
1776 for(i=0;i<6;i++) {
1777 *forward_ptr++ = addr;
1778 line_parity ^= addr;
1779 addr >>= 1;
1780 }
1781
1782 *forward_ptr++ = (line_parity & 1);
1783
1784 return 7; //return number of emited bits
1785 }
1786
1787 //====================================================================
1788 // prepares data bits intreleaved with parity bits
1789 // see EM4469 spec
1790 //====================================================================
1791
1792 //--------------------------------------------------------------------
1793 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1794 //--------------------------------------------------------------------
1795
1796 register uint8_t line_parity;
1797 register uint8_t column_parity;
1798 register uint8_t i, j;
1799 register uint16_t data;
1800
1801 data = data_low;
1802 column_parity = 0;
1803
1804 for(i=0; i<4; i++) {
1805 line_parity = 0;
1806 for(j=0; j<8; j++) {
1807 line_parity ^= data;
1808 column_parity ^= (data & 1) << j;
1809 *forward_ptr++ = data;
1810 data >>= 1;
1811 }
1812 *forward_ptr++ = line_parity;
1813 if(i == 1)
1814 data = data_hi;
1815 }
1816
1817 for(j=0; j<8; j++) {
1818 *forward_ptr++ = column_parity;
1819 column_parity >>= 1;
1820 }
1821 *forward_ptr = 0;
1822
1823 return 45; //return number of emited bits
1824 }
1825
1826 //====================================================================
1827 // Forward Link send function
1828 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1829 // fwd_bit_count set with number of bits to be sent
1830 //====================================================================
1831 void SendForward(uint8_t fwd_bit_count) {
1832
1833 fwd_write_ptr = forwardLink_data;
1834 fwd_bit_sz = fwd_bit_count;
1835
1836 LED_D_ON();
1837
1838 //Field on
1839 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1840 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1841 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1842
1843 // Give it a bit of time for the resonant antenna to settle.
1844 // And for the tag to fully power up
1845 SpinDelay(150);
1846
1847 // force 1st mod pulse (start gap must be longer for 4305)
1848 fwd_bit_sz--; //prepare next bit modulation
1849 fwd_write_ptr++;
1850 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1851 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1852 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1853 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1854 SpinDelayUs(16*8); //16 cycles on (8us each)
1855
1856 // now start writting
1857 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1858 if(((*fwd_write_ptr++) & 1) == 1)
1859 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1860 else {
1861 //These timings work for 4469/4269/4305 (with the 55*8 above)
1862 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1863 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1864 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1865 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1866 SpinDelayUs(9*8); //16 cycles on (8us each)
1867 }
1868 }
1869 }
1870
1871
1872 void EM4xLogin(uint32_t Password) {
1873
1874 uint8_t fwd_bit_count;
1875
1876 forward_ptr = forwardLink_data;
1877 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1878 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1879
1880 SendForward(fwd_bit_count);
1881
1882 //Wait for command to complete
1883 SpinDelay(20);
1884
1885 }
1886
1887 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1888
1889 uint8_t *dest = get_bigbufptr_recvrespbuf();
1890 uint16_t bufferlength = 12000;
1891 uint32_t i = 0;
1892
1893 // Clear destination buffer before sending the command 0x80 = average.
1894 memset(dest, 0x80, bufferlength);
1895
1896 uint8_t fwd_bit_count;
1897
1898 //If password mode do login
1899 if (PwdMode == 1) EM4xLogin(Pwd);
1900
1901 forward_ptr = forwardLink_data;
1902 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1903 fwd_bit_count += Prepare_Addr( Address );
1904
1905 // Connect the A/D to the peak-detected low-frequency path.
1906 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1907 // Now set up the SSC to get the ADC samples that are now streaming at us.
1908 FpgaSetupSsc();
1909
1910 SendForward(fwd_bit_count);
1911
1912 // // Turn field on to read the response
1913 // TurnReadLFOn();
1914
1915 // Now do the acquisition
1916 i = 0;
1917 for(;;) {
1918 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1919 AT91C_BASE_SSC->SSC_THR = 0x43;
1920 }
1921 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1922 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1923 ++i;
1924 if (i >= bufferlength) break;
1925 }
1926 }
1927
1928 cmd_send(CMD_ACK,0,0,0,0,0);
1929 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1930 LED_D_OFF();
1931 }
1932
1933 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1934
1935 uint8_t fwd_bit_count;
1936
1937 //If password mode do login
1938 if (PwdMode == 1) EM4xLogin(Pwd);
1939
1940 forward_ptr = forwardLink_data;
1941 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1942 fwd_bit_count += Prepare_Addr( Address );
1943 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1944
1945 SendForward(fwd_bit_count);
1946
1947 //Wait for write to complete
1948 SpinDelay(20);
1949 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1950 LED_D_OFF();
1951 }
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