]> cvs.zerfleddert.de Git - proxmark3-svn/blob - armsrc/hfsnoop.c
Merge pull request #862 from pwpiwi/fix_iclass_sim
[proxmark3-svn] / armsrc / hfsnoop.c
1 //-----------------------------------------------------------------------------
2 // piwi, 2019
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // Routines to get sample data from FPGA.
9 //-----------------------------------------------------------------------------
10
11 #include "hfsnoop.h"
12
13 #include "proxmark3.h"
14 #include "BigBuf.h"
15 #include "util.h"
16 #include "apps.h"
17 #include "usb_cdc.h" // for usb_poll_validate_length
18 #include "fpga.h"
19 #include "fpgaloader.h"
20
21 static void RAMFUNC optimizedSnoop(void)
22 {
23 int n = BigBuf_max_traceLen() / sizeof(uint16_t); // take all memory
24
25 uint16_t *dest = (uint16_t *)BigBuf_get_addr();
26 uint16_t *destend = dest + n;
27
28 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(16); // Setting Frame mode, 16 bits per word
29 // Reading data loop
30 while(dest <= destend)
31 {
32 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)
33 {
34 *dest = (uint16_t)(AT91C_BASE_SSC->SSC_RHR);
35 dest++;
36 }
37 }
38 //Resetting Frame mode (First set in fpgaloader.c)
39 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
40 }
41
42 void HfSnoop(int samplesToSkip, int triggersToSkip)
43 {
44 BigBuf_free(); BigBuf_Clear();
45
46 Dbprintf("Skipping first %d sample pairs, Skipping %d triggers.\n", samplesToSkip, triggersToSkip);
47 int trigger_cnt;
48 LED_D_ON();
49 // Select correct configs
50 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
51 // Set up the synchronous serial port
52 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SNOOP);
53 // connect Demodulated Signal to ADC:
54 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
55 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SNOOP);
56 SpinDelay(100);
57
58 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(16); // Setting Frame Mode For better performance on high speed data transfer.
59
60 trigger_cnt = 0;
61 uint16_t r = 0;
62 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
63 WDT_HIT();
64 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
65 r = (uint16_t)AT91C_BASE_SSC->SSC_RHR;
66 r = MAX(r & 0xff, r >> 8);
67 if (r >= 240) {
68 if (++trigger_cnt > triggersToSkip)
69 break;
70 }
71 }
72 }
73
74 if(!BUTTON_PRESS()) {
75 int waitcount = samplesToSkip; // lets wait 40000 ticks of pck0
76 while(waitcount != 0) {
77 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY))
78 waitcount--;
79 }
80 optimizedSnoop();
81 Dbprintf("Trigger kicked! Value: %d, Dumping Samples Hispeed now.", r);
82 }
83
84 DbpString("HF Snoop end");
85 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
86 LED_D_OFF();
87 }
88
89 void HfPlot(void)
90 {
91 uint8_t *buf = ToSend;
92 uint8_t *this_buf = buf;
93
94 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
95 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_GET_TRACE);
96 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; // Disable DMA Transfer
97 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) this_buf; // start transfer to this memory address
98 AT91C_BASE_PDC_SSC->PDC_RCR = USB_CMD_DATA_SIZE; // transfer this many samples
99 buf[0] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; // clear receive register
100 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; // Start DMA transfer
101 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_GET_TRACE); // let FPGA transfer its internal Block-RAM
102
103 LED_B_ON();
104 for(size_t i = 0; i < FPGA_TRACE_SIZE; i += USB_CMD_DATA_SIZE) {
105 // prepare next DMA transfer:
106 uint8_t *next_buf = buf + ((i + USB_CMD_DATA_SIZE) % (2 * USB_CMD_DATA_SIZE));
107 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t)next_buf;
108 AT91C_BASE_PDC_SSC->PDC_RNCR = USB_CMD_DATA_SIZE;
109 size_t len = MIN(FPGA_TRACE_SIZE - i, USB_CMD_DATA_SIZE);
110 while (!(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_ENDRX))) ; // wait for DMA transfer to complete
111 cmd_send(CMD_DOWNLOADED_RAW_ADC_SAMPLES_125K, i, len, FPGA_TRACE_SIZE, this_buf, len);
112 this_buf = next_buf;
113 }
114 // Trigger a finish downloading signal with an ACK frame
115 cmd_send(CMD_ACK, 1, 0, FPGA_TRACE_SIZE, 0, 0);
116 LED_B_OFF();
117 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
118 }
Impressum, Datenschutz