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FIX: corrected the FLAG_NR_AR_ATTACK
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1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12
13 #include "proxmark3.h"
14 #include "apps.h"
15 #include "util.h"
16 #include "string.h"
17 #include "cmd.h"
18 #include "iso14443crc.h"
19 #include "iso14443a.h"
20 #include "iso14443b.h"
21 #include "crapto1.h"
22 #include "mifareutil.h"
23 #include "BigBuf.h"
24 #include "parity.h"
25
26 static uint32_t iso14a_timeout;
27 int rsamples = 0;
28 uint8_t trigger = 0;
29 // the block number for the ISO14443-4 PCB
30 static uint8_t iso14_pcb_blocknum = 0;
31
32 static uint8_t* free_buffer_pointer;
33
34 //
35 // ISO14443 timing:
36 //
37 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
38 #define REQUEST_GUARD_TIME (7000/16 + 1)
39 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
40 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
41 // bool LastCommandWasRequest = FALSE;
42
43 //
44 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
45 //
46 // When the PM acts as reader and is receiving tag data, it takes
47 // 3 ticks delay in the AD converter
48 // 16 ticks until the modulation detector completes and sets curbit
49 // 8 ticks until bit_to_arm is assigned from curbit
50 // 8*16 ticks for the transfer from FPGA to ARM
51 // 4*16 ticks until we measure the time
52 // - 8*16 ticks because we measure the time of the previous transfer
53 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
54
55 // When the PM acts as a reader and is sending, it takes
56 // 4*16 ticks until we can write data to the sending hold register
57 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
58 // 8 ticks until the first transfer starts
59 // 8 ticks later the FPGA samples the data
60 // 1 tick to assign mod_sig_coil
61 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
62
63 // When the PM acts as tag and is receiving it takes
64 // 2 ticks delay in the RF part (for the first falling edge),
65 // 3 ticks for the A/D conversion,
66 // 8 ticks on average until the start of the SSC transfer,
67 // 8 ticks until the SSC samples the first data
68 // 7*16 ticks to complete the transfer from FPGA to ARM
69 // 8 ticks until the next ssp_clk rising edge
70 // 4*16 ticks until we measure the time
71 // - 8*16 ticks because we measure the time of the previous transfer
72 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
73
74 // The FPGA will report its internal sending delay in
75 uint16_t FpgaSendQueueDelay;
76 // the 5 first bits are the number of bits buffered in mod_sig_buf
77 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
78 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
79
80 // When the PM acts as tag and is sending, it takes
81 // 4*16 ticks until we can write data to the sending hold register
82 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
83 // 8 ticks until the first transfer starts
84 // 8 ticks later the FPGA samples the data
85 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
86 // + 1 tick to assign mod_sig_coil
87 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
88
89 // When the PM acts as sniffer and is receiving tag data, it takes
90 // 3 ticks A/D conversion
91 // 14 ticks to complete the modulation detection
92 // 8 ticks (on average) until the result is stored in to_arm
93 // + the delays in transferring data - which is the same for
94 // sniffing reader and tag data and therefore not relevant
95 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
96
97 // When the PM acts as sniffer and is receiving reader data, it takes
98 // 2 ticks delay in analogue RF receiver (for the falling edge of the
99 // start bit, which marks the start of the communication)
100 // 3 ticks A/D conversion
101 // 8 ticks on average until the data is stored in to_arm.
102 // + the delays in transferring data - which is the same for
103 // sniffing reader and tag data and therefore not relevant
104 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
105
106 //variables used for timing purposes:
107 //these are in ssp_clk cycles:
108 static uint32_t NextTransferTime;
109 static uint32_t LastTimeProxToAirStart;
110 static uint32_t LastProxToAirDuration;
111
112 // CARD TO READER - manchester
113 // Sequence D: 11110000 modulation with subcarrier during first half
114 // Sequence E: 00001111 modulation with subcarrier during second half
115 // Sequence F: 00000000 no modulation with subcarrier
116 // READER TO CARD - miller
117 // Sequence X: 00001100 drop after half a period
118 // Sequence Y: 00000000 no drop
119 // Sequence Z: 11000000 drop at start
120 #define SEC_D 0xf0
121 #define SEC_E 0x0f
122 #define SEC_F 0x00
123 #define SEC_X 0x0c
124 #define SEC_Y 0x00
125 #define SEC_Z 0xc0
126
127 void iso14a_set_trigger(bool enable) {
128 trigger = enable;
129 }
130
131 void iso14a_set_timeout(uint32_t timeout) {
132 iso14a_timeout = timeout;
133 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
134 }
135
136 void iso14a_set_ATS_timeout(uint8_t *ats) {
137 uint8_t tb1;
138 uint8_t fwi;
139 uint32_t fwt;
140
141 if (ats[0] > 1) { // there is a format byte T0
142 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
143
144 if ((ats[1] & 0x10) == 0x10) // there is an interface byte TA(1) preceding TB(1)
145 tb1 = ats[3];
146 else
147 tb1 = ats[2];
148
149 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
150 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
151 //fwt = 4096 * (1 << fwi);
152
153 iso14a_set_timeout(fwt/(8*16));
154 //iso14a_set_timeout(fwt/128);
155 }
156 }
157 }
158
159 //-----------------------------------------------------------------------------
160 // Generate the parity value for a byte sequence
161 //
162 //-----------------------------------------------------------------------------
163 void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par) {
164 uint16_t paritybit_cnt = 0;
165 uint16_t paritybyte_cnt = 0;
166 uint8_t parityBits = 0;
167
168 for (uint16_t i = 0; i < iLen; i++) {
169 // Generate the parity bits
170 parityBits |= ((oddparity8(pbtCmd[i])) << (7-paritybit_cnt));
171 if (paritybit_cnt == 7) {
172 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
173 parityBits = 0; // and advance to next Parity Byte
174 paritybyte_cnt++;
175 paritybit_cnt = 0;
176 } else {
177 paritybit_cnt++;
178 }
179 }
180
181 // save remaining parity bits
182 par[paritybyte_cnt] = parityBits;
183 }
184
185 void AppendCrc14443a(uint8_t* data, int len) {
186 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
187 }
188
189 //=============================================================================
190 // ISO 14443 Type A - Miller decoder
191 //=============================================================================
192 // Basics:
193 // This decoder is used when the PM3 acts as a tag.
194 // The reader will generate "pauses" by temporarily switching of the field.
195 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
196 // The FPGA does a comparison with a threshold and would deliver e.g.:
197 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
198 // The Miller decoder needs to identify the following sequences:
199 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
200 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
201 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
202 // Note 1: the bitstream may start at any time. We therefore need to sync.
203 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
204 //-----------------------------------------------------------------------------
205 static tUart Uart;
206
207 // Lookup-Table to decide if 4 raw bits are a modulation.
208 // We accept the following:
209 // 0001 - a 3 tick wide pause
210 // 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
211 // 0111 - a 2 tick wide pause shifted left
212 // 1001 - a 2 tick wide pause shifted right
213 const bool Mod_Miller_LUT[] = {
214 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
215 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
216 };
217 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
218 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
219
220 void UartReset() {
221 Uart.state = STATE_UNSYNCD;
222 Uart.bitCount = 0;
223 Uart.len = 0; // number of decoded data bytes
224 Uart.parityLen = 0; // number of decoded parity bytes
225 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
226 Uart.parityBits = 0; // holds 8 parity bits
227 Uart.startTime = 0;
228 Uart.endTime = 0;
229
230 Uart.byteCntMax = 0;
231 Uart.posCnt = 0;
232 Uart.syncBit = 9999;
233 }
234
235 void UartInit(uint8_t *data, uint8_t *parity) {
236 Uart.output = data;
237 Uart.parity = parity;
238 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
239 UartReset();
240 }
241
242 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
243 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time) {
244 Uart.fourBits = (Uart.fourBits << 8) | bit;
245
246 if (Uart.state == STATE_UNSYNCD) { // not yet synced
247 Uart.syncBit = 9999; // not set
248
249 // 00x11111 2|3 ticks pause followed by 6|5 ticks unmodulated Sequence Z (a "0" or "start of communication")
250 // 11111111 8 ticks unmodulation Sequence Y (a "0" or "end of communication" or "no information")
251 // 111100x1 4 ticks unmodulated followed by 2|3 ticks pause Sequence X (a "1")
252
253 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
254 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
255 // we therefore look for a ...xx1111 11111111 00x11111xxxxxx... pattern
256 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
257 //
258 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00001111 11111111 1110 1111 10000000
259 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00001111 11111111 1000 1111 10000000
260
261 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
262 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
263 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
264 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
265 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
266 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
267 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
268 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
269
270 if (Uart.syncBit != 9999) { // found a sync bit
271 Uart.startTime = non_real_time ? non_real_time : (GetCountSspClk() & 0xfffffff8);
272 Uart.startTime -= Uart.syncBit;
273 Uart.endTime = Uart.startTime;
274 Uart.state = STATE_START_OF_COMMUNICATION;
275 }
276 } else {
277
278 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
279 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
280 UartReset();
281 } else { // Modulation in first half = Sequence Z = logic "0"
282 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
283 UartReset();
284 } else {
285 Uart.bitCount++;
286 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
287 Uart.state = STATE_MILLER_Z;
288 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
289 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
290 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
291 Uart.parityBits <<= 1; // make room for the parity bit
292 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
293 Uart.bitCount = 0;
294 Uart.shiftReg = 0;
295 if((Uart.len&0x0007) == 0) { // every 8 data bytes
296 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
297 Uart.parityBits = 0;
298 }
299 }
300 }
301 }
302 } else {
303 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
304 Uart.bitCount++;
305 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
306 Uart.state = STATE_MILLER_X;
307 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
308 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
309 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
310 Uart.parityBits <<= 1; // make room for the new parity bit
311 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
312 Uart.bitCount = 0;
313 Uart.shiftReg = 0;
314 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
315 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
316 Uart.parityBits = 0;
317 }
318 }
319 } else { // no modulation in both halves - Sequence Y
320 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
321 Uart.state = STATE_UNSYNCD;
322 Uart.bitCount--; // last "0" was part of EOC sequence
323 Uart.shiftReg <<= 1; // drop it
324 if(Uart.bitCount > 0) { // if we decoded some bits
325 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
326 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
327 Uart.parityBits <<= 1; // add a (void) parity bit
328 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
329 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
330 return TRUE;
331 } else if (Uart.len & 0x0007) { // there are some parity bits to store
332 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
333 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
334 }
335 if (Uart.len) {
336 return TRUE; // we are finished with decoding the raw data sequence
337 } else {
338 UartReset(); // Nothing received - start over
339 }
340 }
341 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
342 UartReset();
343 } else { // a logic "0"
344 Uart.bitCount++;
345 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
346 Uart.state = STATE_MILLER_Y;
347 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
348 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
349 Uart.parityBits <<= 1; // make room for the parity bit
350 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
351 Uart.bitCount = 0;
352 Uart.shiftReg = 0;
353 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
354 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
355 Uart.parityBits = 0;
356 }
357 }
358 }
359 }
360 }
361 }
362 return FALSE; // not finished yet, need more data
363 }
364
365 //=============================================================================
366 // ISO 14443 Type A - Manchester decoder
367 //=============================================================================
368 // Basics:
369 // This decoder is used when the PM3 acts as a reader.
370 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
371 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
372 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
373 // The Manchester decoder needs to identify the following sequences:
374 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
375 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
376 // 8 ticks unmodulated: Sequence F = end of communication
377 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
378 // Note 1: the bitstream may start at any time. We therefore need to sync.
379 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
380 static tDemod Demod;
381
382 // Lookup-Table to decide if 4 raw bits are a modulation.
383 // We accept three or four "1" in any position
384 const bool Mod_Manchester_LUT[] = {
385 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
386 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
387 };
388
389 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
390 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
391
392 void DemodReset() {
393 Demod.state = DEMOD_UNSYNCD;
394 Demod.len = 0; // number of decoded data bytes
395 Demod.parityLen = 0;
396 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
397 Demod.parityBits = 0; //
398 Demod.collisionPos = 0; // Position of collision bit
399 Demod.twoBits = 0xffff; // buffer for 2 Bits
400 Demod.highCnt = 0;
401 Demod.startTime = 0;
402 Demod.endTime = 0;
403 Demod.bitCount = 0;
404 Demod.syncBit = 0xFFFF;
405 Demod.samples = 0;
406 }
407
408 void DemodInit(uint8_t *data, uint8_t *parity) {
409 Demod.output = data;
410 Demod.parity = parity;
411 DemodReset();
412 }
413
414 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
415 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time) {
416 Demod.twoBits = (Demod.twoBits << 8) | bit;
417
418 if (Demod.state == DEMOD_UNSYNCD) {
419
420 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
421 if (Demod.twoBits == 0x0000) {
422 Demod.highCnt++;
423 } else {
424 Demod.highCnt = 0;
425 }
426 } else {
427 Demod.syncBit = 0xFFFF; // not set
428 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
429 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
430 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
431 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
432 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
433 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
434 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
435 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
436 if (Demod.syncBit != 0xFFFF) {
437 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
438 Demod.startTime -= Demod.syncBit;
439 Demod.bitCount = offset; // number of decoded data bits
440 Demod.state = DEMOD_MANCHESTER_DATA;
441 }
442 }
443 } else {
444
445 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
446 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
447 if (!Demod.collisionPos) {
448 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
449 }
450 } // modulation in first half only - Sequence D = 1
451 Demod.bitCount++;
452 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
453 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
454 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
455 Demod.parityBits <<= 1; // make room for the parity bit
456 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
457 Demod.bitCount = 0;
458 Demod.shiftReg = 0;
459 if((Demod.len&0x0007) == 0) { // every 8 data bytes
460 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
461 Demod.parityBits = 0;
462 }
463 }
464 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
465 } else { // no modulation in first half
466 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
467 Demod.bitCount++;
468 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
469 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
470 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
471 Demod.parityBits <<= 1; // make room for the new parity bit
472 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
473 Demod.bitCount = 0;
474 Demod.shiftReg = 0;
475 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
476 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
477 Demod.parityBits = 0;
478 }
479 }
480 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
481 } else { // no modulation in both halves - End of communication
482 if(Demod.bitCount > 0) { // there are some remaining data bits
483 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
484 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
485 Demod.parityBits <<= 1; // add a (void) parity bit
486 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
487 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
488 return TRUE;
489 } else if (Demod.len & 0x0007) { // there are some parity bits to store
490 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
491 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
492 }
493 if (Demod.len) {
494 return TRUE; // we are finished with decoding the raw data sequence
495 } else { // nothing received. Start over
496 DemodReset();
497 }
498 }
499 }
500 }
501 return FALSE; // not finished yet, need more data
502 }
503
504 //=============================================================================
505 // Finally, a `sniffer' for ISO 14443 Type A
506 // Both sides of communication!
507 //=============================================================================
508
509 //-----------------------------------------------------------------------------
510 // Record the sequence of commands sent by the reader to the tag, with
511 // triggering so that we start recording at the point that the tag is moved
512 // near the reader.
513 //-----------------------------------------------------------------------------
514 void RAMFUNC SniffIso14443a(uint8_t param) {
515 // param:
516 // bit 0 - trigger from first card answer
517 // bit 1 - trigger from first reader 7-bit request
518 LEDsoff();
519
520 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
521
522 // Allocate memory from BigBuf for some buffers
523 // free all previous allocations first
524 BigBuf_free(); BigBuf_Clear_ext(false);
525 clear_trace();
526 set_tracing(TRUE);
527
528 // The command (reader -> tag) that we're receiving.
529 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
530 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
531
532 // The response (tag -> reader) that we're receiving.
533 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
534 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
535
536 // The DMA buffer, used to stream samples from the FPGA
537 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
538
539 uint8_t *data = dmaBuf;
540 uint8_t previous_data = 0;
541 int maxDataLen = 0;
542 int dataLen = 0;
543 bool TagIsActive = FALSE;
544 bool ReaderIsActive = FALSE;
545
546 // Set up the demodulator for tag -> reader responses.
547 DemodInit(receivedResponse, receivedResponsePar);
548
549 // Set up the demodulator for the reader -> tag commands
550 UartInit(receivedCmd, receivedCmdPar);
551
552 // Setup and start DMA.
553 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
554
555 // We won't start recording the frames that we acquire until we trigger;
556 // a good trigger condition to get started is probably when we see a
557 // response from the tag.
558 // triggered == FALSE -- to wait first for card
559 bool triggered = !(param & 0x03);
560
561 // And now we loop, receiving samples.
562 for(uint32_t rsamples = 0; TRUE; ) {
563
564 if(BUTTON_PRESS()) {
565 DbpString("cancelled by button");
566 break;
567 }
568
569 LED_A_ON();
570 WDT_HIT();
571
572 int register readBufDataP = data - dmaBuf;
573 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
574 if (readBufDataP <= dmaBufDataP){
575 dataLen = dmaBufDataP - readBufDataP;
576 } else {
577 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
578 }
579 // test for length of buffer
580 if(dataLen > maxDataLen) {
581 maxDataLen = dataLen;
582 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
583 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
584 break;
585 }
586 }
587 if(dataLen < 1) continue;
588
589 // primary buffer was stopped( <-- we lost data!
590 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
591 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
592 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
593 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
594 }
595 // secondary buffer sets as primary, secondary buffer was stopped
596 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
597 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
598 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
599 }
600
601 LED_A_OFF();
602
603 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
604
605 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
606 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
607 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
608 LED_C_ON();
609
610 // check - if there is a short 7bit request from reader
611 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
612
613 if(triggered) {
614 if (!LogTrace(receivedCmd,
615 Uart.len,
616 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
617 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
618 Uart.parity,
619 TRUE)) break;
620 }
621 /* And ready to receive another command. */
622 UartReset();
623 /* And also reset the demod code, which might have been */
624 /* false-triggered by the commands from the reader. */
625 DemodReset();
626 LED_B_OFF();
627 }
628 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
629 }
630
631 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
632 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
633 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
634 LED_B_ON();
635
636 if (!LogTrace(receivedResponse,
637 Demod.len,
638 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
639 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
640 Demod.parity,
641 FALSE)) break;
642
643 if ((!triggered) && (param & 0x01)) triggered = TRUE;
644
645 // And ready to receive another response.
646 DemodReset();
647 // And reset the Miller decoder including itS (now outdated) input buffer
648 UartInit(receivedCmd, receivedCmdPar);
649 LED_C_OFF();
650 }
651 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
652 }
653 }
654
655 previous_data = *data;
656 rsamples++;
657 data++;
658 if(data == dmaBuf + DMA_BUFFER_SIZE) {
659 data = dmaBuf;
660 }
661 } // main cycle
662
663 FpgaDisableSscDma();
664 LEDsoff();
665
666 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
667 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
668
669 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
670 set_tracing(FALSE);
671 }
672
673 //-----------------------------------------------------------------------------
674 // Prepare tag messages
675 //-----------------------------------------------------------------------------
676 static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity) {
677 ToSendReset();
678
679 // Correction bit, might be removed when not needed
680 ToSendStuffBit(0);
681 ToSendStuffBit(0);
682 ToSendStuffBit(0);
683 ToSendStuffBit(0);
684 ToSendStuffBit(1); // 1
685 ToSendStuffBit(0);
686 ToSendStuffBit(0);
687 ToSendStuffBit(0);
688
689 // Send startbit
690 ToSend[++ToSendMax] = SEC_D;
691 LastProxToAirDuration = 8 * ToSendMax - 4;
692
693 for(uint16_t i = 0; i < len; i++) {
694 uint8_t b = cmd[i];
695
696 // Data bits
697 for(uint16_t j = 0; j < 8; j++) {
698 if(b & 1) {
699 ToSend[++ToSendMax] = SEC_D;
700 } else {
701 ToSend[++ToSendMax] = SEC_E;
702 }
703 b >>= 1;
704 }
705
706 // Get the parity bit
707 if (parity[i>>3] & (0x80>>(i&0x0007))) {
708 ToSend[++ToSendMax] = SEC_D;
709 LastProxToAirDuration = 8 * ToSendMax - 4;
710 } else {
711 ToSend[++ToSendMax] = SEC_E;
712 LastProxToAirDuration = 8 * ToSendMax;
713 }
714 }
715
716 // Send stopbit
717 ToSend[++ToSendMax] = SEC_F;
718
719 // Convert from last byte pos to length
720 ++ToSendMax;
721 }
722
723 static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len) {
724 uint8_t par[MAX_PARITY_SIZE] = {0};
725 GetParity(cmd, len, par);
726 CodeIso14443aAsTagPar(cmd, len, par);
727 }
728
729 static void Code4bitAnswerAsTag(uint8_t cmd) {
730 uint8_t b = cmd;
731
732 ToSendReset();
733
734 // Correction bit, might be removed when not needed
735 ToSendStuffBit(0);
736 ToSendStuffBit(0);
737 ToSendStuffBit(0);
738 ToSendStuffBit(0);
739 ToSendStuffBit(1); // 1
740 ToSendStuffBit(0);
741 ToSendStuffBit(0);
742 ToSendStuffBit(0);
743
744 // Send startbit
745 ToSend[++ToSendMax] = SEC_D;
746
747 for(uint8_t i = 0; i < 4; i++) {
748 if(b & 1) {
749 ToSend[++ToSendMax] = SEC_D;
750 LastProxToAirDuration = 8 * ToSendMax - 4;
751 } else {
752 ToSend[++ToSendMax] = SEC_E;
753 LastProxToAirDuration = 8 * ToSendMax;
754 }
755 b >>= 1;
756 }
757
758 // Send stopbit
759 ToSend[++ToSendMax] = SEC_F;
760
761 // Convert from last byte pos to length
762 ToSendMax++;
763 }
764
765 //-----------------------------------------------------------------------------
766 // Wait for commands from reader
767 // Stop when button is pressed
768 // Or return TRUE when command is captured
769 //-----------------------------------------------------------------------------
770 static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len) {
771 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
772 // only, since we are receiving, not transmitting).
773 // Signal field is off with the appropriate LED
774 LED_D_OFF();
775 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
776
777 // Now run a `software UART` on the stream of incoming samples.
778 UartInit(received, parity);
779
780 // clear RXRDY:
781 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
782
783 for(;;) {
784 WDT_HIT();
785
786 if(BUTTON_PRESS()) return FALSE;
787
788 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
789 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
790 if(MillerDecoding(b, 0)) {
791 *len = Uart.len;
792 return TRUE;
793 }
794 }
795 }
796 }
797
798 bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
799 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
800 // This will need the following byte array for a modulation sequence
801 // 144 data bits (18 * 8)
802 // 18 parity bits
803 // 2 Start and stop
804 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
805 // 1 just for the case
806 // ----------- +
807 // 166 bytes, since every bit that needs to be send costs us a byte
808 //
809 // Prepare the tag modulation bits from the message
810 CodeIso14443aAsTag(response_info->response,response_info->response_n);
811
812 // Make sure we do not exceed the free buffer space
813 if (ToSendMax > max_buffer_size) {
814 Dbprintf("Out of memory, when modulating bits for tag answer:");
815 Dbhexdump(response_info->response_n,response_info->response,false);
816 return FALSE;
817 }
818
819 // Copy the byte array, used for this modulation to the buffer position
820 memcpy(response_info->modulation,ToSend,ToSendMax);
821
822 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
823 response_info->modulation_n = ToSendMax;
824 response_info->ProxToAirDuration = LastProxToAirDuration;
825 return TRUE;
826 }
827
828 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
829 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
830 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
831 // -> need 273 bytes buffer
832 // 44 * 8 data bits, 44 * 1 parity bits, 9 start bits, 9 stop bits, 9 correction bits --370
833 // 47 * 8 data bits, 47 * 1 parity bits, 10 start bits, 10 stop bits, 10 correction bits
834 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 453
835
836 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
837 // Retrieve and store the current buffer index
838 response_info->modulation = free_buffer_pointer;
839
840 // Determine the maximum size we can use from our buffer
841 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
842
843 // Forward the prepare tag modulation function to the inner function
844 if (prepare_tag_modulation(response_info, max_buffer_size)) {
845 // Update the free buffer offset
846 free_buffer_pointer += ToSendMax;
847 return true;
848 } else {
849 return false;
850 }
851 }
852
853 //-----------------------------------------------------------------------------
854 // Main loop of simulated tag: receive commands from reader, decide what
855 // response to send, and send it.
856 //-----------------------------------------------------------------------------
857 void SimulateIso14443aTag(int tagType, int flags, byte_t* data) {
858
859 //Here, we collect CUID, NT, AR, NR, NT2, AR2, NR2
860 // This can be used in a reader-only attack.
861 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0,0,0};
862 uint8_t ar_nr_collected = 0;
863 uint8_t sak = 0;
864
865 // PACK response to PWD AUTH for EV1/NTAG
866 uint8_t response8[4] = {0,0,0,0};
867 // Counter for EV1/NTAG
868 uint32_t counters[] = {0,0,0};
869
870 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
871 uint8_t response1[] = {0,0};
872
873 switch (tagType) {
874 case 1: { // MIFARE Classic 1k
875 response1[0] = 0x04;
876 sak = 0x08;
877 } break;
878 case 2: { // MIFARE Ultralight
879 response1[0] = 0x44;
880 sak = 0x00;
881 } break;
882 case 3: { // MIFARE DESFire
883 response1[0] = 0x04;
884 response1[1] = 0x03;
885 sak = 0x20;
886 } break;
887 case 4: { // ISO/IEC 14443-4 - javacard (JCOP)
888 response1[0] = 0x04;
889 sak = 0x28;
890 } break;
891 case 5: { // MIFARE TNP3XXX
892 response1[0] = 0x01;
893 response1[1] = 0x0f;
894 sak = 0x01;
895 } break;
896 case 6: { // MIFARE Mini 320b
897 response1[0] = 0x44;
898 sak = 0x09;
899 } break;
900 case 7: { // NTAG
901 response1[0] = 0x44;
902 sak = 0x00;
903 // PACK
904 response8[0] = 0x80;
905 response8[1] = 0x80;
906 ComputeCrc14443(CRC_14443_A, response8, 2, &response8[2], &response8[3]);
907 // uid not supplied then get from emulator memory
908 if (data[0]==0) {
909 uint16_t start = 4 * (0+12);
910 uint8_t emdata[8];
911 emlGetMemBt( emdata, start, sizeof(emdata));
912 memcpy(data, emdata, 3); //uid bytes 0-2
913 memcpy(data+3, emdata+4, 4); //uid bytes 3-7
914 flags |= FLAG_7B_UID_IN_DATA;
915 }
916 } break;
917 default: {
918 Dbprintf("Error: unkown tagtype (%d)",tagType);
919 return;
920 } break;
921 }
922
923 // The second response contains the (mandatory) first 24 bits of the UID
924 uint8_t response2[5] = {0x00};
925
926 // For UID size 7,
927 uint8_t response2a[5] = {0x00};
928
929 if (flags & FLAG_7B_UID_IN_DATA) {
930 response2[0] = 0x88; // Cascade Tag marker
931 response2[1] = data[0];
932 response2[2] = data[1];
933 response2[3] = data[2];
934
935 response2a[0] = data[3];
936 response2a[1] = data[4];
937 response2a[2] = data[5];
938 response2a[3] = data[6]; //??
939 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
940
941 // Configure the ATQA and SAK accordingly
942 response1[0] |= 0x40;
943 sak |= 0x04;
944 } else {
945 memcpy(response2, data, 4);
946 // Configure the ATQA and SAK accordingly
947 response1[0] &= 0xBF;
948 sak &= 0xFB;
949 }
950
951 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
952 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
953
954 // Prepare the mandatory SAK (for 4 and 7 byte UID)
955 uint8_t response3[3] = {sak, 0x00, 0x00};
956 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
957
958 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
959 uint8_t response3a[3] = {0x00};
960 response3a[0] = sak & 0xFB;
961 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
962
963 uint8_t response5[] = { 0x01, 0x01, 0x01, 0x01 }; // Very random tag nonce
964 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
965 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
966 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
967 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
968 // TC(1) = 0x02: CID supported, NAD not supported
969 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
970
971 // Prepare GET_VERSION (different for UL EV-1 / NTAG)
972 //uint8_t response7_EV1[] = {0x00, 0x04, 0x03, 0x01, 0x01, 0x00, 0x0b, 0x03, 0xfd, 0xf7}; //EV1 48bytes VERSION.
973 //uint8_t response7_NTAG[] = {0x00, 0x04, 0x04, 0x02, 0x01, 0x00, 0x11, 0x03, 0x01, 0x9e}; //NTAG 215
974 // Prepare CHK_TEARING
975 //uint8_t response9[] = {0xBD,0x90,0x3f};
976
977 #define TAG_RESPONSE_COUNT 10
978 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
979 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
980 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
981 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
982 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
983 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
984 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
985 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
986
987 { .response = response8, .response_n = sizeof(response8) } // EV1/NTAG PACK response
988 };
989 //{ .response = response7_NTAG, .response_n = sizeof(response7_NTAG)}, // EV1/NTAG GET_VERSION response
990 //{ .response = response9, .response_n = sizeof(response9) } // EV1/NTAG CHK_TEAR response
991
992
993 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
994 // Such a response is less time critical, so we can prepare them on the fly
995 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
996 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
997 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
998 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
999 tag_response_info_t dynamic_response_info = {
1000 .response = dynamic_response_buffer,
1001 .response_n = 0,
1002 .modulation = dynamic_modulation_buffer,
1003 .modulation_n = 0
1004 };
1005
1006 // We need to listen to the high-frequency, peak-detected path.
1007 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1008
1009 BigBuf_free_keep_EM();
1010 clear_trace();
1011 set_tracing(TRUE);
1012
1013 // allocate buffers:
1014 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1015 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1016 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1017
1018 // Prepare the responses of the anticollision phase
1019 // there will be not enough time to do this at the moment the reader sends it REQA
1020 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++)
1021 prepare_allocated_tag_modulation(&responses[i]);
1022
1023 int len = 0;
1024
1025 // To control where we are in the protocol
1026 int order = 0;
1027 int lastorder;
1028
1029 // Just to allow some checks
1030 int happened = 0;
1031 int happened2 = 0;
1032 int cmdsRecvd = 0;
1033 tag_response_info_t* p_response;
1034
1035 LED_A_ON();
1036 for(;;) {
1037 WDT_HIT();
1038
1039 // Clean receive command buffer
1040 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
1041 DbpString("Button press");
1042 break;
1043 }
1044
1045 p_response = NULL;
1046
1047 // Okay, look at the command now.
1048 lastorder = order;
1049 if(receivedCmd[0] == ISO14443A_CMD_REQA) { // Received a REQUEST
1050 p_response = &responses[0]; order = 1;
1051 } else if(receivedCmd[0] == ISO14443A_CMD_WUPA) { // Received a WAKEUP
1052 p_response = &responses[0]; order = 6;
1053 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT) { // Received request for UID (cascade 1)
1054 p_response = &responses[1]; order = 2;
1055 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2) { // Received request for UID (cascade 2)
1056 p_response = &responses[2]; order = 20;
1057 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT) { // Received a SELECT (cascade 1)
1058 p_response = &responses[3]; order = 3;
1059 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2) { // Received a SELECT (cascade 2)
1060 p_response = &responses[4]; order = 30;
1061 } else if(receivedCmd[0] == ISO14443A_CMD_READBLOCK) { // Received a (plain) READ
1062 uint8_t block = receivedCmd[1];
1063 // if Ultralight or NTAG (4 byte blocks)
1064 if ( tagType == 7 || tagType == 2 ) {
1065 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1066 uint16_t start = 4 * (block+12);
1067 uint8_t emdata[MAX_MIFARE_FRAME_SIZE];
1068 emlGetMemBt( emdata, start, 16);
1069 AppendCrc14443a(emdata, 16);
1070 EmSendCmdEx(emdata, sizeof(emdata), false);
1071 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1072 p_response = NULL;
1073 } else { // all other tags (16 byte block tags)
1074 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
1075 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1076 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1077 p_response = NULL;
1078 }
1079 } else if(receivedCmd[0] == MIFARE_ULEV1_FASTREAD) { // Received a FAST READ (ranged read)
1080 uint8_t emdata[MAX_FRAME_SIZE];
1081 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1082 int start = (receivedCmd[1]+12) * 4;
1083 int len = (receivedCmd[2] - receivedCmd[1] + 1) * 4;
1084 emlGetMemBt( emdata, start, len);
1085 AppendCrc14443a(emdata, len);
1086 EmSendCmdEx(emdata, len+2, false);
1087 p_response = NULL;
1088 } else if(receivedCmd[0] == MIFARE_ULEV1_READSIG && tagType == 7) { // Received a READ SIGNATURE --
1089 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1090 uint16_t start = 4 * 4;
1091 uint8_t emdata[34];
1092 emlGetMemBt( emdata, start, 32);
1093 AppendCrc14443a(emdata, 32);
1094 EmSendCmdEx(emdata, sizeof(emdata), false);
1095 p_response = NULL;
1096 } else if (receivedCmd[0] == MIFARE_ULEV1_READ_CNT && tagType == 7) { // Received a READ COUNTER --
1097 uint8_t index = receivedCmd[1];
1098 uint8_t data[] = {0x00,0x00,0x00,0x14,0xa5};
1099 if ( counters[index] > 0) {
1100 num_to_bytes(counters[index], 3, data);
1101 AppendCrc14443a(data, sizeof(data)-2);
1102 }
1103 EmSendCmdEx(data,sizeof(data),false);
1104 p_response = NULL;
1105 } else if (receivedCmd[0] == MIFARE_ULEV1_INCR_CNT && tagType == 7) { // Received a INC COUNTER --
1106 // number of counter
1107 uint8_t counter = receivedCmd[1];
1108 uint32_t val = bytes_to_num(receivedCmd+2,4);
1109 counters[counter] = val;
1110
1111 // send ACK
1112 uint8_t ack[] = {0x0a};
1113 EmSendCmdEx(ack,sizeof(ack),false);
1114 p_response = NULL;
1115 } else if(receivedCmd[0] == MIFARE_ULEV1_CHECKTEAR && tagType == 7) { // Received a CHECK_TEARING_EVENT --
1116 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1117 uint8_t emdata[3];
1118 uint8_t counter=0;
1119 if (receivedCmd[1]<3) counter = receivedCmd[1];
1120 emlGetMemBt( emdata, 10+counter, 1);
1121 AppendCrc14443a(emdata, sizeof(emdata)-2);
1122 EmSendCmdEx(emdata, sizeof(emdata), false);
1123 p_response = NULL;
1124 } else if(receivedCmd[0] == ISO14443A_CMD_HALT) { // Received a HALT
1125 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1126 p_response = NULL;
1127 } else if(receivedCmd[0] == MIFARE_AUTH_KEYA || receivedCmd[0] == MIFARE_AUTH_KEYB) { // Received an authentication request
1128
1129 if ( tagType == 7 ) { // IF NTAG /EV1 0x60 == GET_VERSION, not a authentication request.
1130 uint8_t emdata[10];
1131 emlGetMemBt( emdata, 0, 8 );
1132 AppendCrc14443a(emdata, sizeof(emdata)-2);
1133 EmSendCmdEx(emdata, sizeof(emdata), false);
1134 p_response = NULL;
1135 } else {
1136 p_response = &responses[5]; order = 7;
1137 }
1138 } else if(receivedCmd[0] == ISO14443A_CMD_RATS) { // Received a RATS request
1139 if (tagType == 1 || tagType == 2) { // RATS not supported
1140 EmSend4bit(CARD_NACK_NA);
1141 p_response = NULL;
1142 } else {
1143 p_response = &responses[6]; order = 70;
1144 }
1145 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
1146 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1147 uint32_t nonce = bytes_to_num(response5,4);
1148 uint32_t nr = bytes_to_num(receivedCmd,4);
1149 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1150
1151 if(flags & FLAG_NR_AR_ATTACK ) {
1152 if(ar_nr_collected < 2){
1153 // Avoid duplicates... probably not necessary, nr should vary.
1154 //if(ar_nr_responses[3] != nr){
1155 ar_nr_responses[ar_nr_collected*4] = 0;
1156 ar_nr_responses[ar_nr_collected*4+1] = nonce;
1157 ar_nr_responses[ar_nr_collected*4+2] = nr;
1158 ar_nr_responses[ar_nr_collected*4+3] = ar;
1159 ar_nr_collected++;
1160 //}
1161 }
1162
1163 if(ar_nr_collected > 1 ) {
1164 if (MF_DBGLEVEL >= 2) {
1165 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
1166 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
1167 ar_nr_responses[0], // CUID
1168 ar_nr_responses[1], // NT
1169 ar_nr_responses[2], // AR1
1170 ar_nr_responses[3], // NR1
1171 ar_nr_responses[6], // AR2
1172 ar_nr_responses[7] // NR2
1173 );
1174 }
1175 uint8_t len = ar_nr_collected*5*4;
1176 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,len,0,&ar_nr_responses,len);
1177 ar_nr_collected = 0;
1178 memset(ar_nr_responses, 0x00, len);
1179 }
1180 }
1181 } else if (receivedCmd[0] == MIFARE_ULC_AUTH_1 ) { // ULC authentication, or Desfire Authentication
1182 } else if (receivedCmd[0] == MIFARE_ULEV1_AUTH) { // NTAG / EV-1 authentication
1183 if ( tagType == 7 ) {
1184 uint16_t start = 13; //first 4 blocks of emu are [getversion answer - check tearing - pack - 0x00]
1185 uint8_t emdata[4];
1186 emlGetMemBt( emdata, start, 2);
1187 AppendCrc14443a(emdata, 2);
1188 EmSendCmdEx(emdata, sizeof(emdata), false);
1189 p_response = NULL;
1190 uint32_t pwd = bytes_to_num(receivedCmd+1,4);
1191
1192 if ( MF_DBGLEVEL >= 3) Dbprintf("Auth attempt: %08x", pwd);
1193 }
1194 } else {
1195 // Check for ISO 14443A-4 compliant commands, look at left nibble
1196 switch (receivedCmd[0]) {
1197 case 0x02:
1198 case 0x03: { // IBlock (command no CID)
1199 dynamic_response_info.response[0] = receivedCmd[0];
1200 dynamic_response_info.response[1] = 0x90;
1201 dynamic_response_info.response[2] = 0x00;
1202 dynamic_response_info.response_n = 3;
1203 } break;
1204 case 0x0B:
1205 case 0x0A: { // IBlock (command CID)
1206 dynamic_response_info.response[0] = receivedCmd[0];
1207 dynamic_response_info.response[1] = 0x00;
1208 dynamic_response_info.response[2] = 0x90;
1209 dynamic_response_info.response[3] = 0x00;
1210 dynamic_response_info.response_n = 4;
1211 } break;
1212
1213 case 0x1A:
1214 case 0x1B: { // Chaining command
1215 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1216 dynamic_response_info.response_n = 2;
1217 } break;
1218
1219 case 0xaa:
1220 case 0xbb: {
1221 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1222 dynamic_response_info.response_n = 2;
1223 } break;
1224
1225 case 0xBA: { // ping / pong
1226 dynamic_response_info.response[0] = 0xAB;
1227 dynamic_response_info.response[1] = 0x00;
1228 dynamic_response_info.response_n = 2;
1229 } break;
1230
1231 case 0xCA:
1232 case 0xC2: { // Readers sends deselect command
1233 dynamic_response_info.response[0] = 0xCA;
1234 dynamic_response_info.response[1] = 0x00;
1235 dynamic_response_info.response_n = 2;
1236 } break;
1237
1238 default: {
1239 // Never seen this command before
1240 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1241 Dbprintf("Received unknown command (len=%d):",len);
1242 Dbhexdump(len,receivedCmd,false);
1243 // Do not respond
1244 dynamic_response_info.response_n = 0;
1245 } break;
1246 }
1247
1248 if (dynamic_response_info.response_n > 0) {
1249 // Copy the CID from the reader query
1250 dynamic_response_info.response[1] = receivedCmd[1];
1251
1252 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1253 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1254 dynamic_response_info.response_n += 2;
1255
1256 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1257 Dbprintf("Error preparing tag response");
1258 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1259 break;
1260 }
1261 p_response = &dynamic_response_info;
1262 }
1263 }
1264
1265 // Count number of wakeups received after a halt
1266 if(order == 6 && lastorder == 5) { happened++; }
1267
1268 // Count number of other messages after a halt
1269 if(order != 6 && lastorder == 5) { happened2++; }
1270
1271 // comment this limit if you want to simulation longer
1272 if(cmdsRecvd > 999) {
1273 DbpString("1000 commands later...");
1274 break;
1275 }
1276 cmdsRecvd++;
1277
1278 if (p_response != NULL) {
1279 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1280 // do the tracing for the previous reader request and this tag answer:
1281 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1282 GetParity(p_response->response, p_response->response_n, par);
1283
1284 EmLogTrace(Uart.output,
1285 Uart.len,
1286 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1287 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1288 Uart.parity,
1289 p_response->response,
1290 p_response->response_n,
1291 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1292 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1293 par);
1294 }
1295
1296 // comment this limit if you want to simulation longer
1297 if (!tracing) {
1298 Dbprintf("Trace Full. Simulation stopped.");
1299 break;
1300 }
1301 }
1302
1303 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1304 set_tracing(FALSE);
1305 BigBuf_free_keep_EM();
1306 LED_A_OFF();
1307
1308 if (MF_DBGLEVEL >= 4){
1309 Dbprintf("-[ Wake ups after halt [%d]", happened);
1310 Dbprintf("-[ Messages after halt [%d]", happened2);
1311 Dbprintf("-[ Num of received cmd [%d]", cmdsRecvd);
1312 }
1313 }
1314
1315 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1316 // of bits specified in the delay parameter.
1317 void PrepareDelayedTransfer(uint16_t delay) {
1318 delay &= 0x07;
1319 if (!delay) return;
1320
1321 uint8_t bitmask = 0;
1322 uint8_t bits_to_shift = 0;
1323 uint8_t bits_shifted = 0;
1324 uint16_t i = 0;
1325
1326 for (i = 0; i < delay; ++i)
1327 bitmask |= (0x01 << i);
1328
1329 ToSend[++ToSendMax] = 0x00;
1330
1331 for (i = 0; i < ToSendMax; ++i) {
1332 bits_to_shift = ToSend[i] & bitmask;
1333 ToSend[i] = ToSend[i] >> delay;
1334 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1335 bits_shifted = bits_to_shift;
1336 }
1337 }
1338
1339
1340 //-------------------------------------------------------------------------------------
1341 // Transmit the command (to the tag) that was placed in ToSend[].
1342 // Parameter timing:
1343 // if NULL: transfer at next possible time, taking into account
1344 // request guard time and frame delay time
1345 // if == 0: transfer immediately and return time of transfer
1346 // if != 0: delay transfer until time specified
1347 //-------------------------------------------------------------------------------------
1348 static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing) {
1349 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1350
1351 uint32_t ThisTransferTime = 0;
1352
1353 if (timing) {
1354 if(*timing == 0) { // Measure time
1355 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1356 } else {
1357 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1358 }
1359 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1360 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1361 LastTimeProxToAirStart = *timing;
1362 } else {
1363 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1364
1365 while(GetCountSspClk() < ThisTransferTime);
1366
1367 LastTimeProxToAirStart = ThisTransferTime;
1368 }
1369
1370 // clear TXRDY
1371 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1372
1373 uint16_t c = 0;
1374 for(;;) {
1375 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1376 AT91C_BASE_SSC->SSC_THR = cmd[c];
1377 ++c;
1378 if(c >= len)
1379 break;
1380 }
1381 }
1382
1383 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1384 }
1385
1386 //-----------------------------------------------------------------------------
1387 // Prepare reader command (in bits, support short frames) to send to FPGA
1388 //-----------------------------------------------------------------------------
1389 void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
1390 {
1391 int i, j;
1392 int last = 0;
1393 uint8_t b;
1394
1395 ToSendReset();
1396
1397 // Start of Communication (Seq. Z)
1398 ToSend[++ToSendMax] = SEC_Z;
1399 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1400
1401 size_t bytecount = nbytes(bits);
1402 // Generate send structure for the data bits
1403 for (i = 0; i < bytecount; i++) {
1404 // Get the current byte to send
1405 b = cmd[i];
1406 size_t bitsleft = MIN((bits-(i*8)),8);
1407
1408 for (j = 0; j < bitsleft; j++) {
1409 if (b & 1) {
1410 // Sequence X
1411 ToSend[++ToSendMax] = SEC_X;
1412 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1413 last = 1;
1414 } else {
1415 if (last == 0) {
1416 // Sequence Z
1417 ToSend[++ToSendMax] = SEC_Z;
1418 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1419 } else {
1420 // Sequence Y
1421 ToSend[++ToSendMax] = SEC_Y;
1422 last = 0;
1423 }
1424 }
1425 b >>= 1;
1426 }
1427
1428 // Only transmit parity bit if we transmitted a complete byte
1429 if (j == 8 && parity != NULL) {
1430 // Get the parity bit
1431 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
1432 // Sequence X
1433 ToSend[++ToSendMax] = SEC_X;
1434 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1435 last = 1;
1436 } else {
1437 if (last == 0) {
1438 // Sequence Z
1439 ToSend[++ToSendMax] = SEC_Z;
1440 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1441 } else {
1442 // Sequence Y
1443 ToSend[++ToSendMax] = SEC_Y;
1444 last = 0;
1445 }
1446 }
1447 }
1448 }
1449
1450 // End of Communication: Logic 0 followed by Sequence Y
1451 if (last == 0) {
1452 // Sequence Z
1453 ToSend[++ToSendMax] = SEC_Z;
1454 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1455 } else {
1456 // Sequence Y
1457 ToSend[++ToSendMax] = SEC_Y;
1458 last = 0;
1459 }
1460 ToSend[++ToSendMax] = SEC_Y;
1461
1462 // Convert to length of command:
1463 ++ToSendMax;
1464 }
1465
1466 //-----------------------------------------------------------------------------
1467 // Prepare reader command to send to FPGA
1468 //-----------------------------------------------------------------------------
1469 void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity) {
1470 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
1471 }
1472
1473 //-----------------------------------------------------------------------------
1474 // Wait for commands from reader
1475 // Stop when button is pressed (return 1) or field was gone (return 2)
1476 // Or return 0 when command is captured
1477 //-----------------------------------------------------------------------------
1478 static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity) {
1479 *len = 0;
1480
1481 uint32_t timer = 0, vtime = 0;
1482 int analogCnt = 0;
1483 int analogAVG = 0;
1484
1485 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1486 // only, since we are receiving, not transmitting).
1487 // Signal field is off with the appropriate LED
1488 LED_D_OFF();
1489 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1490
1491 // Set ADC to read field strength
1492 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1493 AT91C_BASE_ADC->ADC_MR =
1494 ADC_MODE_PRESCALE(63) |
1495 ADC_MODE_STARTUP_TIME(1) |
1496 ADC_MODE_SAMPLE_HOLD_TIME(15);
1497 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1498 // start ADC
1499 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1500
1501 // Now run a 'software UART' on the stream of incoming samples.
1502 UartInit(received, parity);
1503
1504 // Clear RXRDY:
1505 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1506
1507 for(;;) {
1508 WDT_HIT();
1509
1510 if (BUTTON_PRESS()) return 1;
1511
1512 // test if the field exists
1513 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1514 analogCnt++;
1515 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1516 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1517 if (analogCnt >= 32) {
1518 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1519 vtime = GetTickCount();
1520 if (!timer) timer = vtime;
1521 // 50ms no field --> card to idle state
1522 if (vtime - timer > 50) return 2;
1523 } else
1524 if (timer) timer = 0;
1525 analogCnt = 0;
1526 analogAVG = 0;
1527 }
1528 }
1529
1530 // receive and test the miller decoding
1531 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1532 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1533 if(MillerDecoding(b, 0)) {
1534 *len = Uart.len;
1535 return 0;
1536 }
1537 }
1538 }
1539 }
1540
1541 int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded) {
1542 uint8_t b;
1543 uint16_t i = 0;
1544 uint32_t ThisTransferTime;
1545
1546 // Modulate Manchester
1547 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1548
1549 // include correction bit if necessary
1550 if (Uart.parityBits & 0x01) {
1551 correctionNeeded = TRUE;
1552 }
1553 // 1236, so correction bit needed
1554 i = (correctionNeeded) ? 0 : 1;
1555
1556 // clear receiving shift register and holding register
1557 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1558 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1559 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1560 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1561
1562 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1563 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1564 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1565 if (AT91C_BASE_SSC->SSC_RHR) break;
1566 }
1567
1568 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1569
1570 // Clear TXRDY:
1571 AT91C_BASE_SSC->SSC_THR = SEC_F;
1572
1573 // send cycle
1574 for(; i < respLen; ) {
1575 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1576 AT91C_BASE_SSC->SSC_THR = resp[i++];
1577 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1578 }
1579
1580 if(BUTTON_PRESS()) break;
1581 }
1582
1583 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1584 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3; // twich /8 ?? >>3,
1585 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
1586 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1587 AT91C_BASE_SSC->SSC_THR = SEC_F;
1588 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1589 i++;
1590 }
1591 }
1592 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1593 return 0;
1594 }
1595
1596 int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1597 Code4bitAnswerAsTag(resp);
1598 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1599 // do the tracing for the previous reader request and this tag answer:
1600 uint8_t par[1] = {0x00};
1601 GetParity(&resp, 1, par);
1602 EmLogTrace(Uart.output,
1603 Uart.len,
1604 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1605 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1606 Uart.parity,
1607 &resp,
1608 1,
1609 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1610 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1611 par);
1612 return res;
1613 }
1614
1615 int EmSend4bit(uint8_t resp){
1616 return EmSend4bitEx(resp, false);
1617 }
1618
1619 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
1620 CodeIso14443aAsTagPar(resp, respLen, par);
1621 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1622 // do the tracing for the previous reader request and this tag answer:
1623 EmLogTrace(Uart.output,
1624 Uart.len,
1625 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1626 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1627 Uart.parity,
1628 resp,
1629 respLen,
1630 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1631 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1632 par);
1633 return res;
1634 }
1635
1636 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1637 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1638 GetParity(resp, respLen, par);
1639 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
1640 }
1641
1642 int EmSendCmd(uint8_t *resp, uint16_t respLen){
1643 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1644 GetParity(resp, respLen, par);
1645 return EmSendCmdExPar(resp, respLen, false, par);
1646 }
1647
1648 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
1649 return EmSendCmdExPar(resp, respLen, false, par);
1650 }
1651
1652 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1653 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
1654 {
1655 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1656 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1657 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1658 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1659 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1660 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1661 reader_EndTime = tag_StartTime - exact_fdt;
1662 reader_StartTime = reader_EndTime - reader_modlen;
1663
1664 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE))
1665 return FALSE;
1666 else
1667 return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1668
1669 }
1670
1671 //-----------------------------------------------------------------------------
1672 // Wait a certain time for tag response
1673 // If a response is captured return TRUE
1674 // If it takes too long return FALSE
1675 //-----------------------------------------------------------------------------
1676 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset) {
1677 uint32_t c = 0x00;
1678
1679 // Set FPGA mode to "reader listen mode", no modulation (listen
1680 // only, since we are receiving, not transmitting).
1681 // Signal field is on with the appropriate LED
1682 LED_D_ON();
1683 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1684
1685 // Now get the answer from the card
1686 DemodInit(receivedResponse, receivedResponsePar);
1687
1688 // clear RXRDY:
1689 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1690
1691 for(;;) {
1692 WDT_HIT();
1693
1694 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1695 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1696 if(ManchesterDecoding(b, offset, 0)) {
1697 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1698 return TRUE;
1699 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
1700 return FALSE;
1701 }
1702 }
1703 }
1704 }
1705
1706 void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing) {
1707 CodeIso14443aBitsAsReaderPar(frame, bits, par);
1708
1709 // Send command to tag
1710 TransmitFor14443a(ToSend, ToSendMax, timing);
1711 if(trigger) LED_A_ON();
1712
1713 // Log reader command in trace buffer
1714 //LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
1715 LogTrace(frame, nbytes(bits), (LastTimeProxToAirStart<<4) + DELAY_ARM2AIR_AS_READER, ((LastTimeProxToAirStart + LastProxToAirDuration)<<4) + DELAY_ARM2AIR_AS_READER, par, TRUE);
1716 }
1717
1718 void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing) {
1719 ReaderTransmitBitsPar(frame, len*8, par, timing);
1720 }
1721
1722 void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing) {
1723 // Generate parity and redirect
1724 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1725 GetParity(frame, len/8, par);
1726 ReaderTransmitBitsPar(frame, len, par, timing);
1727 }
1728
1729 void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing) {
1730 // Generate parity and redirect
1731 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1732 GetParity(frame, len, par);
1733 ReaderTransmitBitsPar(frame, len*8, par, timing);
1734 }
1735
1736 int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity) {
1737 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset))
1738 return FALSE;
1739 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1740 return Demod.len;
1741 }
1742
1743 int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity) {
1744 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0))
1745 return FALSE;
1746 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1747 return Demod.len;
1748 }
1749
1750 // performs iso14443a anticollision (optional) and card select procedure
1751 // fills the uid and cuid pointer unless NULL
1752 // fills the card info record unless NULL
1753 // if anticollision is false, then the UID must be provided in uid_ptr[]
1754 // and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
1755 int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr, bool anticollision, uint8_t num_cascades) {
1756 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1757 uint8_t sel_all[] = { 0x93,0x20 };
1758 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1759 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1760 uint8_t resp[MAX_FRAME_SIZE] = {0}; // theoretically. A usual RATS will be much smaller
1761 uint8_t resp_par[MAX_PARITY_SIZE] = {0};
1762 byte_t uid_resp[4] = {0};
1763 size_t uid_resp_len = 0;
1764
1765 uint8_t sak = 0x04; // cascade uid
1766 int cascade_level = 0;
1767 int len;
1768
1769 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1770 ReaderTransmitBitsPar(wupa, 7, NULL, NULL);
1771
1772 // Receive the ATQA
1773 if(!ReaderReceive(resp, resp_par)) return 0;
1774
1775 if(p_hi14a_card) {
1776 memcpy(p_hi14a_card->atqa, resp, 2);
1777 p_hi14a_card->uidlen = 0;
1778 memset(p_hi14a_card->uid,0,10);
1779 }
1780
1781 if (anticollision) {
1782 // clear uid
1783 if (uid_ptr)
1784 memset(uid_ptr,0,10);
1785 }
1786
1787 // check for proprietary anticollision:
1788 if ((resp[0] & 0x1F) == 0) return 3;
1789
1790 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1791 // which case we need to make a cascade 2 request and select - this is a long UID
1792 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1793 for(; sak & 0x04; cascade_level++) {
1794 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1795 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1796
1797 if (anticollision) {
1798 // SELECT_ALL
1799 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1800 if (!ReaderReceive(resp, resp_par)) return 0;
1801
1802 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1803 memset(uid_resp, 0, 4);
1804 uint16_t uid_resp_bits = 0;
1805 uint16_t collision_answer_offset = 0;
1806 // anti-collision-loop:
1807 while (Demod.collisionPos) {
1808 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1809 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1810 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1811 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1812 }
1813 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1814 uid_resp_bits++;
1815 // construct anticollosion command:
1816 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1817 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1818 sel_uid[2+i] = uid_resp[i];
1819 }
1820 collision_answer_offset = uid_resp_bits%8;
1821 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1822 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
1823 }
1824 // finally, add the last bits and BCC of the UID
1825 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1826 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1827 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1828 }
1829
1830 } else { // no collision, use the response to SELECT_ALL as current uid
1831 memcpy(uid_resp, resp, 4);
1832 }
1833
1834 } else {
1835 if (cascade_level < num_cascades - 1) {
1836 uid_resp[0] = 0x88;
1837 memcpy(uid_resp+1, uid_ptr+cascade_level*3, 3);
1838 } else {
1839 memcpy(uid_resp, uid_ptr+cascade_level*3, 4);
1840 }
1841 }
1842 uid_resp_len = 4;
1843
1844 // calculate crypto UID. Always use last 4 Bytes.
1845 if(cuid_ptr)
1846 *cuid_ptr = bytes_to_num(uid_resp, 4);
1847
1848 // Construct SELECT UID command
1849 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1850 memcpy(sel_uid+2, uid_resp, 4); // the UID received during anticollision, or the provided UID
1851 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1852 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1853 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1854
1855 // Receive the SAK
1856 if (!ReaderReceive(resp, resp_par)) return 0;
1857
1858 sak = resp[0];
1859
1860 // Test if more parts of the uid are coming
1861 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1862 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1863 // http://www.nxp.com/documents/application_note/AN10927.pdf
1864 uid_resp[0] = uid_resp[1];
1865 uid_resp[1] = uid_resp[2];
1866 uid_resp[2] = uid_resp[3];
1867 uid_resp_len = 3;
1868 }
1869
1870 if(uid_ptr && anticollision)
1871 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1872
1873 if(p_hi14a_card) {
1874 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1875 p_hi14a_card->uidlen += uid_resp_len;
1876 }
1877 }
1878
1879 if(p_hi14a_card) {
1880 p_hi14a_card->sak = sak;
1881 p_hi14a_card->ats_len = 0;
1882 }
1883
1884 // non iso14443a compliant tag
1885 if( (sak & 0x20) == 0) return 2;
1886
1887 // Request for answer to select
1888 AppendCrc14443a(rats, 2);
1889 ReaderTransmit(rats, sizeof(rats), NULL);
1890
1891 if (!(len = ReaderReceive(resp, resp_par))) return 0;
1892
1893 if(p_hi14a_card) {
1894 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1895 p_hi14a_card->ats_len = len;
1896 }
1897
1898 // reset the PCB block number
1899 iso14_pcb_blocknum = 0;
1900
1901 // set default timeout based on ATS
1902 iso14a_set_ATS_timeout(resp);
1903
1904 return 1;
1905 }
1906
1907 void iso14443a_setup(uint8_t fpga_minor_mode) {
1908 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1909 // Set up the synchronous serial port
1910 FpgaSetupSsc();
1911 // connect Demodulated Signal to ADC:
1912 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1913
1914 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
1915
1916 LED_D_OFF();
1917 // Signal field is on with the appropriate LED
1918 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD ||
1919 fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN)
1920 LED_D_ON();
1921
1922 // Prepare the demodulation functions
1923 DemodReset();
1924 UartReset();
1925
1926 iso14a_set_timeout(10*106); // 10ms default
1927
1928 //NextTransferTime = 2 * DELAY_ARM2AIR_AS_READER;
1929 NextTransferTime = DELAY_ARM2AIR_AS_READER << 1;
1930
1931 // Start the timer
1932 StartCountSspClk();
1933 }
1934
1935 int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1936 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1937 uint8_t real_cmd[cmd_len+4];
1938 real_cmd[0] = 0x0a; //I-Block
1939 // put block number into the PCB
1940 real_cmd[0] |= iso14_pcb_blocknum;
1941 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1942 memcpy(real_cmd+2, cmd, cmd_len);
1943 AppendCrc14443a(real_cmd,cmd_len+2);
1944
1945 ReaderTransmit(real_cmd, cmd_len+4, NULL);
1946 size_t len = ReaderReceive(data, parity);
1947 //DATA LINK ERROR
1948 if (!len) return 0;
1949
1950 uint8_t *data_bytes = (uint8_t *) data;
1951
1952 // if we received an I- or R(ACK)-Block with a block number equal to the
1953 // current block number, toggle the current block number
1954 if (len >= 4 // PCB+CID+CRC = 4 bytes
1955 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1956 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1957 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1958 {
1959 iso14_pcb_blocknum ^= 1;
1960 }
1961
1962 return len;
1963 }
1964
1965 //-----------------------------------------------------------------------------
1966 // Read an ISO 14443a tag. Send out commands and store answers.
1967 //
1968 //-----------------------------------------------------------------------------
1969 void ReaderIso14443a(UsbCommand *c) {
1970 iso14a_command_t param = c->arg[0];
1971 size_t len = c->arg[1] & 0xffff;
1972 size_t lenbits = c->arg[1] >> 16;
1973 uint32_t timeout = c->arg[2];
1974 uint8_t *cmd = c->d.asBytes;
1975 uint32_t arg0 = 0;
1976 byte_t buf[USB_CMD_DATA_SIZE] = {0x00};
1977 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1978
1979 if (param & ISO14A_CONNECT)
1980 clear_trace();
1981
1982 set_tracing(TRUE);
1983
1984 if (param & ISO14A_REQUEST_TRIGGER)
1985 iso14a_set_trigger(TRUE);
1986
1987 if (param & ISO14A_CONNECT) {
1988 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
1989 if(!(param & ISO14A_NO_SELECT)) {
1990 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1991 arg0 = iso14443a_select_card(NULL,card,NULL, true, 0);
1992 cmd_send(CMD_ACK, arg0, card->uidlen, 0, buf, sizeof(iso14a_card_select_t));
1993 // if it fails, the cmdhf14a.c client quites.. however this one still executes.
1994 if ( arg0 == 0 ) return;
1995 }
1996 }
1997
1998 if (param & ISO14A_SET_TIMEOUT)
1999 iso14a_set_timeout(timeout);
2000
2001 if (param & ISO14A_APDU) {
2002 arg0 = iso14_apdu(cmd, len, buf);
2003 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
2004 }
2005
2006 if (param & ISO14A_RAW) {
2007 if(param & ISO14A_APPEND_CRC) {
2008 if(param & ISO14A_TOPAZMODE) {
2009 AppendCrc14443b(cmd,len);
2010 } else {
2011 AppendCrc14443a(cmd,len);
2012 }
2013 len += 2;
2014 if (lenbits) lenbits += 16;
2015 }
2016 if(lenbits>0) { // want to send a specific number of bits (e.g. short commands)
2017 if(param & ISO14A_TOPAZMODE) {
2018 int bits_to_send = lenbits;
2019 uint16_t i = 0;
2020 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
2021 bits_to_send -= 7;
2022 while (bits_to_send > 0) {
2023 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
2024 bits_to_send -= 8;
2025 }
2026 } else {
2027 GetParity(cmd, lenbits/8, par);
2028 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
2029 }
2030 } else { // want to send complete bytes only
2031 if(param & ISO14A_TOPAZMODE) {
2032 uint16_t i = 0;
2033 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
2034 while (i < len) {
2035 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
2036 }
2037 } else {
2038 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
2039 }
2040 }
2041 arg0 = ReaderReceive(buf, par);
2042 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
2043 }
2044
2045 if (param & ISO14A_REQUEST_TRIGGER)
2046 iso14a_set_trigger(FALSE);
2047
2048 if (param & ISO14A_NO_DISCONNECT)
2049 return;
2050
2051 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2052 set_tracing(FALSE);
2053 LEDsoff();
2054 }
2055
2056 // Determine the distance between two nonces.
2057 // Assume that the difference is small, but we don't know which is first.
2058 // Therefore try in alternating directions.
2059 int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2060
2061 if (nt1 == nt2) return 0;
2062
2063 uint16_t i;
2064 uint32_t nttmp1 = nt1;
2065 uint32_t nttmp2 = nt2;
2066
2067 for (i = 1; i < (32768/8); ++i) {
2068 nttmp1 = prng_successor(nttmp1, 1);
2069 if (nttmp1 == nt2) return i;
2070 nttmp2 = prng_successor(nttmp2, 1);
2071 if (nttmp2 == nt1) return -i;
2072
2073 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+1;
2074 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+1);
2075 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+2;
2076 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+2);
2077 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+3;
2078 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+3);
2079 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+4;
2080 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+4);
2081 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+5;
2082 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+5);
2083 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+6;
2084 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+6);
2085 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+7;
2086 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+7);
2087 }
2088 // either nt1 or nt2 are invalid nonces
2089 return(-99999);
2090 }
2091
2092 //-----------------------------------------------------------------------------
2093 // Recover several bits of the cypher stream. This implements (first stages of)
2094 // the algorithm described in "The Dark Side of Security by Obscurity and
2095 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2096 // (article by Nicolas T. Courtois, 2009)
2097 //-----------------------------------------------------------------------------
2098 void ReaderMifare(bool first_try, uint8_t block ) {
2099 //uint8_t mf_auth[] = { MIFARE_AUTH_KEYA,0x00,0xf5,0x7b };
2100 uint8_t mf_auth[] = { MIFARE_AUTH_KEYA, block, 0x00, 0x00 };
2101 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2102 uint8_t uid[10] = {0,0,0,0,0,0,0,0,0,0};
2103 uint8_t par_list[8] = {0,0,0,0,0,0,0,0};
2104 uint8_t ks_list[8] = {0,0,0,0,0,0,0,0};
2105 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE] = {0x00};
2106 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
2107 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2108 byte_t nt_diff = 0;
2109 uint32_t nt = 0;
2110 uint32_t previous_nt = 0;
2111 uint32_t cuid = 0;
2112
2113 int32_t catch_up_cycles = 0;
2114 int32_t last_catch_up = 0;
2115 int32_t isOK = 0;
2116 int32_t nt_distance = 0;
2117
2118 uint16_t elapsed_prng_sequences = 1;
2119 uint16_t consecutive_resyncs = 0;
2120 uint16_t unexpected_random = 0;
2121 uint16_t sync_tries = 0;
2122
2123 // static variables here, is re-used in the next call?
2124 static uint32_t nt_attacked = 0;
2125 static uint32_t sync_time = 0;
2126 static uint32_t sync_cycles = 0;
2127 static uint8_t par_low = 0;
2128 static uint8_t mf_nr_ar3 = 0;
2129
2130 #define PRNG_SEQUENCE_LENGTH (1 << 16)
2131 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2132 #define MAX_SYNC_TRIES 32
2133 #define MAX_STRATEGY 3
2134
2135 BigBuf_free(); BigBuf_Clear_ext(false);
2136 clear_trace();
2137 set_tracing(TRUE);
2138 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2139
2140 AppendCrc14443a(mf_auth, 2);
2141
2142 if (first_try) {
2143 sync_time = GetCountSspClk() & 0xfffffff8;
2144 sync_cycles = PRNG_SEQUENCE_LENGTH + 1130; //65536; //0x10000 // Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
2145 mf_nr_ar3 = 0;
2146 nt_attacked = 0;
2147 par_low = 0;
2148
2149 Dbprintf("FIRST: sync_time - %08X", sync_time);
2150 } else {
2151 // we were unsuccessful on a previous call.
2152 // Try another READER nonce (first 3 parity bits remain the same)
2153 ++mf_nr_ar3;
2154 mf_nr_ar[3] = mf_nr_ar3;
2155 par[0] = par_low;
2156 }
2157
2158 bool have_uid = FALSE;
2159 uint8_t cascade_levels = 0;
2160
2161 LED_C_ON();
2162 uint16_t i;
2163 for(i = 0; TRUE; ++i) {
2164
2165 WDT_HIT();
2166
2167 // Test if the action was cancelled
2168 if(BUTTON_PRESS()) {
2169 isOK = -1;
2170 break;
2171 }
2172
2173 // this part is from Piwi's faster nonce collecting part in Hardnested.
2174 if (!have_uid) { // need a full select cycle to get the uid first
2175 iso14a_card_select_t card_info;
2176 if(!iso14443a_select_card(uid, &card_info, &cuid, true, 0)) {
2177 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (ALL)");
2178 break;
2179 }
2180 switch (card_info.uidlen) {
2181 case 4 : cascade_levels = 1; break;
2182 case 7 : cascade_levels = 2; break;
2183 case 10: cascade_levels = 3; break;
2184 default: break;
2185 }
2186 have_uid = TRUE;
2187 } else { // no need for anticollision. We can directly select the card
2188 if(!iso14443a_select_card(uid, NULL, &cuid, false, cascade_levels)) {
2189 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (UID)");
2190 continue;
2191 }
2192 }
2193
2194 // Sending timeslot of ISO14443a frame
2195 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles + catch_up_cycles;
2196 catch_up_cycles = 0;
2197
2198 // if we missed the sync time already, advance to the next nonce repeat
2199 while( GetCountSspClk() > sync_time) {
2200 ++elapsed_prng_sequences;
2201 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles;
2202 }
2203
2204 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2205 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2206
2207 // Receive the (4 Byte) "random" nonce from TAG
2208 if (!ReaderReceive(receivedAnswer, receivedAnswerPar))
2209 continue;
2210
2211 previous_nt = nt;
2212 nt = bytes_to_num(receivedAnswer, 4);
2213
2214 // Transmit reader nonce with fake par
2215 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2216
2217 WDT_HIT();
2218 LED_B_ON();
2219 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2220
2221 nt_distance = dist_nt(previous_nt, nt);
2222
2223 // if no distance between, then we are in sync.
2224 if (nt_distance == 0) {
2225 nt_attacked = nt;
2226 } else {
2227 if (nt_distance == -99999) { // invalid nonce received
2228 ++unexpected_random;
2229 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
2230 isOK = -3; // Card has an unpredictable PRNG. Give up
2231 break;
2232 } else {
2233 if (sync_cycles <= 0) sync_cycles += PRNG_SEQUENCE_LENGTH;
2234 LED_B_OFF();
2235 continue; // continue trying...
2236 }
2237 }
2238
2239 if (++sync_tries > MAX_SYNC_TRIES) {
2240 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2241 break;
2242 }
2243
2244 sync_cycles = (sync_cycles - nt_distance)/elapsed_prng_sequences;
2245
2246 if (sync_cycles <= 0)
2247 sync_cycles += PRNG_SEQUENCE_LENGTH;
2248
2249 if (MF_DBGLEVEL >= 4)
2250 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
2251
2252 LED_B_OFF();
2253 continue;
2254 }
2255 }
2256 LED_B_OFF();
2257
2258 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2259
2260 catch_up_cycles = ABS(dist_nt(nt_attacked, nt));
2261 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2262 catch_up_cycles = 0;
2263 continue;
2264 }
2265 // average?
2266 catch_up_cycles /= elapsed_prng_sequences;
2267
2268 if (catch_up_cycles == last_catch_up) {
2269 ++consecutive_resyncs;
2270 } else {
2271 last_catch_up = catch_up_cycles;
2272 consecutive_resyncs = 0;
2273 }
2274
2275 if (consecutive_resyncs < 3) {
2276 if (MF_DBGLEVEL >= 4)
2277 Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, catch_up_cycles, consecutive_resyncs);
2278 } else {
2279 sync_cycles += catch_up_cycles;
2280
2281 if (MF_DBGLEVEL >= 4)
2282 Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, catch_up_cycles, sync_cycles);
2283
2284 last_catch_up = 0;
2285 catch_up_cycles = 0;
2286 consecutive_resyncs = 0;
2287 }
2288 continue;
2289 }
2290
2291 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2292 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2293 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2294
2295 if (nt_diff == 0)
2296 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2297
2298 par_list[nt_diff] = SwapBits(par[0], 8);
2299 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05; // xor with NACK value to get keystream
2300
2301 // Test if the information is complete
2302 if (nt_diff == 0x07) {
2303 isOK = 1;
2304 break;
2305 }
2306
2307 nt_diff = (nt_diff + 1) & 0x07;
2308 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2309 par[0] = par_low;
2310
2311 } else {
2312 // No NACK.
2313 if (nt_diff == 0 && first_try) {
2314 par[0]++;
2315 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
2316 isOK = -2;
2317 break;
2318 }
2319 } else {
2320 // Why this?
2321 par[0] = ((par[0] & 0x1F) + 1) | par_low;
2322 }
2323 }
2324
2325 // reset the resyncs since we got a complete transaction on right time.
2326 consecutive_resyncs = 0;
2327 } // end for loop
2328
2329 mf_nr_ar[3] &= 0x1F;
2330
2331 if (MF_DBGLEVEL >= 1) Dbprintf("\nNumber of sent auth requestes: %u", i);
2332
2333 uint8_t buf[28] = {0x00};
2334 memset(buf, 0x00, sizeof(buf));
2335 num_to_bytes(cuid, 4, buf);
2336 num_to_bytes(nt, 4, buf + 4);
2337 memcpy(buf + 8, par_list, 8);
2338 memcpy(buf + 16, ks_list, 8);
2339 memcpy(buf + 24, mf_nr_ar, 4);
2340
2341 cmd_send(CMD_ACK, isOK, 0, 0, buf, sizeof(buf) );
2342
2343 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2344 LEDsoff();
2345 set_tracing(FALSE);
2346 }
2347
2348 /**
2349 *MIFARE 1K simulate.
2350 *
2351 *@param flags :
2352 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2353 * FLAG_4B_UID_IN_DATA - use 4-byte UID in the data-section
2354 * FLAG_7B_UID_IN_DATA - use 7-byte UID in the data-section
2355 * FLAG_10B_UID_IN_DATA - use 10-byte UID in the data-section
2356 * FLAG_UID_IN_EMUL - use 4-byte UID from emulator memory
2357 * FLAG_NR_AR_ATTACK - collect NR_AR responses for bruteforcing later
2358 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2359 */
2360 void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain) {
2361 int cardSTATE = MFEMUL_NOFIELD;
2362 int _UID_LEN = 0; // 4, 7, 10
2363 int vHf = 0; // in mV
2364 int res = 0;
2365 uint32_t selTimer = 0;
2366 uint32_t authTimer = 0;
2367 uint16_t len = 0;
2368 uint8_t cardWRBL = 0;
2369 uint8_t cardAUTHSC = 0;
2370 uint8_t cardAUTHKEY = 0xff; // no authentication
2371 uint32_t cuid = 0;
2372 uint32_t ans = 0;
2373 uint32_t cardINTREG = 0;
2374 uint8_t cardINTBLOCK = 0;
2375 struct Crypto1State mpcs = {0, 0};
2376 struct Crypto1State *pcs;
2377 pcs = &mpcs;
2378 uint32_t numReads = 0; //Counts numer of times reader read a block
2379 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
2380 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
2381 uint8_t response[MAX_MIFARE_FRAME_SIZE] = {0x00};
2382 uint8_t response_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
2383
2384 uint8_t atqa[] = {0x04, 0x00}; // Mifare classic 1k (4b UID)
2385 uint8_t sak_4[] = {0x08, 0x00, 0x00}; // Mifare Classic
2386 uint8_t sak_7[] = {0x08, 0x00, 0x00}; // CL2 - 7b uid
2387 uint8_t sak_10[] = {0x08, 0x00, 0x00}; // CL3 - 10b uid
2388 //uint8_t sak[] = {0x09, 0x3f, 0xcc }; // Mifare Mini
2389
2390 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2391 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2392 uint8_t rUIDBCC3[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2393
2394 uint8_t rAUTH_NT[] = {0x01, 0x01, 0x01, 0x01}; // very random nonce
2395 //uint8_t rAUTH_NT[] = {0x55, 0x41, 0x49, 0x92};// nonce from nested? why this?
2396 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
2397
2398 // Here, we collect CUID, NT, AR, NR, NT2, AR2, NR2
2399 // This can be used in a reader-only attack.
2400 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0};
2401 uint8_t ar_nr_collected = 0;
2402
2403 // Authenticate response - nonce
2404 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
2405
2406 //-- Determine the UID
2407 // Can be set from emulator memory or incoming data
2408 // Length: 4,7,or 10 bytes
2409 if ( flags & FLAG_UID_IN_EMUL ) {
2410 emlGetMemBt(rUIDBCC1, 0, 4);
2411 _UID_LEN = 4;
2412 } else if (flags & FLAG_4B_UID_IN_DATA) {
2413 memcpy(rUIDBCC1, datain, 4);
2414 _UID_LEN = 4;
2415 } else if (flags & FLAG_7B_UID_IN_DATA) {
2416 memcpy(&rUIDBCC1[1], datain, 3);
2417 memcpy( rUIDBCC2, datain+3, 4);
2418 _UID_LEN = 7;
2419 } else if (flags & FLAG_10B_UID_IN_DATA) {
2420 memcpy(&rUIDBCC1[1], datain, 3);
2421 memcpy(&rUIDBCC2[1], datain+3, 4);
2422 memcpy( rUIDBCC3, datain+7, 4);
2423 _UID_LEN = 10;
2424 }
2425
2426 /*
2427 * Save cuid to collected response array.
2428 * Set XOR BCC (fifth byte) and modify the ATQA for 4,7 or 10-byte UID
2429 atqa[] = 0x04, 0x00;
2430 sak = 0x08;
2431 if (flags & FLAG_7B_UID_IN_DATA) {
2432 atqa[0] |= 0x40;
2433 sak |= 0x04;
2434 } else {
2435 atqa[0] &= 0xBF;
2436 sak &= 0xFB;
2437
2438 // Prepare the mandatory SAK (for 4 and 7 byte UID)
2439 uint8_t response3[3] = {sak, 0x00, 0x00};
2440 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
2441 */
2442 switch (_UID_LEN) {
2443 case 4:
2444 atqa[0] &= 0xBF;
2445 sak_4[0] &= 0xFB;
2446 ComputeCrc14443(CRC_14443_A, sak_4, 1, &sak_4[1], &sak_4[2]);
2447
2448 // save CUID
2449 ar_nr_responses[0] = cuid = bytes_to_num(rUIDBCC1, 4);
2450 // BCC
2451 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2452 if (MF_DBGLEVEL >= 1) {
2453 Dbprintf("4B UID: %02x%02x%02x%02x",
2454 rUIDBCC1[0],
2455 rUIDBCC1[1],
2456 rUIDBCC1[2],
2457 rUIDBCC1[3]
2458 );
2459 }
2460 break;
2461 case 7:
2462 atqa[0] |= 0x40;
2463 sak_7[0] |= 0x04;
2464 ComputeCrc14443(CRC_14443_A, sak_7, 1, &sak_7[1], &sak_7[2]);
2465
2466 // save CUID
2467 ar_nr_responses[0] = cuid = bytes_to_num(rUIDBCC2, 4);
2468
2469 rUIDBCC1[0] = 0x88; // CascadeTag, CT
2470 // BCC
2471 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2472 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2473 if (MF_DBGLEVEL >= 1) {
2474 Dbprintf("7B UID: %02x %02x %02x %02x %02x %02x %02x",
2475 //rUIDBCC1[0],
2476 rUIDBCC1[1],
2477 rUIDBCC1[2],
2478 rUIDBCC1[3],
2479 rUIDBCC2[0],
2480 rUIDBCC2[1],
2481 rUIDBCC2[2],
2482 rUIDBCC2[3]
2483 );
2484 }
2485 break;
2486 case 10:
2487 atqa[0] |= 0x40;
2488 sak_10[0] |= 0x04;
2489 ComputeCrc14443(CRC_14443_A, sak_10, 1, &sak_10[1], &sak_10[2]);
2490
2491 // save CUID
2492 ar_nr_responses[0] = cuid = bytes_to_num(rUIDBCC3, 4);
2493 rUIDBCC1[0] = 0x88; // CascadeTag, CT
2494 // BCC
2495 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2496
2497 rUIDBCC2[0] = 0x88; // CascadeTag, CT
2498 // BCC
2499 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2500 rUIDBCC3[4] = rUIDBCC3[0] ^ rUIDBCC3[1] ^ rUIDBCC3[2] ^ rUIDBCC3[3];
2501 if (MF_DBGLEVEL >= 1) {
2502 Dbprintf("10B UID: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
2503 //rUIDBCC1[0],
2504 rUIDBCC1[1],
2505 rUIDBCC1[2],
2506 rUIDBCC1[3],
2507 //rUIDBCC2[0],
2508 rUIDBCC2[1],
2509 rUIDBCC2[2],
2510 rUIDBCC2[3],
2511 rUIDBCC3[0],
2512 rUIDBCC3[1],
2513 rUIDBCC3[2],
2514 rUIDBCC3[3]
2515 );
2516 }
2517 break;
2518 default:
2519 break;
2520 }
2521
2522 // We need to listen to the high-frequency, peak-detected path.
2523 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2524
2525 // free eventually allocated BigBuf memory but keep Emulator Memory
2526 BigBuf_free_keep_EM();
2527 clear_trace();
2528 set_tracing(TRUE);
2529
2530 bool finished = FALSE;
2531 while (!BUTTON_PRESS() && !finished && !usb_poll_validate_length()) {
2532 WDT_HIT();
2533
2534 // find reader field
2535 if (cardSTATE == MFEMUL_NOFIELD) {
2536 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
2537 if (vHf > MF_MINFIELDV) {
2538 cardSTATE_TO_IDLE();
2539 LED_A_ON();
2540 }
2541 }
2542 if (cardSTATE == MFEMUL_NOFIELD) continue;
2543
2544 //Now, get data
2545 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
2546 if (res == 2) { //Field is off!
2547 cardSTATE = MFEMUL_NOFIELD;
2548 LEDsoff();
2549 continue;
2550 } else if (res == 1) {
2551 break; //return value 1 means button press
2552 }
2553
2554 // REQ or WUP request in ANY state and WUP in HALTED state
2555 if (len == 1 && ((receivedCmd[0] == ISO14443A_CMD_REQA && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == ISO14443A_CMD_WUPA)) {
2556 selTimer = GetTickCount();
2557 EmSendCmdEx(atqa, sizeof(atqa), (receivedCmd[0] == ISO14443A_CMD_WUPA));
2558 cardSTATE = MFEMUL_SELECT1;
2559 crypto1_destroy(pcs);
2560 cardAUTHKEY = 0xff;
2561 LEDsoff();
2562 continue;
2563 }
2564
2565 switch (cardSTATE) {
2566 case MFEMUL_NOFIELD:
2567 case MFEMUL_HALTED:
2568 case MFEMUL_IDLE:{
2569 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2570 break;
2571 }
2572 case MFEMUL_SELECT1:{
2573 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT && receivedCmd[1] == 0x20)) {
2574 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
2575 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
2576 break;
2577 }
2578 // select card
2579 if (len == 9 &&
2580 ( receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT &&
2581 receivedCmd[1] == 0x70 &&
2582 memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2583
2584 // SAK 4b
2585 EmSendCmd(sak_4, sizeof(sak_4));
2586 switch(_UID_LEN){
2587 case 4:
2588 cardSTATE = MFEMUL_WORK;
2589 LED_B_ON();
2590 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2591 continue;
2592 case 7:
2593 case 10:
2594 cardSTATE = MFEMUL_SELECT2;
2595 continue;
2596 default:break;
2597 }
2598 } else {
2599 cardSTATE_TO_IDLE();
2600 }
2601 break;
2602 }
2603 case MFEMUL_SELECT2:{
2604 if (!len) {
2605 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2606 break;
2607 }
2608 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 && receivedCmd[1] == 0x20)) {
2609 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2610 break;
2611 }
2612 if (len == 9 &&
2613 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 &&
2614 receivedCmd[1] == 0x70 &&
2615 memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0) ) {
2616
2617 EmSendCmd(sak_7, sizeof(sak_7));
2618 switch(_UID_LEN){
2619 case 7:
2620 cardSTATE = MFEMUL_WORK;
2621 LED_B_ON();
2622 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2623 continue;
2624 case 10:
2625 cardSTATE = MFEMUL_SELECT3;
2626 continue;
2627 default:break;
2628 }
2629 } else {
2630 cardSTATE_TO_IDLE();
2631 }
2632 break;
2633 }
2634 case MFEMUL_SELECT3:{
2635 if (!len) {
2636 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2637 break;
2638 }
2639 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 && receivedCmd[1] == 0x20)) {
2640 EmSendCmd(rUIDBCC3, sizeof(rUIDBCC3));
2641 break;
2642 }
2643 if (len == 9 &&
2644 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 &&
2645 receivedCmd[1] == 0x70 &&
2646 memcmp(&receivedCmd[2], rUIDBCC3, 4) == 0) ) {
2647
2648 EmSendCmd(sak_10, sizeof(sak_10));
2649 cardSTATE = MFEMUL_WORK;
2650 LED_B_ON();
2651 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol3 time: %d", GetTickCount() - selTimer);
2652 break;
2653 } else {
2654 cardSTATE_TO_IDLE();
2655 }
2656 break;
2657 }
2658 case MFEMUL_AUTH1:{
2659 if( len != 8) {
2660 cardSTATE_TO_IDLE();
2661 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2662 break;
2663 }
2664
2665 uint32_t ar = bytes_to_num(receivedCmd, 4);
2666 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
2667
2668 //Collect AR/NR
2669 //if(ar_nr_collected < 2 && cardAUTHSC == 2){
2670 if(ar_nr_collected < 2) {
2671 if(ar_nr_responses[2] != ar) {
2672 // Avoid duplicates... probably not necessary, ar should vary.
2673 //ar_nr_responses[ar_nr_collected*5] = 0;
2674 //ar_nr_responses[ar_nr_collected*5+1] = 0;
2675 ar_nr_responses[ar_nr_collected*5+2] = nonce;
2676 ar_nr_responses[ar_nr_collected*5+3] = nr;
2677 ar_nr_responses[ar_nr_collected*5+4] = ar;
2678 ar_nr_collected++;
2679 }
2680 // Interactive mode flag, means we need to send ACK
2681 finished = (flags & FLAG_INTERACTIVE && ar_nr_collected == 2);
2682 }
2683 /*
2684 crypto1_word(pcs, ar , 1);
2685 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2686
2687 test if auth OK
2688 if (cardRr != prng_successor(nonce, 64)){
2689
2690 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2691 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2692 cardRr, prng_successor(nonce, 64));
2693 Shouldn't we respond anything here?
2694 Right now, we don't nack or anything, which causes the
2695 reader to do a WUPA after a while. /Martin
2696 -- which is the correct response. /piwi
2697 cardSTATE_TO_IDLE();
2698 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2699 break;
2700 }
2701 */
2702
2703 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2704 num_to_bytes(ans, 4, rAUTH_AT);
2705 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2706 LED_C_ON();
2707
2708 if (MF_DBGLEVEL >= 4) {
2709 Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2710 cardAUTHSC,
2711 cardAUTHKEY == 0 ? 'A' : 'B',
2712 GetTickCount() - authTimer
2713 );
2714 }
2715 cardSTATE = MFEMUL_WORK;
2716 break;
2717 }
2718 case MFEMUL_WORK:{
2719 if (len == 0) {
2720 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2721 break;
2722 }
2723 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2724
2725 if(encrypted_data)
2726 mf_crypto1_decrypt(pcs, receivedCmd, len);
2727
2728 if (len == 4 && (receivedCmd[0] == MIFARE_AUTH_KEYA ||
2729 receivedCmd[0] == MIFARE_AUTH_KEYB) ) {
2730
2731 authTimer = GetTickCount();
2732 cardAUTHSC = receivedCmd[1] / 4; // received block num
2733 cardAUTHKEY = receivedCmd[0] - 0x60; // & 1
2734 crypto1_destroy(pcs);
2735 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
2736
2737 if (!encrypted_data) {
2738 // first authentication
2739 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2740 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
2741
2742 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2743
2744 } else {
2745 // nested authentication
2746 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
2747 num_to_bytes(ans, 4, rAUTH_AT);
2748
2749 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2750 }
2751
2752 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2753 cardSTATE = MFEMUL_AUTH1;
2754 break;
2755 }
2756
2757 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2758 // BUT... ACK --> NACK
2759 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2760 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2761 break;
2762 }
2763
2764 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2765 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2766 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2767 break;
2768 }
2769
2770 if(len != 4) {
2771 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2772 break;
2773 }
2774
2775 if ( receivedCmd[0] == ISO14443A_CMD_READBLOCK ||
2776 receivedCmd[0] == ISO14443A_CMD_WRITEBLOCK ||
2777 receivedCmd[0] == MIFARE_CMD_INC ||
2778 receivedCmd[0] == MIFARE_CMD_DEC ||
2779 receivedCmd[0] == MIFARE_CMD_RESTORE ||
2780 receivedCmd[0] == MIFARE_CMD_TRANSFER ) {
2781
2782 if (receivedCmd[1] >= 16 * 4) {
2783 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2784 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2785 break;
2786 }
2787
2788 if (receivedCmd[1] / 4 != cardAUTHSC) {
2789 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2790 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
2791 break;
2792 }
2793 }
2794 // read block
2795 if (receivedCmd[0] == ISO14443A_CMD_READBLOCK) {
2796 if (MF_DBGLEVEL >= 4) Dbprintf("Reader reading block %d (0x%02x)", receivedCmd[1], receivedCmd[1]);
2797
2798 emlGetMem(response, receivedCmd[1], 1);
2799 AppendCrc14443a(response, 16);
2800 mf_crypto1_encrypt(pcs, response, 18, response_par);
2801 EmSendCmdPar(response, 18, response_par);
2802 numReads++;
2803 if(exitAfterNReads > 0 && numReads >= exitAfterNReads) {
2804 Dbprintf("%d reads done, exiting", numReads);
2805 finished = true;
2806 }
2807 break;
2808 }
2809 // write block
2810 if (receivedCmd[0] == ISO14443A_CMD_WRITEBLOCK) {
2811 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)", receivedCmd[1], receivedCmd[1]);
2812 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2813 cardSTATE = MFEMUL_WRITEBL2;
2814 cardWRBL = receivedCmd[1];
2815 break;
2816 }
2817 // increment, decrement, restore
2818 if ( receivedCmd[0] == MIFARE_CMD_INC ||
2819 receivedCmd[0] == MIFARE_CMD_DEC ||
2820 receivedCmd[0] == MIFARE_CMD_RESTORE) {
2821
2822 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0], receivedCmd[1], receivedCmd[1]);
2823
2824 if (emlCheckValBl(receivedCmd[1])) {
2825 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
2826 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2827 break;
2828 }
2829 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2830 if (receivedCmd[0] == MIFARE_CMD_INC) cardSTATE = MFEMUL_INTREG_INC;
2831 if (receivedCmd[0] == MIFARE_CMD_DEC) cardSTATE = MFEMUL_INTREG_DEC;
2832 if (receivedCmd[0] == MIFARE_CMD_RESTORE) cardSTATE = MFEMUL_INTREG_REST;
2833 cardWRBL = receivedCmd[1];
2834 break;
2835 }
2836 // transfer
2837 if (receivedCmd[0] == MIFARE_CMD_TRANSFER) {
2838 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)", receivedCmd[0], receivedCmd[1], receivedCmd[1]);
2839 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2840 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2841 else
2842 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2843 break;
2844 }
2845 // halt
2846 if (receivedCmd[0] == ISO14443A_CMD_HALT && receivedCmd[1] == 0x00) {
2847 LED_B_OFF();
2848 LED_C_OFF();
2849 cardSTATE = MFEMUL_HALTED;
2850 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
2851 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2852 break;
2853 }
2854 // RATS
2855 if (receivedCmd[0] == ISO14443A_CMD_RATS) {
2856 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2857 break;
2858 }
2859 // command not allowed
2860 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2861 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2862 break;
2863 }
2864 case MFEMUL_WRITEBL2:{
2865 if (len == 18) {
2866 mf_crypto1_decrypt(pcs, receivedCmd, len);
2867 emlSetMem(receivedCmd, cardWRBL, 1);
2868 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2869 cardSTATE = MFEMUL_WORK;
2870 } else {
2871 cardSTATE_TO_IDLE();
2872 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2873 }
2874 break;
2875 }
2876 case MFEMUL_INTREG_INC:{
2877 mf_crypto1_decrypt(pcs, receivedCmd, len);
2878 memcpy(&ans, receivedCmd, 4);
2879 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2880 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2881 cardSTATE_TO_IDLE();
2882 break;
2883 }
2884 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2885 cardINTREG = cardINTREG + ans;
2886 cardSTATE = MFEMUL_WORK;
2887 break;
2888 }
2889 case MFEMUL_INTREG_DEC:{
2890 mf_crypto1_decrypt(pcs, receivedCmd, len);
2891 memcpy(&ans, receivedCmd, 4);
2892 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2893 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2894 cardSTATE_TO_IDLE();
2895 break;
2896 }
2897 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2898 cardINTREG = cardINTREG - ans;
2899 cardSTATE = MFEMUL_WORK;
2900 break;
2901 }
2902 case MFEMUL_INTREG_REST:{
2903 mf_crypto1_decrypt(pcs, receivedCmd, len);
2904 memcpy(&ans, receivedCmd, 4);
2905 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2906 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2907 cardSTATE_TO_IDLE();
2908 break;
2909 }
2910 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2911 cardSTATE = MFEMUL_WORK;
2912 break;
2913 }
2914 }
2915 }
2916
2917 // Interactive mode flag, means we need to send ACK
2918 if(flags & FLAG_INTERACTIVE) {
2919 //May just aswell send the collected ar_nr in the response aswell
2920 uint8_t len = ar_nr_collected*5*4;
2921 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, len, 0, &ar_nr_responses, len);
2922 }
2923
2924 if(flags & FLAG_NR_AR_ATTACK && MF_DBGLEVEL >= 1 ) {
2925 if(ar_nr_collected > 1 ) {
2926 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
2927 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
2928 ar_nr_responses[0], // CUID
2929 ar_nr_responses[1], // NT
2930 ar_nr_responses[2], // AR1
2931 ar_nr_responses[3], // NR1
2932 ar_nr_responses[4], // AR2
2933 ar_nr_responses[5] // NR2
2934 );
2935 } else {
2936 Dbprintf("Failed to obtain two AR/NR pairs!");
2937 if(ar_nr_collected > 0 ) {
2938 Dbprintf("Only got these: UID=%08x, nonce=%08x, AR1=%08x, NR1=%08x",
2939 ar_nr_responses[0], // CUID
2940 ar_nr_responses[1], // NT
2941 ar_nr_responses[2], // AR1
2942 ar_nr_responses[3] // NR1
2943 );
2944 }
2945 }
2946 }
2947 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
2948
2949 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2950 LEDsoff();
2951 set_tracing(FALSE);
2952 }
2953
2954
2955 //-----------------------------------------------------------------------------
2956 // MIFARE sniffer.
2957 //
2958 // if no activity for 2sec, it sends the collected data to the client.
2959 //-----------------------------------------------------------------------------
2960 void RAMFUNC SniffMifare(uint8_t param) {
2961 // param:
2962 // bit 0 - trigger from first card answer
2963 // bit 1 - trigger from first reader 7-bit request
2964 LEDsoff();
2965
2966 // free eventually allocated BigBuf memory
2967 BigBuf_free(); BigBuf_Clear_ext(false);
2968 clear_trace();
2969 set_tracing(TRUE);
2970
2971 // The command (reader -> tag) that we're receiving.
2972 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
2973 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
2974
2975 // The response (tag -> reader) that we're receiving.
2976 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE] = {0x00};
2977 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE] = {0x00};
2978
2979 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2980
2981 // allocate the DMA buffer, used to stream samples from the FPGA
2982 // [iceman] is this sniffed data unsigned?
2983 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
2984 uint8_t *data = dmaBuf;
2985 uint8_t previous_data = 0;
2986 int maxDataLen = 0;
2987 int dataLen = 0;
2988 bool ReaderIsActive = FALSE;
2989 bool TagIsActive = FALSE;
2990
2991 // Set up the demodulator for tag -> reader responses.
2992 DemodInit(receivedResponse, receivedResponsePar);
2993
2994 // Set up the demodulator for the reader -> tag commands
2995 UartInit(receivedCmd, receivedCmdPar);
2996
2997 // set transfer address and number of bytes. Start transfer.
2998 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
2999
3000 LED_D_OFF();
3001
3002 MfSniffInit();
3003
3004 // And now we loop, receiving samples.
3005 for(uint32_t sniffCounter = 0;; ) {
3006
3007 LED_A_ON();
3008 WDT_HIT();
3009
3010 if(BUTTON_PRESS()) {
3011 DbpString("cancelled by button");
3012 break;
3013 }
3014
3015 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
3016 // check if a transaction is completed (timeout after 2000ms).
3017 // if yes, stop the DMA transfer and send what we have so far to the client
3018 if (MfSniffSend(2000)) {
3019 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
3020 sniffCounter = 0;
3021 data = dmaBuf;
3022 maxDataLen = 0;
3023 ReaderIsActive = FALSE;
3024 TagIsActive = FALSE;
3025 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
3026 }
3027 }
3028
3029 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
3030 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
3031
3032 if (readBufDataP <= dmaBufDataP) // we are processing the same block of data which is currently being transferred
3033 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
3034 else
3035 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
3036
3037 // test for length of buffer
3038 if(dataLen > maxDataLen) { // we are more behind than ever...
3039 maxDataLen = dataLen;
3040 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
3041 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
3042 break;
3043 }
3044 }
3045 if(dataLen < 1) continue;
3046
3047 // primary buffer was stopped ( <-- we lost data!
3048 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
3049 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
3050 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
3051 Dbprintf("RxEmpty ERROR, data length:%d", dataLen); // temporary
3052 }
3053 // secondary buffer sets as primary, secondary buffer was stopped
3054 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
3055 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
3056 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
3057 }
3058
3059 LED_A_OFF();
3060
3061 if (sniffCounter & 0x01) {
3062
3063 // no need to try decoding tag data if the reader is sending
3064 if(!TagIsActive) {
3065 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
3066 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
3067 LED_C_INV();
3068
3069 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
3070
3071 UartInit(receivedCmd, receivedCmdPar);
3072 DemodReset();
3073 }
3074 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
3075 }
3076
3077 // no need to try decoding tag data if the reader is sending
3078 if(!ReaderIsActive) {
3079 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
3080 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
3081 LED_C_INV();
3082
3083 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
3084
3085 DemodReset();
3086 UartInit(receivedCmd, receivedCmdPar);
3087 }
3088 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
3089 }
3090 }
3091
3092 previous_data = *data;
3093 sniffCounter++;
3094 data++;
3095
3096 if(data == dmaBuf + DMA_BUFFER_SIZE)
3097 data = dmaBuf;
3098
3099 } // main cycle
3100
3101 FpgaDisableSscDma();
3102 MfSniffEnd();
3103 if (MF_DBGLEVEL >= 1) Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
3104 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
3105 LEDsoff();
3106 set_tracing(FALSE);
3107 }
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