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ADD: added a StopTicks functions, to disable the timer used for ticks (TC0, TC1)
[proxmark3-svn] / armsrc / legicrf.c
1 //-----------------------------------------------------------------------------
2 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
3 // 2016 Iceman
4 //
5 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
6 // at your option, any later version. See the LICENSE.txt file for the text of
7 // the license.
8 //-----------------------------------------------------------------------------
9 // LEGIC RF simulation code
10 //-----------------------------------------------------------------------------
11 #include "legicrf.h"
12
13 static struct legic_frame {
14 uint8_t bits;
15 uint32_t data;
16 } current_frame;
17
18 static enum {
19 STATE_DISCON,
20 STATE_IV,
21 STATE_CON,
22 } legic_state;
23
24 static crc_t legic_crc;
25 static int legic_read_count;
26 static uint32_t legic_prng_bc;
27 static uint32_t legic_prng_iv;
28
29 static int legic_phase_drift;
30 static int legic_frame_drift;
31 static int legic_reqresp_drift;
32
33 AT91PS_TC timer;
34 AT91PS_TC prng_timer;
35
36 /*
37 static void setup_timer(void) {
38 // Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
39 // this it won't be terribly accurate but should be good enough.
40 //
41 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
42 timer = AT91C_BASE_TC1;
43 timer->TC_CCR = AT91C_TC_CLKDIS;
44 timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
45 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
46
47 //
48 // Set up Timer 2 to use for measuring time between frames in
49 // tag simulation mode. Runs 4x faster as Timer 1
50 //
51 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);
52 prng_timer = AT91C_BASE_TC2;
53 prng_timer->TC_CCR = AT91C_TC_CLKDIS;
54 prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
55 prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
56 }
57
58 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
59 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
60
61 // fast clock
62 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
63 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
64 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
65 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
66 AT91C_BASE_TC0->TC_RA = 1;
67 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
68
69 */
70
71 // At TIMER_CLOCK3 (MCK/32)
72 // testing calculating in (us) microseconds.
73 #define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks
74 #define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks
75 #define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */
76 #define TAG_BIT_PERIOD 142 // 100us == 100 * 1.5 == 150ticks
77 #define TAG_FRAME_WAIT 495 // 330us from READER frame end to TAG frame start. 330 * 1.5 == 495
78
79 #define RWD_TIME_FUZZ 20 // rather generous 13us, since the peak detector + hysteresis fuzz quite a bit
80
81 #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
82 #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
83
84 #define OFFSET_LOG 1024
85
86 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
87
88 #ifndef SHORT_COIL
89 # define SHORT_COIL LOW(GPIO_SSC_DOUT);
90 #endif
91 #ifndef OPEN_COIL
92 # define OPEN_COIL HIGH(GPIO_SSC_DOUT);
93 #endif
94
95 // Pause pulse, off in 20us / 30ticks,
96 // ONE / ZERO bit pulse,
97 // one == 80us / 120ticks
98 // zero == 40us / 60ticks
99 #ifndef COIL_PULSE
100 # define COIL_PULSE(x) \
101 do { \
102 SHORT_COIL; \
103 WaitTicks( (RWD_TIME_PAUSE) ); \
104 OPEN_COIL; \
105 WaitTicks((x)); \
106 } while (0);
107 #endif
108
109 // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
110 // Historically it used to be FREE_BUFFER_SIZE, which was 2744.
111 #define LEGIC_CARD_MEMSIZE 1024
112 static uint8_t* cardmem;
113
114 static void frame_append_bit(struct legic_frame * const f, uint8_t bit) {
115 // Overflow, won't happen
116 if (f->bits >= 31) return;
117
118 f->data |= (bit << f->bits);
119 f->bits++;
120 }
121
122 static void frame_clean(struct legic_frame * const f) {
123 f->data = 0;
124 f->bits = 0;
125 }
126
127 // Prng works when waiting in 99.1us cycles.
128 // and while sending/receiving in bit frames (100, 60)
129 /*static void CalibratePrng( uint32_t time){
130 // Calculate Cycles based on timer 100us
131 uint32_t i = (time - sendFrameStop) / 100 ;
132
133 // substract cycles of finished frames
134 int k = i - legic_prng_count()+1;
135
136 // substract current frame length, rewind to beginning
137 if ( k > 0 )
138 legic_prng_forward(k);
139 }
140 */
141
142 /* Generate Keystream */
143 uint32_t get_key_stream(int skip, int count) {
144
145 int i;
146
147 // Use int to enlarge timer tc to 32bit
148 legic_prng_bc += prng_timer->TC_CV;
149
150 // reset the prng timer.
151
152 /* If skip == -1, forward prng time based */
153 if(skip == -1) {
154 i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */
155 i -= legic_prng_count(); /* substract cycles of finished frames */
156 i -= count; /* substract current frame length, rewind to beginning */
157 legic_prng_forward(i);
158 } else {
159 legic_prng_forward(skip);
160 }
161
162 i = (count == 6) ? -1 : legic_read_count;
163
164 // log
165 //uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1), BYTEx(send, 0), BYTEx(send, 1), legic_prng_count()};
166 //LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, TRUE);
167
168 /* Generate KeyStream */
169 return legic_prng_get_bits(count);
170 }
171
172 /* Send a frame in tag mode, the FPGA must have been set up by
173 * LegicRfSimulate
174 */
175 void frame_send_tag(uint16_t response, uint8_t bits) {
176
177 uint16_t mask = 1;
178
179 /* Bitbang the response */
180 SHORT_COIL;
181 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
182 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
183
184 /* TAG_FRAME_WAIT -> shift by 2 */
185 legic_prng_forward(2);
186 response ^= legic_prng_get_bits(bits);
187
188 /* Wait for the frame start */
189 WaitTicks( TAG_FRAME_WAIT );
190
191 for (; mask < BITMASK(bits); mask <<= 1) {
192 if (response & mask)
193 OPEN_COIL
194 else
195 SHORT_COIL
196 WaitTicks(TAG_BIT_PERIOD);
197 }
198 SHORT_COIL;
199 }
200
201 /* Send a frame in reader mode, the FPGA must have been set up by
202 * LegicRfReader
203 */
204 void frame_sendAsReader(uint32_t data, uint8_t bits){
205
206 uint32_t starttime = GET_TICKS, send = 0;
207 uint16_t mask = 1;
208
209 // xor lsfr onto data.
210 send = data ^ legic_prng_get_bits(bits);
211
212 for (; mask < BITMASK(bits); mask <<= 1) {
213 if (send & mask)
214 COIL_PULSE(RWD_TIME_1)
215 else
216 COIL_PULSE(RWD_TIME_0)
217 }
218
219 // Final pause to mark the end of the frame
220 COIL_PULSE(0);
221
222 // log
223 uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1), BYTEx(send, 0), BYTEx(send, 1)};
224 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, TRUE);
225 }
226
227 /* Receive a frame from the card in reader emulation mode, the FPGA and
228 * timer must have been set up by LegicRfReader and frame_sendAsReader.
229 *
230 * The LEGIC RF protocol from card to reader does not include explicit
231 * frame start/stop information or length information. The reader must
232 * know beforehand how many bits it wants to receive. (Notably: a card
233 * sending a stream of 0-bits is indistinguishable from no card present.)
234 *
235 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
236 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
237 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
238 * for edges. Count the edges in each bit interval. If they are approximately
239 * 0 this was a 0-bit, if they are approximately equal to the number of edges
240 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
241 * timer that's still running from frame_sendAsReader in order to get a synchronization
242 * with the frame that we just sent.
243 *
244 * FIXME: Because we're relying on the hysteresis to just do the right thing
245 * the range is severely reduced (and you'll probably also need a good antenna).
246 * So this should be fixed some time in the future for a proper receiver.
247 */
248 static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) {
249
250 if ( bits > 32 ) return;
251
252 uint8_t i = bits, edges = 0;
253 uint32_t the_bit = 1, next_bit_at = 0, data = 0;
254 uint32_t old_level = 0;
255 volatile uint32_t level = 0;
256
257 frame_clean(f);
258
259 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
260 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
261
262 // calibrate the prng.
263 legic_prng_forward(2);
264 data = legic_prng_get_bits(bits);
265
266 //FIXED time between sending frame and now listening frame. 330us
267 uint32_t starttime = GET_TICKS;
268 // its about 9+9 ticks delay from end-send to here.
269 WaitTicks( 477 );
270
271 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
272
273 while ( i-- ){
274 edges = 0;
275 while ( GET_TICKS < next_bit_at) {
276
277 level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
278
279 if (level != old_level)
280 ++edges;
281
282 old_level = level;
283 }
284
285 next_bit_at += TAG_BIT_PERIOD;
286
287 // We expect 42 edges (ONE)
288 if ( edges > 20 )
289 data ^= the_bit;
290
291 the_bit <<= 1;
292 }
293
294 // output
295 f->data = data;
296 f->bits = bits;
297
298 // log
299 uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
300 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
301 }
302
303 // Setup pm3 as a Legic Reader
304 static uint32_t setup_phase_reader(uint8_t iv) {
305
306 // Switch on carrier and let the tag charge for 1ms
307 HIGH(GPIO_SSC_DOUT);
308 WaitUS(5000);
309
310 ResetTicks();
311
312 // no keystream yet
313 legic_prng_init(0);
314
315 // send IV handshake
316 frame_sendAsReader(iv, 7);
317
318 // Now both tag and reader has same IV. Prng can start.
319 legic_prng_init(iv);
320
321 frame_receiveAsReader(&current_frame, 6);
322
323 // 292us (438t) - fixed delay before sending ack.
324 // minus log and stuff 100tick?
325 WaitTicks(338);
326 legic_prng_forward(3);
327
328 // Send obsfuscated acknowledgment frame.
329 // 0x19 = 0x18 MIM22, 0x01 LSB READCMD
330 // 0x39 = 0x38 MIM256, MIM1024 0x01 LSB READCMD
331 switch ( current_frame.data ) {
332 case 0x0D: frame_sendAsReader(0x19, 6); break;
333 case 0x1D:
334 case 0x3D: frame_sendAsReader(0x39, 6); break;
335 default: break;
336 }
337
338 legic_prng_forward(2);
339 return current_frame.data;
340 }
341
342 static void LegicCommonInit(void) {
343
344 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
345 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
346 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
347
348 /* Bitbang the transmitter */
349 LOW(GPIO_SSC_DOUT);
350 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
351 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
352
353 // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
354 cardmem = BigBuf_get_EM_addr();
355 memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE);
356
357 clear_trace();
358 set_tracing(TRUE);
359 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
360
361 StartTicks();
362 }
363
364 // Switch off carrier, make sure tag is reset
365 static void switch_off_tag_rwd(void) {
366 LOW(GPIO_SSC_DOUT);
367 WaitUS(20);
368 WDT_HIT();
369 }
370
371 // calculate crc4 for a legic READ command
372 static uint32_t legic4Crc(uint8_t cmd, uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
373 crc_clear(&legic_crc);
374 uint32_t temp = (value << cmd_sz) | (byte_index << 1) | cmd;
375 crc_update(&legic_crc, temp, cmd_sz + 8 );
376 return crc_finish(&legic_crc);
377 }
378
379 int legic_read_byte( uint16_t index, uint8_t cmd_sz) {
380
381 uint8_t byte, crc, calcCrc = 0;
382 uint32_t cmd = (index << 1) | LEGIC_READ;
383
384 // 90ticks = 60us (should be 100us but crc calc takes time.)
385 //WaitTicks(330); // 330ticks prng(4) - works
386 WaitTicks(240); // 240ticks prng(3) - works
387
388 frame_sendAsReader(cmd, cmd_sz);
389 frame_receiveAsReader(&current_frame, 12);
390
391 // CRC check.
392 byte = BYTEx(current_frame.data, 0);
393 crc = BYTEx(current_frame.data, 1);
394 calcCrc = legic4Crc(LEGIC_READ, index, byte, cmd_sz);
395
396 if( calcCrc != crc ) {
397 Dbprintf("!!! crc mismatch: expected %x but got %x !!!", calcCrc, crc);
398 return -1;
399 }
400
401 legic_prng_forward(3);
402 return byte;
403 }
404
405 /*
406 * - assemble a write_cmd_frame with crc and send it
407 * - wait until the tag sends back an ACK ('1' bit unencrypted)
408 * - forward the prng based on the timing
409 */
410 int legic_write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz) {
411
412 // crc
413 crc_clear(&legic_crc);
414 crc_update(&legic_crc, 0, 1); /* CMD_WRITE */
415 crc_update(&legic_crc, index, addr_sz);
416 crc_update(&legic_crc, byte, 8);
417 uint32_t crc = crc_finish(&legic_crc);
418 uint32_t crc2 = legic4Crc(LEGIC_WRITE, index, byte, addr_sz+1);
419 if ( crc != crc2 ) {
420 Dbprintf("crc is missmatch");
421 return 1;
422 }
423 // send write command
424 uint32_t cmd = ((crc <<(addr_sz+1+8)) //CRC
425 |(byte <<(addr_sz+1)) //Data
426 |(index <<1) //index
427 | LEGIC_WRITE); //CMD = Write
428
429 uint32_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd
430
431 legic_prng_forward(2);
432
433 WaitTicks(330);
434
435 frame_sendAsReader(cmd, cmd_sz);
436
437 // wait for ack
438 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
439 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
440
441 int t, old_level = 0, edges = 0;
442 int next_bit_at = 0;
443
444 // ACK 3.6ms = 3600us * 1.5 = 5400ticks.
445 WaitTicks(5360);
446
447 for( t = 0; t < 80; ++t) {
448 edges = 0;
449 next_bit_at += TAG_BIT_PERIOD;
450 while(timer->TC_CV < next_bit_at) {
451 volatile uint32_t level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
452 if(level != old_level)
453 edges++;
454
455 old_level = level;
456 }
457 /* expected are 42 edges (ONE) */
458 if(edges > 20 ) {
459 int t = timer->TC_CV;
460 int c = t / TAG_BIT_PERIOD;
461
462 ResetTimer(timer);
463 legic_prng_forward(c);
464 return 0;
465 }
466 }
467
468 return -1;
469 }
470
471 int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) {
472
473 uint16_t i = 0;
474 uint8_t isOK = 1;
475 legic_card_select_t card;
476
477 LegicCommonInit();
478
479 if ( legic_select_card_iv(&card, iv) ) {
480 isOK = 0;
481 goto OUT;
482 }
483
484 switch_off_tag_rwd();
485
486 if (len + offset >= card.cardsize)
487 len = card.cardsize - offset;
488
489 setup_phase_reader(iv);
490
491 LED_B_ON();
492 while (i < len) {
493 int r = legic_read_byte(offset + i, card.cmdsize);
494
495 if (r == -1 || BUTTON_PRESS()) {
496 if ( MF_DBGLEVEL >= 2) DbpString("operation aborted");
497 isOK = 0;
498 goto OUT;
499 }
500 cardmem[i++] = r;
501 WDT_HIT();
502 }
503
504 OUT:
505 WDT_HIT();
506 switch_off_tag_rwd();
507 LEDsoff();
508 cmd_send(CMD_ACK, isOK, len, 0, cardmem, len);
509 return 0;
510 }
511
512 void LegicRfWriter(uint16_t offset, uint16_t len, uint8_t iv, uint8_t *data) {
513
514 uint8_t isOK = 1;
515
516 // UID not is writeable.
517 if ( offset <= 4 ) {
518 isOK = 0;
519 goto OUT;
520 }
521
522 legic_card_select_t card;
523
524 LegicCommonInit();
525
526 if ( legic_select_card_iv(&card, iv) ) {
527 isOK = 0;
528 goto OUT;
529 }
530
531 if (len + offset >= card.cardsize)
532 len = card.cardsize - offset;
533
534 setup_phase_reader(iv);
535
536 LED_B_ON();
537 int r = 0;
538 // how about we write backwards instead. no need for this extra DCF check.
539 // index = len - cardsize
540 // stops uid 01234,
541 /*
542 len = 20
543 offset = 5
544
545 index = 20+5 = 25
546 if ( index > cardsize ) return -1;
547
548 loop
549 write( cardmem[index], index , card.addrsize);
550 --index;
551 end loop
552 */
553 uint16_t index = len;
554 while(index > 4) {
555
556 r = legic_write_byte( index, cardmem[ index ], card.addrsize);
557
558 if ( r ) {
559 Dbprintf("operation aborted @ 0x%03.3x", index);
560 isOK = 0;
561 goto OUT;
562 }
563 --index;
564 WDT_HIT();
565 }
566
567 OUT:
568 cmd_send(CMD_ACK, isOK, 0,0,0,0);
569 switch_off_tag_rwd();
570 LEDsoff();
571 }
572
573 int legic_select_card_iv(legic_card_select_t *p_card, uint8_t iv){
574
575 if ( p_card == NULL ) return 1;
576
577 p_card->tagtype = setup_phase_reader(iv);
578
579 switch(p_card->tagtype) {
580 case 0x0d:
581 p_card->cmdsize = 6;
582 p_card->addrsize = 5;
583 p_card->cardsize = 22;
584 break;
585 case 0x1d:
586 p_card->cmdsize = 9;
587 p_card->addrsize = 8;
588 p_card->cardsize = 256;
589 break;
590 case 0x3d:
591 p_card->cmdsize = 11;
592 p_card->addrsize = 10;
593 p_card->cardsize = 1024;
594 break;
595 default:
596 p_card->cmdsize = 0;
597 p_card->addrsize = 0;
598 p_card->cardsize = 0;
599 return 2;
600 }
601 return 0;
602 }
603 int legic_select_card(legic_card_select_t *p_card){
604 return legic_select_card_iv(p_card, 0x01);
605 }
606
607 //-----------------------------------------------------------------------------
608 // Work with emulator memory
609 //
610 // Note: we call FpgaDownloadAndGo(FPGA_BITSTREAM_HF) here although FPGA is not
611 // involved in dealing with emulator memory. But if it is called later, it might
612 // destroy the Emulator Memory.
613 //-----------------------------------------------------------------------------
614 // arg0 = offset
615 // arg1 = num of bytes
616 void LegicEMemSet(uint32_t arg0, uint32_t arg1, uint8_t *data) {
617 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
618 legic_emlset_mem(data, arg0, arg1);
619 }
620 // arg0 = offset
621 // arg1 = num of bytes
622 void LegicEMemGet(uint32_t arg0, uint32_t arg1) {
623 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
624 uint8_t buf[USB_CMD_DATA_SIZE] = {0x00};
625 legic_emlget_mem(buf, arg0, arg1);
626 LED_B_ON();
627 cmd_send(CMD_ACK, arg0, arg1, 0, buf, USB_CMD_DATA_SIZE);
628 LED_B_OFF();
629 }
630 void legic_emlset_mem(uint8_t *data, int offset, int numofbytes) {
631 cardmem = BigBuf_get_EM_addr();
632 memcpy(cardmem + offset, data, numofbytes);
633 }
634 void legic_emlget_mem(uint8_t *data, int offset, int numofbytes) {
635 cardmem = BigBuf_get_EM_addr();
636 memcpy(data, cardmem + offset, numofbytes);
637 }
638
639 void LegicRfInfo(void){
640
641 int r;
642
643 uint8_t buf[sizeof(legic_card_select_t)] = {0x00};
644 legic_card_select_t *card = (legic_card_select_t*) buf;
645
646 LegicCommonInit();
647
648 if ( legic_select_card(card) ) {
649 cmd_send(CMD_ACK,0,0,0,0,0);
650 goto OUT;
651 }
652
653 // read UID bytes
654 for ( uint8_t i = 0; i < sizeof(card->uid); ++i) {
655 r = legic_read_byte(i, card->cmdsize);
656 if ( r == -1 ) {
657 cmd_send(CMD_ACK,0,0,0,0,0);
658 goto OUT;
659 }
660 card->uid[i] = r & 0xFF;
661 }
662
663 // MCC byte.
664 r = legic_read_byte(4, card->cmdsize);
665 uint32_t calc_mcc = CRC8Legic(card->uid, 4);;
666 if ( r != calc_mcc) {
667 cmd_send(CMD_ACK,0,0,0,0,0);
668 goto OUT;
669 }
670
671 // OK
672 cmd_send(CMD_ACK, 1, 0, 0, buf, sizeof(legic_card_select_t));
673
674 OUT:
675 switch_off_tag_rwd();
676 LEDsoff();
677 }
678
679 /* Handle (whether to respond) a frame in tag mode
680 * Only called when simulating a tag.
681 */
682 static void frame_handle_tag(struct legic_frame const * const f)
683 {
684 uint8_t *BigBuf = BigBuf_get_addr();
685
686 /* First Part of Handshake (IV) */
687 if(f->bits == 7) {
688
689 LED_C_ON();
690
691 // Reset prng timer
692 ResetTimer(prng_timer);
693
694 legic_prng_init(f->data);
695 frame_send_tag(0x3d, 6); /* 0x3d^0x26 = 0x1B */
696 legic_state = STATE_IV;
697 legic_read_count = 0;
698 legic_prng_bc = 0;
699 legic_prng_iv = f->data;
700
701
702 ResetTimer(timer);
703 WaitUS(280);
704 return;
705 }
706
707 /* 0x19==??? */
708 if(legic_state == STATE_IV) {
709 int local_key = get_key_stream(3, 6);
710 int xored = 0x39 ^ local_key;
711 if((f->bits == 6) && (f->data == xored)) {
712 legic_state = STATE_CON;
713
714 ResetTimer(timer);
715 WaitUS(200);
716 return;
717
718 } else {
719 legic_state = STATE_DISCON;
720 LED_C_OFF();
721 Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored);
722 return;
723 }
724 }
725
726 /* Read */
727 if(f->bits == 11) {
728 if(legic_state == STATE_CON) {
729 int key = get_key_stream(2, 11); //legic_phase_drift, 11);
730 int addr = f->data ^ key; addr = addr >> 1;
731 int data = BigBuf[addr];
732 int hash = legic4Crc(LEGIC_READ, addr, data, 11) << 8;
733 BigBuf[OFFSET_LOG+legic_read_count] = (uint8_t)addr;
734 legic_read_count++;
735
736 //Dbprintf("Data:%03.3x, key:%03.3x, addr: %03.3x, read_c:%u", f->data, key, addr, read_c);
737 legic_prng_forward(legic_reqresp_drift);
738
739 frame_send_tag(hash | data, 12);
740
741 ResetTimer(timer);
742 legic_prng_forward(2);
743 WaitUS(180);
744 return;
745 }
746 }
747
748 /* Write */
749 if(f->bits == 23) {
750 int key = get_key_stream(-1, 23); //legic_frame_drift, 23);
751 int addr = f->data ^ key; addr = addr >> 1; addr = addr & 0x3ff;
752 int data = f->data ^ key; data = data >> 11; data = data & 0xff;
753
754 /* write command */
755 legic_state = STATE_DISCON;
756 LED_C_OFF();
757 Dbprintf("write - addr: %x, data: %x", addr, data);
758 return;
759 }
760
761 if(legic_state != STATE_DISCON) {
762 Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count);
763 int i;
764 Dbprintf("IV: %03.3x", legic_prng_iv);
765 for(i = 0; i<legic_read_count; i++) {
766 Dbprintf("Read Nb: %u, Addr: %u", i, BigBuf[OFFSET_LOG+i]);
767 }
768
769 for(i = -1; i<legic_read_count; i++) {
770 uint32_t t;
771 t = BigBuf[OFFSET_LOG+256+i*4];
772 t |= BigBuf[OFFSET_LOG+256+i*4+1] << 8;
773 t |= BigBuf[OFFSET_LOG+256+i*4+2] <<16;
774 t |= BigBuf[OFFSET_LOG+256+i*4+3] <<24;
775
776 Dbprintf("Cycles: %u, Frame Length: %u, Time: %u",
777 BigBuf[OFFSET_LOG+128+i],
778 BigBuf[OFFSET_LOG+384+i],
779 t);
780 }
781 }
782 legic_state = STATE_DISCON;
783 legic_read_count = 0;
784 SpinDelay(10);
785 LED_C_OFF();
786 return;
787 }
788
789 /* Read bit by bit untill full frame is received
790 * Call to process frame end answer
791 */
792 static void emit(int bit) {
793
794 switch (bit) {
795 case 1:
796 frame_append_bit(&current_frame, 1);
797 break;
798 case 0:
799 frame_append_bit(&current_frame, 0);
800 break;
801 default:
802 if(current_frame.bits <= 4) {
803 frame_clean(&current_frame);
804 } else {
805 frame_handle_tag(&current_frame);
806 frame_clean(&current_frame);
807 }
808 WDT_HIT();
809 break;
810 }
811 }
812
813 void LegicRfSimulate(int phase, int frame, int reqresp)
814 {
815 /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
816 * modulation mode set to 212kHz subcarrier. We are getting the incoming raw
817 * envelope waveform on DIN and should send our response on DOUT.
818 *
819 * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
820 * measure the time between two rising edges on DIN, and no encoding on the
821 * subcarrier from card to reader, so we'll just shift out our verbatim data
822 * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
823 * seems to be 300us-ish.
824 */
825
826 legic_phase_drift = phase;
827 legic_frame_drift = frame;
828 legic_reqresp_drift = reqresp;
829
830 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
831 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
832 FpgaSetupSsc();
833 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
834
835 /* Bitbang the receiver */
836 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
837 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
838
839 //setup_timer();
840 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
841
842 int old_level = 0;
843 int active = 0;
844 legic_state = STATE_DISCON;
845
846 LED_B_ON();
847 DbpString("Starting Legic emulator, press button to end");
848
849 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
850 int level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
851 int time = timer->TC_CV;
852
853 if(level != old_level) {
854 if(level == 1) {
855 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
856
857 if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
858 /* 1 bit */
859 emit(1);
860 active = 1;
861 LED_A_ON();
862 } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
863 /* 0 bit */
864 emit(0);
865 active = 1;
866 LED_A_ON();
867 } else if (active) {
868 /* invalid */
869 emit(-1);
870 active = 0;
871 LED_A_OFF();
872 }
873 }
874 }
875
876 /* Frame end */
877 if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) {
878 emit(-1);
879 active = 0;
880 LED_A_OFF();
881 }
882
883 if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) {
884 timer->TC_CCR = AT91C_TC_CLKDIS;
885 }
886
887 old_level = level;
888 WDT_HIT();
889 }
890 if ( MF_DBGLEVEL >= 1) DbpString("Stopped");
891 LEDsoff();
892 }
893
894 //-----------------------------------------------------------------------------
895 // Code up a string of octets at layer 2 (including CRC, we don't generate
896 // that here) so that they can be transmitted to the reader. Doesn't transmit
897 // them yet, just leaves them ready to send in ToSend[].
898 //-----------------------------------------------------------------------------
899 // static void CodeLegicAsTag(const uint8_t *cmd, int len)
900 // {
901 // int i;
902
903 // ToSendReset();
904
905 // // Transmit a burst of ones, as the initial thing that lets the
906 // // reader get phase sync. This (TR1) must be > 80/fs, per spec,
907 // // but tag that I've tried (a Paypass) exceeds that by a fair bit,
908 // // so I will too.
909 // for(i = 0; i < 20; i++) {
910 // ToSendStuffBit(1);
911 // ToSendStuffBit(1);
912 // ToSendStuffBit(1);
913 // ToSendStuffBit(1);
914 // }
915
916 // // Send SOF.
917 // for(i = 0; i < 10; i++) {
918 // ToSendStuffBit(0);
919 // ToSendStuffBit(0);
920 // ToSendStuffBit(0);
921 // ToSendStuffBit(0);
922 // }
923 // for(i = 0; i < 2; i++) {
924 // ToSendStuffBit(1);
925 // ToSendStuffBit(1);
926 // ToSendStuffBit(1);
927 // ToSendStuffBit(1);
928 // }
929
930 // for(i = 0; i < len; i++) {
931 // int j;
932 // uint8_t b = cmd[i];
933
934 // // Start bit
935 // ToSendStuffBit(0);
936 // ToSendStuffBit(0);
937 // ToSendStuffBit(0);
938 // ToSendStuffBit(0);
939
940 // // Data bits
941 // for(j = 0; j < 8; j++) {
942 // if(b & 1) {
943 // ToSendStuffBit(1);
944 // ToSendStuffBit(1);
945 // ToSendStuffBit(1);
946 // ToSendStuffBit(1);
947 // } else {
948 // ToSendStuffBit(0);
949 // ToSendStuffBit(0);
950 // ToSendStuffBit(0);
951 // ToSendStuffBit(0);
952 // }
953 // b >>= 1;
954 // }
955
956 // // Stop bit
957 // ToSendStuffBit(1);
958 // ToSendStuffBit(1);
959 // ToSendStuffBit(1);
960 // ToSendStuffBit(1);
961 // }
962
963 // // Send EOF.
964 // for(i = 0; i < 10; i++) {
965 // ToSendStuffBit(0);
966 // ToSendStuffBit(0);
967 // ToSendStuffBit(0);
968 // ToSendStuffBit(0);
969 // }
970 // for(i = 0; i < 2; i++) {
971 // ToSendStuffBit(1);
972 // ToSendStuffBit(1);
973 // ToSendStuffBit(1);
974 // ToSendStuffBit(1);
975 // }
976
977 // // Convert from last byte pos to length
978 // ToSendMax++;
979 // }
980
981 //-----------------------------------------------------------------------------
982 // The software UART that receives commands from the reader, and its state
983 // variables.
984 //-----------------------------------------------------------------------------
985 /*
986 static struct {
987 enum {
988 STATE_UNSYNCD,
989 STATE_GOT_FALLING_EDGE_OF_SOF,
990 STATE_AWAITING_START_BIT,
991 STATE_RECEIVING_DATA
992 } state;
993 uint16_t shiftReg;
994 int bitCnt;
995 int byteCnt;
996 int byteCntMax;
997 int posCnt;
998 uint8_t *output;
999 } Uart;
1000 */
1001 /* Receive & handle a bit coming from the reader.
1002 *
1003 * This function is called 4 times per bit (every 2 subcarrier cycles).
1004 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1005 *
1006 * LED handling:
1007 * LED A -> ON once we have received the SOF and are expecting the rest.
1008 * LED A -> OFF once we have received EOF or are in error state or unsynced
1009 *
1010 * Returns: true if we received a EOF
1011 * false if we are still waiting for some more
1012 */
1013 // static RAMFUNC int HandleLegicUartBit(uint8_t bit)
1014 // {
1015 // switch(Uart.state) {
1016 // case STATE_UNSYNCD:
1017 // if(!bit) {
1018 // // we went low, so this could be the beginning of an SOF
1019 // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
1020 // Uart.posCnt = 0;
1021 // Uart.bitCnt = 0;
1022 // }
1023 // break;
1024
1025 // case STATE_GOT_FALLING_EDGE_OF_SOF:
1026 // Uart.posCnt++;
1027 // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
1028 // if(bit) {
1029 // if(Uart.bitCnt > 9) {
1030 // // we've seen enough consecutive
1031 // // zeros that it's a valid SOF
1032 // Uart.posCnt = 0;
1033 // Uart.byteCnt = 0;
1034 // Uart.state = STATE_AWAITING_START_BIT;
1035 // LED_A_ON(); // Indicate we got a valid SOF
1036 // } else {
1037 // // didn't stay down long enough
1038 // // before going high, error
1039 // Uart.state = STATE_UNSYNCD;
1040 // }
1041 // } else {
1042 // // do nothing, keep waiting
1043 // }
1044 // Uart.bitCnt++;
1045 // }
1046 // if(Uart.posCnt >= 4) Uart.posCnt = 0;
1047 // if(Uart.bitCnt > 12) {
1048 // // Give up if we see too many zeros without
1049 // // a one, too.
1050 // LED_A_OFF();
1051 // Uart.state = STATE_UNSYNCD;
1052 // }
1053 // break;
1054
1055 // case STATE_AWAITING_START_BIT:
1056 // Uart.posCnt++;
1057 // if(bit) {
1058 // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
1059 // // stayed high for too long between
1060 // // characters, error
1061 // Uart.state = STATE_UNSYNCD;
1062 // }
1063 // } else {
1064 // // falling edge, this starts the data byte
1065 // Uart.posCnt = 0;
1066 // Uart.bitCnt = 0;
1067 // Uart.shiftReg = 0;
1068 // Uart.state = STATE_RECEIVING_DATA;
1069 // }
1070 // break;
1071
1072 // case STATE_RECEIVING_DATA:
1073 // Uart.posCnt++;
1074 // if(Uart.posCnt == 2) {
1075 // // time to sample a bit
1076 // Uart.shiftReg >>= 1;
1077 // if(bit) {
1078 // Uart.shiftReg |= 0x200;
1079 // }
1080 // Uart.bitCnt++;
1081 // }
1082 // if(Uart.posCnt >= 4) {
1083 // Uart.posCnt = 0;
1084 // }
1085 // if(Uart.bitCnt == 10) {
1086 // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
1087 // {
1088 // // this is a data byte, with correct
1089 // // start and stop bits
1090 // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
1091 // Uart.byteCnt++;
1092
1093 // if(Uart.byteCnt >= Uart.byteCntMax) {
1094 // // Buffer overflowed, give up
1095 // LED_A_OFF();
1096 // Uart.state = STATE_UNSYNCD;
1097 // } else {
1098 // // so get the next byte now
1099 // Uart.posCnt = 0;
1100 // Uart.state = STATE_AWAITING_START_BIT;
1101 // }
1102 // } else if (Uart.shiftReg == 0x000) {
1103 // // this is an EOF byte
1104 // LED_A_OFF(); // Finished receiving
1105 // Uart.state = STATE_UNSYNCD;
1106 // if (Uart.byteCnt != 0) {
1107 // return TRUE;
1108 // }
1109 // } else {
1110 // // this is an error
1111 // LED_A_OFF();
1112 // Uart.state = STATE_UNSYNCD;
1113 // }
1114 // }
1115 // break;
1116
1117 // default:
1118 // LED_A_OFF();
1119 // Uart.state = STATE_UNSYNCD;
1120 // break;
1121 // }
1122
1123 // return FALSE;
1124 // }
1125 /*
1126
1127 static void UartReset() {
1128 Uart.byteCntMax = 3;
1129 Uart.state = STATE_UNSYNCD;
1130 Uart.byteCnt = 0;
1131 Uart.bitCnt = 0;
1132 Uart.posCnt = 0;
1133 memset(Uart.output, 0x00, 3);
1134 }
1135 */
1136 // static void UartInit(uint8_t *data) {
1137 // Uart.output = data;
1138 // UartReset();
1139 // }
1140
1141 //=============================================================================
1142 // An LEGIC reader. We take layer two commands, code them
1143 // appropriately, and then send them to the tag. We then listen for the
1144 // tag's response, which we leave in the buffer to be demodulated on the
1145 // PC side.
1146 //=============================================================================
1147 /*
1148 static struct {
1149 enum {
1150 DEMOD_UNSYNCD,
1151 DEMOD_PHASE_REF_TRAINING,
1152 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
1153 DEMOD_GOT_FALLING_EDGE_OF_SOF,
1154 DEMOD_AWAITING_START_BIT,
1155 DEMOD_RECEIVING_DATA
1156 } state;
1157 int bitCount;
1158 int posCount;
1159 int thisBit;
1160 uint16_t shiftReg;
1161 uint8_t *output;
1162 int len;
1163 int sumI;
1164 int sumQ;
1165 } Demod;
1166 */
1167 /*
1168 * Handles reception of a bit from the tag
1169 *
1170 * This function is called 2 times per bit (every 4 subcarrier cycles).
1171 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1172 *
1173 * LED handling:
1174 * LED C -> ON once we have received the SOF and are expecting the rest.
1175 * LED C -> OFF once we have received EOF or are unsynced
1176 *
1177 * Returns: true if we received a EOF
1178 * false if we are still waiting for some more
1179 *
1180 */
1181
1182 /*
1183 static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq)
1184 {
1185 int v = 0;
1186 int ai = ABS(ci);
1187 int aq = ABS(cq);
1188 int halfci = (ai >> 1);
1189 int halfcq = (aq >> 1);
1190
1191 switch(Demod.state) {
1192 case DEMOD_UNSYNCD:
1193
1194 CHECK_FOR_SUBCARRIER()
1195
1196 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
1197 Demod.state = DEMOD_PHASE_REF_TRAINING;
1198 Demod.sumI = ci;
1199 Demod.sumQ = cq;
1200 Demod.posCount = 1;
1201 }
1202 break;
1203
1204 case DEMOD_PHASE_REF_TRAINING:
1205 if(Demod.posCount < 8) {
1206
1207 CHECK_FOR_SUBCARRIER()
1208
1209 if (v > SUBCARRIER_DETECT_THRESHOLD) {
1210 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
1211 // note: synchronization time > 80 1/fs
1212 Demod.sumI += ci;
1213 Demod.sumQ += cq;
1214 ++Demod.posCount;
1215 } else {
1216 // subcarrier lost
1217 Demod.state = DEMOD_UNSYNCD;
1218 }
1219 } else {
1220 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
1221 }
1222 break;
1223
1224 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
1225
1226 MAKE_SOFT_DECISION()
1227
1228 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
1229 // logic '0' detected
1230 if (v <= 0) {
1231
1232 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
1233
1234 // start of SOF sequence
1235 Demod.posCount = 0;
1236 } else {
1237 // maximum length of TR1 = 200 1/fs
1238 if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
1239 }
1240 ++Demod.posCount;
1241 break;
1242
1243 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
1244 ++Demod.posCount;
1245
1246 MAKE_SOFT_DECISION()
1247
1248 if(v > 0) {
1249 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
1250 if(Demod.posCount < 10*2) {
1251 Demod.state = DEMOD_UNSYNCD;
1252 } else {
1253 LED_C_ON(); // Got SOF
1254 Demod.state = DEMOD_AWAITING_START_BIT;
1255 Demod.posCount = 0;
1256 Demod.len = 0;
1257 }
1258 } else {
1259 // low phase of SOF too long (> 12 etu)
1260 if(Demod.posCount > 13*2) {
1261 Demod.state = DEMOD_UNSYNCD;
1262 LED_C_OFF();
1263 }
1264 }
1265 break;
1266
1267 case DEMOD_AWAITING_START_BIT:
1268 ++Demod.posCount;
1269
1270 MAKE_SOFT_DECISION()
1271
1272 if(v > 0) {
1273 // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
1274 if(Demod.posCount > 3*2) {
1275 Demod.state = DEMOD_UNSYNCD;
1276 LED_C_OFF();
1277 }
1278 } else {
1279 // start bit detected
1280 Demod.bitCount = 0;
1281 Demod.posCount = 1; // this was the first half
1282 Demod.thisBit = v;
1283 Demod.shiftReg = 0;
1284 Demod.state = DEMOD_RECEIVING_DATA;
1285 }
1286 break;
1287
1288 case DEMOD_RECEIVING_DATA:
1289
1290 MAKE_SOFT_DECISION()
1291
1292 if(Demod.posCount == 0) {
1293 // first half of bit
1294 Demod.thisBit = v;
1295 Demod.posCount = 1;
1296 } else {
1297 // second half of bit
1298 Demod.thisBit += v;
1299 Demod.shiftReg >>= 1;
1300 // logic '1'
1301 if(Demod.thisBit > 0)
1302 Demod.shiftReg |= 0x200;
1303
1304 ++Demod.bitCount;
1305
1306 if(Demod.bitCount == 10) {
1307
1308 uint16_t s = Demod.shiftReg;
1309
1310 if((s & 0x200) && !(s & 0x001)) {
1311 // stop bit == '1', start bit == '0'
1312 uint8_t b = (s >> 1);
1313 Demod.output[Demod.len] = b;
1314 ++Demod.len;
1315 Demod.state = DEMOD_AWAITING_START_BIT;
1316 } else {
1317 Demod.state = DEMOD_UNSYNCD;
1318 LED_C_OFF();
1319
1320 if(s == 0x000) {
1321 // This is EOF (start, stop and all data bits == '0'
1322 return TRUE;
1323 }
1324 }
1325 }
1326 Demod.posCount = 0;
1327 }
1328 break;
1329
1330 default:
1331 Demod.state = DEMOD_UNSYNCD;
1332 LED_C_OFF();
1333 break;
1334 }
1335 return FALSE;
1336 }
1337 */
1338 /*
1339 // Clear out the state of the "UART" that receives from the tag.
1340 static void DemodReset() {
1341 Demod.len = 0;
1342 Demod.state = DEMOD_UNSYNCD;
1343 Demod.posCount = 0;
1344 Demod.sumI = 0;
1345 Demod.sumQ = 0;
1346 Demod.bitCount = 0;
1347 Demod.thisBit = 0;
1348 Demod.shiftReg = 0;
1349 memset(Demod.output, 0x00, 3);
1350 }
1351
1352 static void DemodInit(uint8_t *data) {
1353 Demod.output = data;
1354 DemodReset();
1355 }
1356 */
1357
1358 /*
1359 * Demodulate the samples we received from the tag, also log to tracebuffer
1360 * quiet: set to 'TRUE' to disable debug output
1361 */
1362
1363 /*
1364 #define LEGIC_DMA_BUFFER_SIZE 256
1365
1366 static void GetSamplesForLegicDemod(int n, bool quiet)
1367 {
1368 int max = 0;
1369 bool gotFrame = FALSE;
1370 int lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1371 int ci, cq, samples = 0;
1372
1373 BigBuf_free();
1374
1375 // And put the FPGA in the appropriate mode
1376 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ);
1377
1378 // The response (tag -> reader) that we're receiving.
1379 // Set up the demodulator for tag -> reader responses.
1380 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1381
1382 // The DMA buffer, used to stream samples from the FPGA
1383 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE);
1384 int8_t *upTo = dmaBuf;
1385
1386 // Setup and start DMA.
1387 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){
1388 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1389 return;
1390 }
1391
1392 // Signal field is ON with the appropriate LED:
1393 LED_D_ON();
1394 for(;;) {
1395 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
1396 if(behindBy > max) max = behindBy;
1397
1398 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) {
1399 ci = upTo[0];
1400 cq = upTo[1];
1401 upTo += 2;
1402 if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) {
1403 upTo = dmaBuf;
1404 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
1405 AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE;
1406 }
1407 lastRxCounter -= 2;
1408 if(lastRxCounter <= 0)
1409 lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1410
1411 samples += 2;
1412
1413 gotFrame = HandleLegicSamplesDemod(ci , cq );
1414 if ( gotFrame )
1415 break;
1416 }
1417
1418 if(samples > n || gotFrame)
1419 break;
1420 }
1421
1422 FpgaDisableSscDma();
1423
1424 if (!quiet && Demod.len == 0) {
1425 Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
1426 max,
1427 samples,
1428 gotFrame,
1429 Demod.len,
1430 Demod.sumI,
1431 Demod.sumQ
1432 );
1433 }
1434
1435 //Tracing
1436 if (Demod.len > 0) {
1437 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1438 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
1439 }
1440 }
1441
1442 */
1443
1444 //-----------------------------------------------------------------------------
1445 // Transmit the command (to the tag) that was placed in ToSend[].
1446 //-----------------------------------------------------------------------------
1447 /*
1448 static void TransmitForLegic(void)
1449 {
1450 int c;
1451
1452 FpgaSetupSsc();
1453
1454 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
1455 AT91C_BASE_SSC->SSC_THR = 0xff;
1456
1457 // Signal field is ON with the appropriate Red LED
1458 LED_D_ON();
1459
1460 // Signal we are transmitting with the Green LED
1461 LED_B_ON();
1462 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1463
1464 for(c = 0; c < 10;) {
1465 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1466 AT91C_BASE_SSC->SSC_THR = 0xff;
1467 c++;
1468 }
1469 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1470 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1471 (void)r;
1472 }
1473 WDT_HIT();
1474 }
1475
1476 c = 0;
1477 for(;;) {
1478 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1479 AT91C_BASE_SSC->SSC_THR = ToSend[c];
1480 legic_prng_forward(1); // forward the lfsr
1481 c++;
1482 if(c >= ToSendMax) {
1483 break;
1484 }
1485 }
1486 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1487 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1488 (void)r;
1489 }
1490 WDT_HIT();
1491 }
1492 LED_B_OFF();
1493 }
1494 */
1495
1496 //-----------------------------------------------------------------------------
1497 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1498 // so that it is ready to transmit to the tag using TransmitForLegic().
1499 //-----------------------------------------------------------------------------
1500 /*
1501 static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1502 {
1503 int i, j;
1504 uint8_t b;
1505
1506 ToSendReset();
1507
1508 // Send SOF
1509 for(i = 0; i < 7; i++)
1510 ToSendStuffBit(1);
1511
1512
1513 for(i = 0; i < cmdlen; i++) {
1514 // Start bit
1515 ToSendStuffBit(0);
1516
1517 // Data bits
1518 b = cmd[i];
1519 for(j = 0; j < bits; j++) {
1520 if(b & 1) {
1521 ToSendStuffBit(1);
1522 } else {
1523 ToSendStuffBit(0);
1524 }
1525 b >>= 1;
1526 }
1527 }
1528
1529 // Convert from last character reference to length
1530 ++ToSendMax;
1531 }
1532 */
1533 /**
1534 Convenience function to encode, transmit and trace Legic comms
1535 **/
1536 /*
1537 static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1538 {
1539 CodeLegicBitsAsReader(cmd, cmdlen, bits);
1540 TransmitForLegic();
1541 if (tracing) {
1542 uint8_t parity[1] = {0x00};
1543 LogTrace(cmd, cmdlen, 0, 0, parity, TRUE);
1544 }
1545 }
1546
1547 */
1548 // Set up LEGIC communication
1549 /*
1550 void ice_legic_setup() {
1551
1552 // standard things.
1553 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1554 BigBuf_free(); BigBuf_Clear_ext(false);
1555 clear_trace();
1556 set_tracing(TRUE);
1557 DemodReset();
1558 UartReset();
1559
1560 // Set up the synchronous serial port
1561 FpgaSetupSsc();
1562
1563 // connect Demodulated Signal to ADC:
1564 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1565
1566 // Signal field is on with the appropriate LED
1567 LED_D_ON();
1568 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1569 SpinDelay(20);
1570 // Start the timer
1571 //StartCountSspClk();
1572
1573 // initalize CRC
1574 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
1575
1576 // initalize prng
1577 legic_prng_init(0);
1578 }
1579 */
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