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Support TCP ports for proxmark (#720)
[proxmark3-svn] / armsrc / iso14443b.c
1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, split Nov 2006
3 // piwi 2018
4 //
5 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
6 // at your option, any later version. See the LICENSE.txt file for the text of
7 // the license.
8 //-----------------------------------------------------------------------------
9 // Routines to support ISO 14443B. This includes both the reader software and
10 // the `fake tag' modes.
11 //-----------------------------------------------------------------------------
12
13 #include "proxmark3.h"
14 #include "apps.h"
15 #include "util.h"
16 #include "string.h"
17
18 #include "iso14443crc.h"
19
20 #define RECEIVE_SAMPLES_TIMEOUT 1000 // TR0 max is 256/fs = 256/(848kHz) = 302us or 64 samples from FPGA. 1000 seems to be much too high?
21 #define ISO14443B_DMA_BUFFER_SIZE 128
22
23 // PCB Block number for APDUs
24 static uint8_t pcb_blocknum = 0;
25
26 //=============================================================================
27 // An ISO 14443 Type B tag. We listen for commands from the reader, using
28 // a UART kind of thing that's implemented in software. When we get a
29 // frame (i.e., a group of bytes between SOF and EOF), we check the CRC.
30 // If it's good, then we can do something appropriate with it, and send
31 // a response.
32 //=============================================================================
33
34 //-----------------------------------------------------------------------------
35 // Code up a string of octets at layer 2 (including CRC, we don't generate
36 // that here) so that they can be transmitted to the reader. Doesn't transmit
37 // them yet, just leaves them ready to send in ToSend[].
38 //-----------------------------------------------------------------------------
39 static void CodeIso14443bAsTag(const uint8_t *cmd, int len)
40 {
41 int i;
42
43 ToSendReset();
44
45 // Transmit a burst of ones, as the initial thing that lets the
46 // reader get phase sync. This (TR1) must be > 80/fs, per spec,
47 // but tag that I've tried (a Paypass) exceeds that by a fair bit,
48 // so I will too.
49 for(i = 0; i < 20; i++) {
50 ToSendStuffBit(1);
51 ToSendStuffBit(1);
52 ToSendStuffBit(1);
53 ToSendStuffBit(1);
54 }
55
56 // Send SOF.
57 for(i = 0; i < 10; i++) {
58 ToSendStuffBit(0);
59 ToSendStuffBit(0);
60 ToSendStuffBit(0);
61 ToSendStuffBit(0);
62 }
63 for(i = 0; i < 2; i++) {
64 ToSendStuffBit(1);
65 ToSendStuffBit(1);
66 ToSendStuffBit(1);
67 ToSendStuffBit(1);
68 }
69
70 for(i = 0; i < len; i++) {
71 int j;
72 uint8_t b = cmd[i];
73
74 // Start bit
75 ToSendStuffBit(0);
76 ToSendStuffBit(0);
77 ToSendStuffBit(0);
78 ToSendStuffBit(0);
79
80 // Data bits
81 for(j = 0; j < 8; j++) {
82 if(b & 1) {
83 ToSendStuffBit(1);
84 ToSendStuffBit(1);
85 ToSendStuffBit(1);
86 ToSendStuffBit(1);
87 } else {
88 ToSendStuffBit(0);
89 ToSendStuffBit(0);
90 ToSendStuffBit(0);
91 ToSendStuffBit(0);
92 }
93 b >>= 1;
94 }
95
96 // Stop bit
97 ToSendStuffBit(1);
98 ToSendStuffBit(1);
99 ToSendStuffBit(1);
100 ToSendStuffBit(1);
101 }
102
103 // Send EOF.
104 for(i = 0; i < 10; i++) {
105 ToSendStuffBit(0);
106 ToSendStuffBit(0);
107 ToSendStuffBit(0);
108 ToSendStuffBit(0);
109 }
110 for(i = 0; i < 2; i++) {
111 ToSendStuffBit(1);
112 ToSendStuffBit(1);
113 ToSendStuffBit(1);
114 ToSendStuffBit(1);
115 }
116
117 // Convert from last byte pos to length
118 ToSendMax++;
119 }
120
121 //-----------------------------------------------------------------------------
122 // The software UART that receives commands from the reader, and its state
123 // variables.
124 //-----------------------------------------------------------------------------
125 static struct {
126 enum {
127 STATE_UNSYNCD,
128 STATE_GOT_FALLING_EDGE_OF_SOF,
129 STATE_AWAITING_START_BIT,
130 STATE_RECEIVING_DATA
131 } state;
132 uint16_t shiftReg;
133 int bitCnt;
134 int byteCnt;
135 int byteCntMax;
136 int posCnt;
137 uint8_t *output;
138 } Uart;
139
140 /* Receive & handle a bit coming from the reader.
141 *
142 * This function is called 4 times per bit (every 2 subcarrier cycles).
143 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 2,36us
144 *
145 * LED handling:
146 * LED A -> ON once we have received the SOF and are expecting the rest.
147 * LED A -> OFF once we have received EOF or are in error state or unsynced
148 *
149 * Returns: true if we received a EOF
150 * false if we are still waiting for some more
151 */
152 static RAMFUNC int Handle14443bUartBit(uint8_t bit)
153 {
154 switch(Uart.state) {
155 case STATE_UNSYNCD:
156 if(!bit) {
157 // we went low, so this could be the beginning
158 // of an SOF
159 Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
160 Uart.posCnt = 0;
161 Uart.bitCnt = 0;
162 }
163 break;
164
165 case STATE_GOT_FALLING_EDGE_OF_SOF:
166 Uart.posCnt++;
167 if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
168 if(bit) {
169 if(Uart.bitCnt > 9) {
170 // we've seen enough consecutive
171 // zeros that it's a valid SOF
172 Uart.posCnt = 0;
173 Uart.byteCnt = 0;
174 Uart.state = STATE_AWAITING_START_BIT;
175 LED_A_ON(); // Indicate we got a valid SOF
176 } else {
177 // didn't stay down long enough
178 // before going high, error
179 Uart.state = STATE_UNSYNCD;
180 }
181 } else {
182 // do nothing, keep waiting
183 }
184 Uart.bitCnt++;
185 }
186 if(Uart.posCnt >= 4) Uart.posCnt = 0;
187 if(Uart.bitCnt > 12) {
188 // Give up if we see too many zeros without
189 // a one, too.
190 LED_A_OFF();
191 Uart.state = STATE_UNSYNCD;
192 }
193 break;
194
195 case STATE_AWAITING_START_BIT:
196 Uart.posCnt++;
197 if(bit) {
198 if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
199 // stayed high for too long between
200 // characters, error
201 Uart.state = STATE_UNSYNCD;
202 }
203 } else {
204 // falling edge, this starts the data byte
205 Uart.posCnt = 0;
206 Uart.bitCnt = 0;
207 Uart.shiftReg = 0;
208 Uart.state = STATE_RECEIVING_DATA;
209 }
210 break;
211
212 case STATE_RECEIVING_DATA:
213 Uart.posCnt++;
214 if(Uart.posCnt == 2) {
215 // time to sample a bit
216 Uart.shiftReg >>= 1;
217 if(bit) {
218 Uart.shiftReg |= 0x200;
219 }
220 Uart.bitCnt++;
221 }
222 if(Uart.posCnt >= 4) {
223 Uart.posCnt = 0;
224 }
225 if(Uart.bitCnt == 10) {
226 if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
227 {
228 // this is a data byte, with correct
229 // start and stop bits
230 Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
231 Uart.byteCnt++;
232
233 if(Uart.byteCnt >= Uart.byteCntMax) {
234 // Buffer overflowed, give up
235 LED_A_OFF();
236 Uart.state = STATE_UNSYNCD;
237 } else {
238 // so get the next byte now
239 Uart.posCnt = 0;
240 Uart.state = STATE_AWAITING_START_BIT;
241 }
242 } else if (Uart.shiftReg == 0x000) {
243 // this is an EOF byte
244 LED_A_OFF(); // Finished receiving
245 Uart.state = STATE_UNSYNCD;
246 if (Uart.byteCnt != 0) {
247 return true;
248 }
249 } else {
250 // this is an error
251 LED_A_OFF();
252 Uart.state = STATE_UNSYNCD;
253 }
254 }
255 break;
256
257 default:
258 LED_A_OFF();
259 Uart.state = STATE_UNSYNCD;
260 break;
261 }
262
263 return false;
264 }
265
266
267 static void UartReset()
268 {
269 Uart.byteCntMax = MAX_FRAME_SIZE;
270 Uart.state = STATE_UNSYNCD;
271 Uart.byteCnt = 0;
272 Uart.bitCnt = 0;
273 }
274
275
276 static void UartInit(uint8_t *data)
277 {
278 Uart.output = data;
279 UartReset();
280 }
281
282
283 //-----------------------------------------------------------------------------
284 // Receive a command (from the reader to us, where we are the simulated tag),
285 // and store it in the given buffer, up to the given maximum length. Keeps
286 // spinning, waiting for a well-framed command, until either we get one
287 // (returns true) or someone presses the pushbutton on the board (false).
288 //
289 // Assume that we're called with the SSC (to the FPGA) and ADC path set
290 // correctly.
291 //-----------------------------------------------------------------------------
292 static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len)
293 {
294 // Set FPGA mode to "simulated ISO 14443B tag", no modulation (listen
295 // only, since we are receiving, not transmitting).
296 // Signal field is off with the appropriate LED
297 LED_D_OFF();
298 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
299
300 // Now run a `software UART' on the stream of incoming samples.
301 UartInit(received);
302
303 for(;;) {
304 WDT_HIT();
305
306 if(BUTTON_PRESS()) return false;
307
308 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
309 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
310 for(uint8_t mask = 0x80; mask != 0x00; mask >>= 1) {
311 if(Handle14443bUartBit(b & mask)) {
312 *len = Uart.byteCnt;
313 return true;
314 }
315 }
316 }
317 }
318
319 return false;
320 }
321
322 //-----------------------------------------------------------------------------
323 // Main loop of simulated tag: receive commands from reader, decide what
324 // response to send, and send it.
325 //-----------------------------------------------------------------------------
326 void SimulateIso14443bTag(void)
327 {
328 // the only commands we understand is WUPB, AFI=0, Select All, N=1:
329 static const uint8_t cmd1[] = { 0x05, 0x00, 0x08, 0x39, 0x73 }; // WUPB
330 // ... and REQB, AFI=0, Normal Request, N=1:
331 static const uint8_t cmd2[] = { 0x05, 0x00, 0x00, 0x71, 0xFF }; // REQB
332 // ... and HLTB
333 static const uint8_t cmd3[] = { 0x50, 0xff, 0xff, 0xff, 0xff }; // HLTB
334 // ... and ATTRIB
335 static const uint8_t cmd4[] = { 0x1D, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; // ATTRIB
336
337 // ... and we always respond with ATQB, PUPI = 820de174, Application Data = 0x20381922,
338 // supports only 106kBit/s in both directions, max frame size = 32Bytes,
339 // supports ISO14443-4, FWI=8 (77ms), NAD supported, CID not supported:
340 static const uint8_t response1[] = {
341 0x50, 0x82, 0x0d, 0xe1, 0x74, 0x20, 0x38, 0x19, 0x22,
342 0x00, 0x21, 0x85, 0x5e, 0xd7
343 };
344 // response to HLTB and ATTRIB
345 static const uint8_t response2[] = {0x00, 0x78, 0xF0};
346
347
348 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
349
350 clear_trace();
351 set_tracing(true);
352
353 const uint8_t *resp;
354 uint8_t *respCode;
355 uint16_t respLen, respCodeLen;
356
357 // allocate command receive buffer
358 BigBuf_free();
359 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
360
361 uint16_t len;
362 uint16_t cmdsRecvd = 0;
363
364 // prepare the (only one) tag answer:
365 CodeIso14443bAsTag(response1, sizeof(response1));
366 uint8_t *resp1Code = BigBuf_malloc(ToSendMax);
367 memcpy(resp1Code, ToSend, ToSendMax);
368 uint16_t resp1CodeLen = ToSendMax;
369
370 // prepare the (other) tag answer:
371 CodeIso14443bAsTag(response2, sizeof(response2));
372 uint8_t *resp2Code = BigBuf_malloc(ToSendMax);
373 memcpy(resp2Code, ToSend, ToSendMax);
374 uint16_t resp2CodeLen = ToSendMax;
375
376 // We need to listen to the high-frequency, peak-detected path.
377 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
378 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SIMULATOR);
379
380 cmdsRecvd = 0;
381
382 for(;;) {
383
384 if(!GetIso14443bCommandFromReader(receivedCmd, &len)) {
385 Dbprintf("button pressed, received %d commands", cmdsRecvd);
386 break;
387 }
388
389 if (tracing) {
390 uint8_t parity[MAX_PARITY_SIZE];
391 LogTrace(receivedCmd, len, 0, 0, parity, true);
392 }
393
394 // Good, look at the command now.
395 if ( (len == sizeof(cmd1) && memcmp(receivedCmd, cmd1, len) == 0)
396 || (len == sizeof(cmd2) && memcmp(receivedCmd, cmd2, len) == 0) ) {
397 resp = response1;
398 respLen = sizeof(response1);
399 respCode = resp1Code;
400 respCodeLen = resp1CodeLen;
401 } else if ( (len == sizeof(cmd3) && receivedCmd[0] == cmd3[0])
402 || (len == sizeof(cmd4) && receivedCmd[0] == cmd4[0]) ) {
403 resp = response2;
404 respLen = sizeof(response2);
405 respCode = resp2Code;
406 respCodeLen = resp2CodeLen;
407 } else {
408 Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsRecvd);
409 // And print whether the CRC fails, just for good measure
410 uint8_t b1, b2;
411 if (len >= 3){ // if crc exists
412 ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);
413 if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1]) {
414 // Not so good, try again.
415 DbpString("+++CRC fail");
416
417 } else {
418 DbpString("CRC passes");
419 }
420 }
421 //get rid of compiler warning
422 respCodeLen = 0;
423 resp = response1;
424 respLen = 0;
425 respCode = resp1Code;
426 //don't crash at new command just wait and see if reader will send other new cmds.
427 //break;
428 }
429
430 cmdsRecvd++;
431
432 if(cmdsRecvd > 0x30) {
433 DbpString("many commands later...");
434 break;
435 }
436
437 if(respCodeLen <= 0) continue;
438
439 // Modulate BPSK
440 // Signal field is off with the appropriate LED
441 LED_D_OFF();
442 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
443 AT91C_BASE_SSC->SSC_THR = 0xff;
444 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SIMULATOR);
445
446 // Transmit the response.
447 uint16_t i = 0;
448 for(;;) {
449 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
450 uint8_t b = respCode[i];
451
452 AT91C_BASE_SSC->SSC_THR = b;
453
454 i++;
455 if(i > respCodeLen) {
456 break;
457 }
458 }
459 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
460 volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
461 (void)b;
462 }
463 }
464
465 // trace the response:
466 if (tracing) {
467 uint8_t parity[MAX_PARITY_SIZE];
468 LogTrace(resp, respLen, 0, 0, parity, false);
469 }
470
471 }
472 }
473
474 //=============================================================================
475 // An ISO 14443 Type B reader. We take layer two commands, code them
476 // appropriately, and then send them to the tag. We then listen for the
477 // tag's response, which we leave in the buffer to be demodulated on the
478 // PC side.
479 //=============================================================================
480
481 static struct {
482 enum {
483 DEMOD_UNSYNCD,
484 DEMOD_PHASE_REF_TRAINING,
485 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
486 DEMOD_GOT_FALLING_EDGE_OF_SOF,
487 DEMOD_AWAITING_START_BIT,
488 DEMOD_RECEIVING_DATA
489 } state;
490 int bitCount;
491 int posCount;
492 int thisBit;
493 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
494 int metric;
495 int metricN;
496 */
497 uint16_t shiftReg;
498 uint8_t *output;
499 int len;
500 int sumI;
501 int sumQ;
502 } Demod;
503
504 /*
505 * Handles reception of a bit from the tag
506 *
507 * This function is called 2 times per bit (every 4 subcarrier cycles).
508 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 4,72us
509 *
510 * LED handling:
511 * LED C -> ON once we have received the SOF and are expecting the rest.
512 * LED C -> OFF once we have received EOF or are unsynced
513 *
514 * Returns: true if we received a EOF
515 * false if we are still waiting for some more
516 *
517 */
518 static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
519 {
520 int v;
521
522 // The soft decision on the bit uses an estimate of just the
523 // quadrant of the reference angle, not the exact angle.
524 #define MAKE_SOFT_DECISION() { \
525 if(Demod.sumI > 0) { \
526 v = ci; \
527 } else { \
528 v = -ci; \
529 } \
530 if(Demod.sumQ > 0) { \
531 v += cq; \
532 } else { \
533 v -= cq; \
534 } \
535 }
536
537 #define SUBCARRIER_DETECT_THRESHOLD 8
538
539 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
540 #define AMPLITUDE(ci,cq) (MAX(ABS(ci),ABS(cq)) + (MIN(ABS(ci),ABS(cq))/2))
541 switch(Demod.state) {
542 case DEMOD_UNSYNCD:
543 if(AMPLITUDE(ci,cq) > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
544 Demod.state = DEMOD_PHASE_REF_TRAINING;
545 Demod.sumI = ci;
546 Demod.sumQ = cq;
547 Demod.posCount = 1;
548 }
549 break;
550
551 case DEMOD_PHASE_REF_TRAINING:
552 if(Demod.posCount < 8) {
553 if (AMPLITUDE(ci,cq) > SUBCARRIER_DETECT_THRESHOLD) {
554 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
555 // note: synchronization time > 80 1/fs
556 Demod.sumI += ci;
557 Demod.sumQ += cq;
558 Demod.posCount++;
559 } else { // subcarrier lost
560 Demod.state = DEMOD_UNSYNCD;
561 }
562 } else {
563 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
564 }
565 break;
566
567 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
568 MAKE_SOFT_DECISION();
569 if(v < 0) { // logic '0' detected
570 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
571 Demod.posCount = 0; // start of SOF sequence
572 } else {
573 if(Demod.posCount > 200/4) { // maximum length of TR1 = 200 1/fs
574 Demod.state = DEMOD_UNSYNCD;
575 }
576 }
577 Demod.posCount++;
578 break;
579
580 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
581 Demod.posCount++;
582 MAKE_SOFT_DECISION();
583 if(v > 0) {
584 if(Demod.posCount < 9*2) { // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
585 Demod.state = DEMOD_UNSYNCD;
586 } else {
587 LED_C_ON(); // Got SOF
588 Demod.state = DEMOD_AWAITING_START_BIT;
589 Demod.posCount = 0;
590 Demod.len = 0;
591 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
592 Demod.metricN = 0;
593 Demod.metric = 0;
594 */
595 }
596 } else {
597 if(Demod.posCount > 12*2) { // low phase of SOF too long (> 12 etu)
598 Demod.state = DEMOD_UNSYNCD;
599 LED_C_OFF();
600 }
601 }
602 break;
603
604 case DEMOD_AWAITING_START_BIT:
605 Demod.posCount++;
606 MAKE_SOFT_DECISION();
607 if(v > 0) {
608 if(Demod.posCount > 3*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
609 Demod.state = DEMOD_UNSYNCD;
610 LED_C_OFF();
611 }
612 } else { // start bit detected
613 Demod.bitCount = 0;
614 Demod.posCount = 1; // this was the first half
615 Demod.thisBit = v;
616 Demod.shiftReg = 0;
617 Demod.state = DEMOD_RECEIVING_DATA;
618 }
619 break;
620
621 case DEMOD_RECEIVING_DATA:
622 MAKE_SOFT_DECISION();
623 if(Demod.posCount == 0) { // first half of bit
624 Demod.thisBit = v;
625 Demod.posCount = 1;
626 } else { // second half of bit
627 Demod.thisBit += v;
628
629 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
630 if(Demod.thisBit > 0) {
631 Demod.metric += Demod.thisBit;
632 } else {
633 Demod.metric -= Demod.thisBit;
634 }
635 (Demod.metricN)++;
636 */
637
638 Demod.shiftReg >>= 1;
639 if(Demod.thisBit > 0) { // logic '1'
640 Demod.shiftReg |= 0x200;
641 }
642
643 Demod.bitCount++;
644 if(Demod.bitCount == 10) {
645 uint16_t s = Demod.shiftReg;
646 if((s & 0x200) && !(s & 0x001)) { // stop bit == '1', start bit == '0'
647 uint8_t b = (s >> 1);
648 Demod.output[Demod.len] = b;
649 Demod.len++;
650 Demod.state = DEMOD_AWAITING_START_BIT;
651 } else {
652 Demod.state = DEMOD_UNSYNCD;
653 LED_C_OFF();
654 if(s == 0x000) {
655 // This is EOF (start, stop and all data bits == '0'
656 return true;
657 }
658 }
659 }
660 Demod.posCount = 0;
661 }
662 break;
663
664 default:
665 Demod.state = DEMOD_UNSYNCD;
666 LED_C_OFF();
667 break;
668 }
669
670 return false;
671 }
672
673
674 static void DemodReset()
675 {
676 // Clear out the state of the "UART" that receives from the tag.
677 Demod.len = 0;
678 Demod.state = DEMOD_UNSYNCD;
679 Demod.posCount = 0;
680 memset(Demod.output, 0x00, MAX_FRAME_SIZE);
681 }
682
683
684 static void DemodInit(uint8_t *data)
685 {
686 Demod.output = data;
687 DemodReset();
688 }
689
690
691 /*
692 * Demodulate the samples we received from the tag, also log to tracebuffer
693 * quiet: set to 'true' to disable debug output
694 */
695 static void GetSamplesFor14443bDemod(int n, bool quiet)
696 {
697 int maxBehindBy = 0;
698 bool gotFrame = false;
699 int lastRxCounter, samples = 0;
700 int8_t ci, cq;
701
702 // Allocate memory from BigBuf for some buffers
703 // free all previous allocations first
704 BigBuf_free();
705
706 // The response (tag -> reader) that we're receiving.
707 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
708
709 // The DMA buffer, used to stream samples from the FPGA
710 uint16_t *dmaBuf = (uint16_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE * sizeof(uint16_t));
711
712 // Set up the demodulator for tag -> reader responses.
713 DemodInit(receivedResponse);
714
715 // wait for last transfer to complete
716 while (!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXEMPTY))
717
718 // Setup and start DMA.
719 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);
720 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
721
722 uint16_t *upTo = dmaBuf;
723 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
724
725 // Signal field is ON with the appropriate LED:
726 LED_D_ON();
727 // And put the FPGA in the appropriate mode
728 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
729
730 for(;;) {
731 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO14443B_DMA_BUFFER_SIZE-1);
732 if(behindBy > maxBehindBy) {
733 maxBehindBy = behindBy;
734 }
735
736 if(behindBy < 1) continue;
737
738 ci = *upTo >> 8;
739 cq = *upTo;
740 upTo++;
741 lastRxCounter--;
742 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) { // we have read all of the DMA buffer content.
743 upTo = dmaBuf; // start reading the circular buffer from the beginning
744 lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
745 }
746 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_ENDRX)) { // DMA Counter Register had reached 0, already rotated.
747 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf; // refresh the DMA Next Buffer and
748 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE; // DMA Next Counter registers
749 }
750 samples++;
751
752 if(Handle14443bSamplesDemod(ci, cq)) {
753 gotFrame = true;
754 break;
755 }
756
757 if(samples > n) {
758 break;
759 }
760 }
761
762 FpgaDisableSscDma();
763
764 if (!quiet) Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d", maxBehindBy, samples, gotFrame, Demod.len, Demod.sumI, Demod.sumQ);
765 //Tracing
766 if (tracing && Demod.len > 0) {
767 uint8_t parity[MAX_PARITY_SIZE];
768 LogTrace(Demod.output, Demod.len, 0, 0, parity, false);
769 }
770 }
771
772
773 //-----------------------------------------------------------------------------
774 // Transmit the command (to the tag) that was placed in ToSend[].
775 //-----------------------------------------------------------------------------
776 static void TransmitFor14443b(void)
777 {
778 int c;
779
780 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_TX);
781
782 // Signal field is ON with the appropriate Red LED
783 LED_D_ON();
784 // Signal we are transmitting with the Green LED
785 LED_B_ON();
786 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
787
788 c = 0;
789 for(;;) {
790 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
791 AT91C_BASE_SSC->SSC_THR = ~ToSend[c];
792 c++;
793 if(c >= ToSendMax) {
794 break;
795 }
796 }
797 WDT_HIT();
798 }
799 LED_B_OFF(); // Finished sending
800 }
801
802
803 //-----------------------------------------------------------------------------
804 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
805 // so that it is ready to transmit to the tag using TransmitFor14443b().
806 //-----------------------------------------------------------------------------
807 static void CodeIso14443bAsReader(const uint8_t *cmd, int len)
808 {
809 int i, j;
810 uint8_t b;
811
812 ToSendReset();
813
814 // Send SOF
815 for(i = 0; i < 10; i++) {
816 ToSendStuffBit(0);
817 }
818 ToSendStuffBit(1);
819 ToSendStuffBit(1);
820
821 for(i = 0; i < len; i++) {
822 // Start bit
823 ToSendStuffBit(0);
824 // Data bits
825 b = cmd[i];
826 for(j = 0; j < 8; j++) {
827 if(b & 1) {
828 ToSendStuffBit(1);
829 } else {
830 ToSendStuffBit(0);
831 }
832 b >>= 1;
833 }
834 // Stop bit
835 ToSendStuffBit(1);
836 }
837
838 // Send EOF
839 for(i = 0; i < 10; i++) {
840 ToSendStuffBit(0);
841 }
842 ToSendStuffBit(1);
843
844 // ensure that last byte is filled up
845 for(i = 0; i < 8; i++) {
846 ToSendStuffBit(1);
847 }
848
849 // Convert from last character reference to length
850 ToSendMax++;
851 }
852
853
854 /**
855 Convenience function to encode, transmit and trace iso 14443b comms
856 **/
857 static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len)
858 {
859 CodeIso14443bAsReader(cmd, len);
860 TransmitFor14443b();
861 if (tracing) {
862 uint8_t parity[MAX_PARITY_SIZE];
863 LogTrace(cmd,len, 0, 0, parity, true);
864 }
865 }
866
867 /* Sends an APDU to the tag
868 * TODO: check CRC and preamble
869 */
870 int iso14443b_apdu(uint8_t const *message, size_t message_length, uint8_t *response)
871 {
872 uint8_t message_frame[message_length + 4];
873 // PCB
874 message_frame[0] = 0x0A | pcb_blocknum;
875 pcb_blocknum ^= 1;
876 // CID
877 message_frame[1] = 0;
878 // INF
879 memcpy(message_frame + 2, message, message_length);
880 // EDC (CRC)
881 ComputeCrc14443(CRC_14443_B, message_frame, message_length + 2, &message_frame[message_length + 2], &message_frame[message_length + 3]);
882 // send
883 CodeAndTransmit14443bAsReader(message_frame, message_length + 4);
884 // get response
885 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
886 if(Demod.len < 3)
887 {
888 return 0;
889 }
890 // TODO: Check CRC
891 // copy response contents
892 if(response != NULL)
893 {
894 memcpy(response, Demod.output, Demod.len);
895 }
896 return Demod.len;
897 }
898
899 /* Perform the ISO 14443 B Card Selection procedure
900 * Currently does NOT do any collision handling.
901 * It expects 0-1 cards in the device's range.
902 * TODO: Support multiple cards (perform anticollision)
903 * TODO: Verify CRC checksums
904 */
905 int iso14443b_select_card()
906 {
907 // WUPB command (including CRC)
908 // Note: WUPB wakes up all tags, REQB doesn't wake up tags in HALT state
909 static const uint8_t wupb[] = { 0x05, 0x00, 0x08, 0x39, 0x73 };
910 // ATTRIB command (with space for CRC)
911 uint8_t attrib[] = { 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00};
912
913 // first, wake up the tag
914 CodeAndTransmit14443bAsReader(wupb, sizeof(wupb));
915 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
916 // ATQB too short?
917 if (Demod.len < 14)
918 {
919 return 2;
920 }
921
922 // select the tag
923 // copy the PUPI to ATTRIB
924 memcpy(attrib + 1, Demod.output + 1, 4);
925 /* copy the protocol info from ATQB (Protocol Info -> Protocol_Type) into
926 ATTRIB (Param 3) */
927 attrib[7] = Demod.output[10] & 0x0F;
928 ComputeCrc14443(CRC_14443_B, attrib, 9, attrib + 9, attrib + 10);
929 CodeAndTransmit14443bAsReader(attrib, sizeof(attrib));
930 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
931 // Answer to ATTRIB too short?
932 if(Demod.len < 3)
933 {
934 return 2;
935 }
936 // reset PCB block number
937 pcb_blocknum = 0;
938 return 1;
939 }
940
941 // Set up ISO 14443 Type B communication (similar to iso14443a_setup)
942 void iso14443b_setup() {
943 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
944 // Set up the synchronous serial port
945 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_TX);
946 // connect Demodulated Signal to ADC:
947 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
948
949 // Signal field is on with the appropriate LED
950 LED_D_ON();
951 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
952
953 DemodReset();
954 UartReset();
955 }
956
957 //-----------------------------------------------------------------------------
958 // Read a SRI512 ISO 14443B tag.
959 //
960 // SRI512 tags are just simple memory tags, here we're looking at making a dump
961 // of the contents of the memory. No anticollision algorithm is done, we assume
962 // we have a single tag in the field.
963 //
964 // I tried to be systematic and check every answer of the tag, every CRC, etc...
965 //-----------------------------------------------------------------------------
966 void ReadSTMemoryIso14443b(uint32_t dwLast)
967 {
968 uint8_t i = 0x00;
969
970 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
971 // Make sure that we start from off, since the tags are stateful;
972 // confusing things will happen if we don't reset them between reads.
973 LED_D_OFF();
974 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
975 SpinDelay(200);
976
977 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
978 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);
979
980 // Now give it time to spin up.
981 // Signal field is on with the appropriate LED
982 LED_D_ON();
983 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
984 SpinDelay(200);
985
986 clear_trace();
987 set_tracing(true);
988
989 // First command: wake up the tag using the INITIATE command
990 uint8_t cmd1[] = {0x06, 0x00, 0x97, 0x5b};
991 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
992 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
993
994 if (Demod.len == 0) {
995 DbpString("No response from tag");
996 LED_D_OFF();
997 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
998 return;
999 } else {
1000 Dbprintf("Randomly generated Chip ID (+ 2 byte CRC): %02x %02x %02x",
1001 Demod.output[0], Demod.output[1], Demod.output[2]);
1002 }
1003
1004 // There is a response, SELECT the uid
1005 DbpString("Now SELECT tag:");
1006 cmd1[0] = 0x0E; // 0x0E is SELECT
1007 cmd1[1] = Demod.output[0];
1008 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1009 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1010 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
1011 if (Demod.len != 3) {
1012 Dbprintf("Expected 3 bytes from tag, got %d", Demod.len);
1013 LED_D_OFF();
1014 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1015 return;
1016 }
1017 // Check the CRC of the answer:
1018 ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]);
1019 if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) {
1020 DbpString("CRC Error reading select response.");
1021 LED_D_OFF();
1022 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1023 return;
1024 }
1025 // Check response from the tag: should be the same UID as the command we just sent:
1026 if (cmd1[1] != Demod.output[0]) {
1027 Dbprintf("Bad response to SELECT from Tag, aborting: %02x %02x", cmd1[1], Demod.output[0]);
1028 LED_D_OFF();
1029 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1030 return;
1031 }
1032
1033 // Tag is now selected,
1034 // First get the tag's UID:
1035 cmd1[0] = 0x0B;
1036 ComputeCrc14443(CRC_14443_B, cmd1, 1 , &cmd1[1], &cmd1[2]);
1037 CodeAndTransmit14443bAsReader(cmd1, 3); // Only first three bytes for this one
1038 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
1039 if (Demod.len != 10) {
1040 Dbprintf("Expected 10 bytes from tag, got %d", Demod.len);
1041 LED_D_OFF();
1042 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1043 return;
1044 }
1045 // The check the CRC of the answer (use cmd1 as temporary variable):
1046 ComputeCrc14443(CRC_14443_B, Demod.output, 8, &cmd1[2], &cmd1[3]);
1047 if(cmd1[2] != Demod.output[8] || cmd1[3] != Demod.output[9]) {
1048 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1049 (cmd1[2]<<8)+cmd1[3], (Demod.output[8]<<8)+Demod.output[9]);
1050 // Do not return;, let's go on... (we should retry, maybe ?)
1051 }
1052 Dbprintf("Tag UID (64 bits): %08x %08x",
1053 (Demod.output[7]<<24) + (Demod.output[6]<<16) + (Demod.output[5]<<8) + Demod.output[4],
1054 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0]);
1055
1056 // Now loop to read all 16 blocks, address from 0 to last block
1057 Dbprintf("Tag memory dump, block 0 to %d", dwLast);
1058 cmd1[0] = 0x08;
1059 i = 0x00;
1060 dwLast++;
1061 for (;;) {
1062 if (i == dwLast) {
1063 DbpString("System area block (0xff):");
1064 i = 0xff;
1065 }
1066 cmd1[1] = i;
1067 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1068 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1069 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
1070 if (Demod.len != 6) { // Check if we got an answer from the tag
1071 DbpString("Expected 6 bytes from tag, got less...");
1072 LED_D_OFF();
1073 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1074 return;
1075 }
1076 // The check the CRC of the answer (use cmd1 as temporary variable):
1077 ComputeCrc14443(CRC_14443_B, Demod.output, 4, &cmd1[2], &cmd1[3]);
1078 if(cmd1[2] != Demod.output[4] || cmd1[3] != Demod.output[5]) {
1079 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1080 (cmd1[2]<<8)+cmd1[3], (Demod.output[4]<<8)+Demod.output[5]);
1081 // Do not return;, let's go on... (we should retry, maybe ?)
1082 }
1083 // Now print out the memory location:
1084 Dbprintf("Address=%02x, Contents=%08x, CRC=%04x", i,
1085 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0],
1086 (Demod.output[4]<<8)+Demod.output[5]);
1087 if (i == 0xff) {
1088 break;
1089 }
1090 i++;
1091 }
1092
1093 LED_D_OFF();
1094 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1095 }
1096
1097
1098 //=============================================================================
1099 // Finally, the `sniffer' combines elements from both the reader and
1100 // simulated tag, to show both sides of the conversation.
1101 //=============================================================================
1102
1103 //-----------------------------------------------------------------------------
1104 // Record the sequence of commands sent by the reader to the tag, with
1105 // triggering so that we start recording at the point that the tag is moved
1106 // near the reader.
1107 //-----------------------------------------------------------------------------
1108 /*
1109 * Memory usage for this function, (within BigBuf)
1110 * Last Received command (reader->tag) - MAX_FRAME_SIZE
1111 * Last Received command (tag->reader) - MAX_FRAME_SIZE
1112 * DMA Buffer - ISO14443B_DMA_BUFFER_SIZE
1113 * Demodulated samples received - all the rest
1114 */
1115 void RAMFUNC SnoopIso14443b(void)
1116 {
1117 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1118 BigBuf_free();
1119
1120 clear_trace();
1121 set_tracing(true);
1122
1123 // The DMA buffer, used to stream samples from the FPGA
1124 uint16_t *dmaBuf = (uint16_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE * sizeof(uint16_t));
1125 int lastRxCounter;
1126 uint16_t *upTo;
1127 int8_t ci, cq;
1128 int maxBehindBy = 0;
1129
1130 // Count of samples received so far, so that we can include timing
1131 // information in the trace buffer.
1132 int samples = 0;
1133
1134 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1135 UartInit(BigBuf_malloc(MAX_FRAME_SIZE));
1136
1137 // Print some debug information about the buffer sizes
1138 Dbprintf("Snooping buffers initialized:");
1139 Dbprintf(" Trace: %i bytes", BigBuf_max_traceLen());
1140 Dbprintf(" Reader -> tag: %i bytes", MAX_FRAME_SIZE);
1141 Dbprintf(" tag -> Reader: %i bytes", MAX_FRAME_SIZE);
1142 Dbprintf(" DMA: %i bytes", ISO14443B_DMA_BUFFER_SIZE);
1143
1144 // Signal field is off, no reader signal, no tag signal
1145 LEDsoff();
1146
1147 // And put the FPGA in the appropriate mode
1148 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP);
1149 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1150
1151 // Setup for the DMA.
1152 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);
1153 upTo = dmaBuf;
1154 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
1155 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
1156 uint8_t parity[MAX_PARITY_SIZE];
1157
1158 bool TagIsActive = false;
1159 bool ReaderIsActive = false;
1160 // We won't start recording the frames that we acquire until we trigger.
1161 // A good trigger condition to get started is probably when we see a
1162 // reader command
1163 bool triggered = false;
1164
1165 // And now we loop, receiving samples.
1166 for(;;) {
1167 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO14443B_DMA_BUFFER_SIZE-1);
1168 if(behindBy > maxBehindBy) {
1169 maxBehindBy = behindBy;
1170 }
1171
1172 if(behindBy < 1) continue;
1173
1174 ci = *upTo>>8;
1175 cq = *upTo;
1176 upTo++;
1177 lastRxCounter--;
1178 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) { // we have read all of the DMA buffer content.
1179 upTo = dmaBuf; // start reading the circular buffer from the beginning again
1180 lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
1181 if(behindBy > (9*ISO14443B_DMA_BUFFER_SIZE/10)) {
1182 Dbprintf("About to blow circular buffer - aborted! behindBy=%d", behindBy);
1183 break;
1184 }
1185 }
1186 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_ENDRX)) { // DMA Counter Register had reached 0, already rotated.
1187 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf; // refresh the DMA Next Buffer and
1188 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE; // DMA Next Counter registers
1189 WDT_HIT();
1190 if(BUTTON_PRESS()) {
1191 DbpString("cancelled");
1192 break;
1193 }
1194 }
1195
1196 samples++;
1197
1198 if (!TagIsActive) { // no need to try decoding reader data if the tag is sending
1199 if(Handle14443bUartBit(ci & 0x01)) {
1200 triggered = true;
1201 if(tracing) {
1202 LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, true);
1203 }
1204 /* And ready to receive another command. */
1205 UartReset();
1206 /* And also reset the demod code, which might have been */
1207 /* false-triggered by the commands from the reader. */
1208 DemodReset();
1209 }
1210 if(Handle14443bUartBit(cq & 0x01)) {
1211 triggered = true;
1212 if(tracing) {
1213 LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, true);
1214 }
1215 /* And ready to receive another command. */
1216 UartReset();
1217 /* And also reset the demod code, which might have been */
1218 /* false-triggered by the commands from the reader. */
1219 DemodReset();
1220 }
1221 ReaderIsActive = (Uart.state > STATE_GOT_FALLING_EDGE_OF_SOF);
1222 }
1223
1224 if(!ReaderIsActive && triggered) { // no need to try decoding tag data if the reader is sending or not yet triggered
1225 if(Handle14443bSamplesDemod(ci/2, cq/2)) {
1226
1227 //Use samples as a time measurement
1228 if(tracing)
1229 {
1230 uint8_t parity[MAX_PARITY_SIZE];
1231 LogTrace(Demod.output, Demod.len, samples, samples, parity, false);
1232 }
1233 // And ready to receive another response.
1234 DemodReset();
1235 }
1236 TagIsActive = (Demod.state > DEMOD_GOT_FALLING_EDGE_OF_SOF);
1237 }
1238
1239 }
1240
1241 FpgaDisableSscDma();
1242 LEDsoff();
1243 DbpString("Snoop statistics:");
1244 Dbprintf(" Max behind by: %i", maxBehindBy);
1245 Dbprintf(" Uart State: %x", Uart.state);
1246 Dbprintf(" Uart ByteCnt: %i", Uart.byteCnt);
1247 Dbprintf(" Uart ByteCntMax: %i", Uart.byteCntMax);
1248 Dbprintf(" Trace length: %i", BigBuf_get_traceLen());
1249 }
1250
1251
1252 /*
1253 * Send raw command to tag ISO14443B
1254 * @Input
1255 * datalen len of buffer data
1256 * recv bool when true wait for data from tag and send to client
1257 * powerfield bool leave the field on when true
1258 * data buffer with byte to send
1259 *
1260 * @Output
1261 * none
1262 *
1263 */
1264 void SendRawCommand14443B(uint32_t datalen, uint32_t recv, uint8_t powerfield, uint8_t data[])
1265 {
1266 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1267 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1268
1269 // switch field on and give tag some time to power up
1270 LED_D_ON();
1271 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_TX);
1272 SpinDelay(10);
1273
1274 if (datalen){
1275 set_tracing(true);
1276
1277 CodeAndTransmit14443bAsReader(data, datalen);
1278
1279 if(recv) {
1280 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
1281 uint16_t iLen = MIN(Demod.len, USB_CMD_DATA_SIZE);
1282 cmd_send(CMD_ACK, iLen, 0, 0, Demod.output, iLen);
1283 }
1284 }
1285
1286 if(!powerfield) {
1287 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1288 LED_D_OFF();
1289 }
1290 }
1291
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