cvs.zerfleddert.de Git - proxmark3-svn/blob - armsrc/ticks.c

   1 //-----------------------------------------------------------------------------
   2 // Jonathan Westhues, Sept 2005
   3 // Iceman, Sept 2016
   4 //
   5 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
   6 // at your option, any later version. See the LICENSE.txt file for the text of
   7 // the license.
   8 //-----------------------------------------------------------------------------
   9 // Timers, Clocks functions used in LF or Legic where you would need detailed time.
  10 //-----------------------------------------------------------------------------
  11 #include "ticks.h"
  12 // attempt at high resolution microsecond timer
  13 // beware: timer counts in 21.3uS increments (1024/48Mhz)
  14 void SpinDelayUs(int us) {
  15         int ticks = (48 * us) >> 10;
  16
  17         // Borrow a PWM unit for my real-time clock
  18         AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
  19
  20         // 48 MHz / 1024 gives 46.875 kHz
  21         AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
  22         AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
  23         AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
  24
  25         uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
  26
  27         for(;;) {
  28                 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
  29                 if (now == (uint16_t)(start + ticks))
  30                         return;
  31
  32                 WDT_HIT();
  33         }
  34 }
  35
  36 void SpinDelay(int ms) {
  37   // convert to uS and call microsecond delay function
  38         SpinDelayUs(ms*1000);
  39 }
  40 //  -------------------------------------------------------------------------
  41 //  timer lib
  42 //  -------------------------------------------------------------------------
  43 //  test procedure:
  44 //
  45 //      ti = GetTickCount();
  46 //      SpinDelay(1000);
  47 //      ti = GetTickCount() - ti;
  48 //      Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
  49 void StartTickCount(void) {
  50         // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
  51         // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
  52     uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff;         // = 16 * main clock frequency (16MHz) / slow clock frequency
  53         // set RealTimeCounter divider to count at 1kHz:
  54         AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf);
  55         // note: worst case precision is approx 2.5%
  56 }
  57
  58 /*
  59 * Get the current count.
  60 */
  61 uint32_t RAMFUNC GetTickCount(void){
  62         return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
  63 }
  64
  65 //  -------------------------------------------------------------------------
  66 //  microseconds timer
  67 //  -------------------------------------------------------------------------
  68 void StartCountUS(void) {
  69         AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1);
  70         AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
  71
  72         // fast clock
  73         // tick=1.5mks
  74         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
  75         AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32
  76                                                                 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
  77                                                                 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
  78         AT91C_BASE_TC0->TC_RA = 1;
  79         AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
  80
  81         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable
  82         AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
  83
  84         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
  85         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
  86         AT91C_BASE_TCB->TCB_BCR = 1;
  87
  88         while (AT91C_BASE_TC1->TC_CV > 0);
  89 }
  90
  91 uint32_t RAMFUNC GetCountUS(void){
  92         //return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
  93         //  By suggestion from PwPiwi, http://www.proxmark.org/forum/viewtopic.php?pid=17548#p17548
  94         return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3);
  95 }
  96
  97 //  -------------------------------------------------------------------------
  98 //  Timer for iso14443 commands. Uses ssp_clk from FPGA
  99 //  -------------------------------------------------------------------------
 100 void StartCountSspClk(void) {
 101         AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers
 102         AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1               // XC0 Clock = TIOA1
 103                                                         | AT91C_TCB_TC1XC1S_NONE                // XC1 Clock = none
 104                                                         | AT91C_TCB_TC2XC2S_TIOA0;              // XC2 Clock = TIOA0
 105
 106         // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
 107         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC1
 108         AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
 109                                                         | AT91C_TC_CPCSTOP                              // Stop clock on RC compare
 110                                                         | AT91C_TC_EEVTEDG_RISING               // Trigger on rising edge of Event
 111                                                         | AT91C_TC_EEVT_TIOB                    // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
 112                                                         | AT91C_TC_ENETRG                               // Enable external trigger event
 113                                                         | AT91C_TC_WAVESEL_UP                   // Upmode without automatic trigger on RC compare
 114                                                         | AT91C_TC_WAVE                                 // Waveform Mode
 115                                                         | AT91C_TC_AEEVT_SET                    // Set TIOA1 on external event
 116                                                         | AT91C_TC_ACPC_CLEAR;                  // Clear TIOA1 on RC Compare
 117         AT91C_BASE_TC1->TC_RC = 0x04;                                                   // RC Compare value = 0x04
 118
 119         // use TC0 to count TIOA1 pulses
 120         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC0
 121         AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0                              // TC0 clock = XC0 clock = TIOA1
 122                                                         | AT91C_TC_WAVE                                 // Waveform Mode
 123                                                         | AT91C_TC_WAVESEL_UP                   // just count
 124                                                         | AT91C_TC_ACPA_CLEAR                   // Clear TIOA0 on RA Compare
 125                                                         | AT91C_TC_ACPC_SET;                    // Set TIOA0 on RC Compare
 126         AT91C_BASE_TC0->TC_RA = 1;                                                              // RA Compare value = 1; pulse width to TC2
 127         AT91C_BASE_TC0->TC_RC = 0;                                                              // RC Compare value = 0; increment TC2 on overflow
 128
 129         // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
 130         AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC2
 131         AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2                              // TC2 clock = XC2 clock = TIOA0
 132                                                         | AT91C_TC_WAVE                                 // Waveform Mode
 133                                                         | AT91C_TC_WAVESEL_UP;                  // just count
 134
 135         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;                               // enable and reset TC0
 136         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;                               // enable and reset TC1
 137         AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;                               // enable and reset TC2
 138
 139         // synchronize the counter with the ssp_frame signal.
 140         // Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present
 141         while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
 142         while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);              // wait for ssp_frame to be low
 143         while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK));     // wait for ssp_clk to go high
 144
 145         // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
 146         // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
 147         AT91C_BASE_TCB->TCB_BCR = 1;                                                    // assert Sync (set all timers to 0 on next active clock edge)
 148         // at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
 149         // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
 150         // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
 151         // (just started with the transfer of the 4th Bit).
 152
 153         // The high word of the counter (TC2) will not reset until the low word (TC0) overflows.
 154         // Therefore need to wait quite some time before we can use the counter.
 155         while (AT91C_BASE_TC2->TC_CV > 0);
 156 }
 157 void ResetSspClk(void) {
 158         //enable clock of timer and software trigger
 159         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 160         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 161         AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 162         while (AT91C_BASE_TC2->TC_CV > 0);
 163 }
 164 uint32_t RAMFUNC GetCountSspClk(void) {
 165         uint32_t tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
 166         if ((tmp_count & 0x0000ffff) == 0)  //small chance that we may have missed an increment in TC2
 167                 return (AT91C_BASE_TC2->TC_CV << 16);
 168         return tmp_count;
 169 }
 170
 171 //  -------------------------------------------------------------------------
 172 //  Timer for bitbanging,  or LF stuff when you need a very precis timer
 173 //  1us = 1.5ticks
 174 //  -------------------------------------------------------------------------
 175 void StartTicks(void){
 176         //initialization of the timer
 177         // tc1 is higher 0xFFFF0000
 178         // tc0 is lower 0x0000FFFF
 179         AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1);
 180         AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
 181         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
 182         AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32
 183                                                                 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
 184                                                                 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
 185         AT91C_BASE_TC0->TC_RA = 1;
 186         AT91C_BASE_TC0->TC_RC = 0;
 187
 188         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;       // timer disable
 189         AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from TC0
 190
 191         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 192         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 193         AT91C_BASE_TCB->TCB_BCR = 1;
 194
 195         // wait until timer becomes zero.
 196         while (AT91C_BASE_TC1->TC_CV > 0);
 197 }
 198 // Wait - Spindelay in ticks.
 199 // if called with a high number, this will trigger the WDT...
 200 void WaitTicks(uint32_t ticks){
 201         if ( ticks == 0 ) return;
 202         ticks += GET_TICKS;
 203         while (GET_TICKS < ticks);
 204 }
 205 // Wait / Spindelay in us (microseconds)
 206 // 1us = 1.5ticks.
 207 void WaitUS(uint16_t us){
 208         if ( us == 0 ) return;
 209         WaitTicks(  (uint32_t)(us * 1.5) );
 210 }
 211 void WaitMS(uint16_t ms){
 212         if (ms == 0) return;
 213         WaitTicks( (uint32_t)(ms * 1500) );
 214 }
 215 // Starts Clock and waits until its reset
 216 void ResetTicks(void){
 217         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 218         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 219         while (AT91C_BASE_TC1->TC_CV > 0);
 220 }
 221 void ResetTimer(AT91PS_TC timer){
 222         timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 223         while(timer->TC_CV > 0) ;
 224 }
 225 // stop clock
 226 void StopTicks(void){
 227         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
 228         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
 229 }