]> cvs.zerfleddert.de Git - proxmark3-svn/blob - fpga/testbed_lo_read.v
Added a new function to read ISO14443-B ST Microelectronics SRI512 memory tags.
[proxmark3-svn] / fpga / testbed_lo_read.v
1 `include "lo_read_org.v"
2 `include "lo_read.v"
3 /*
4 pck0 - input main 24Mhz clock (PLL / 4)
5 [7:0] adc_d - input data from A/D converter
6 lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)
7
8 pwr_lo - output to coil drivers (ssp_clk / 8)
9 adc_clk - output A/D clock signal
10 ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
11 ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
12 ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
13
14 ck_1356meg - input unused
15 ck_1356megb - input unused
16 ssp_dout - input unused
17 cross_hi - input unused
18 cross_lo - input unused
19
20 pwr_hi - output unused, tied low
21 pwr_oe1 - output unused, undefined
22 pwr_oe2 - output unused, undefined
23 pwr_oe3 - output unused, undefined
24 pwr_oe4 - output unused, undefined
25 dbg - output alias for adc_clk
26 */
27
28 module testbed_lo_read;
29 reg pck0;
30 reg [7:0] adc_d;
31 reg lo_is_125khz;
32 reg [15:0] divisor;
33
34 wire pwr_lo;
35 wire adc_clk;
36 wire ck_1356meg;
37 wire ck_1356megb;
38 wire ssp_frame;
39 wire ssp_din;
40 wire ssp_clk;
41 wire ssp_dout;
42 wire pwr_hi;
43 wire pwr_oe1;
44 wire pwr_oe2;
45 wire pwr_oe3;
46 wire pwr_oe4;
47 wire cross_lo;
48 wire cross_hi;
49 wire dbg;
50
51 lo_read_org #(5,10) dut1(
52 .pck0(pck0),
53 .ck_1356meg(ack_1356meg),
54 .ck_1356megb(ack_1356megb),
55 .pwr_lo(apwr_lo),
56 .pwr_hi(apwr_hi),
57 .pwr_oe1(apwr_oe1),
58 .pwr_oe2(apwr_oe2),
59 .pwr_oe3(apwr_oe3),
60 .pwr_oe4(apwr_oe4),
61 .adc_d(adc_d),
62 .adc_clk(adc_clk),
63 .ssp_frame(assp_frame),
64 .ssp_din(assp_din),
65 .ssp_dout(assp_dout),
66 .ssp_clk(assp_clk),
67 .cross_hi(across_hi),
68 .cross_lo(across_lo),
69 .dbg(adbg),
70 .lo_is_125khz(lo_is_125khz)
71 );
72
73 lo_read #(5,10) dut2(
74 .pck0(pck0),
75 .ck_1356meg(bck_1356meg),
76 .ck_1356megb(bck_1356megb),
77 .pwr_lo(bpwr_lo),
78 .pwr_hi(bpwr_hi),
79 .pwr_oe1(bpwr_oe1),
80 .pwr_oe2(bpwr_oe2),
81 .pwr_oe3(bpwr_oe3),
82 .pwr_oe4(bpwr_oe4),
83 .adc_d(adc_d),
84 .adc_clk(badc_clk),
85 .ssp_frame(bssp_frame),
86 .ssp_din(bssp_din),
87 .ssp_dout(bssp_dout),
88 .ssp_clk(bssp_clk),
89 .cross_hi(bcross_hi),
90 .cross_lo(bcross_lo),
91 .dbg(bdbg),
92 .lo_is_125khz(lo_is_125khz),
93 .divisor(divisor)
94 );
95
96 integer idx, i, adc_val=8;
97
98 // main clock
99 always #5 pck0 = !pck0;
100
101 task crank_dut;
102 begin
103 @(posedge adc_clk) ;
104 adc_d = adc_val;
105 adc_val = (adc_val *2) + 53;
106 end
107 endtask
108
109 initial begin
110
111 // init inputs
112 pck0 = 0;
113 adc_d = 0;
114 lo_is_125khz = 1;
115 divisor=255; //min 19, 95=125Khz, max 255
116
117 // simulate 4 A/D cycles at 125Khz
118 for (i = 0 ; i < 8 ; i = i + 1) begin
119 crank_dut;
120 end
121 $finish;
122 end
123 endmodule // main
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