cvs.zerfleddert.de Git - proxmark3-svn/blob - fpga/hi_read_rx_xcorr.v

   1 //-----------------------------------------------------------------------------
   2 //
   3 // Jonathan Westhues, April 2006
   4 //-----------------------------------------------------------------------------
   5
   6 module hi_read_rx_xcorr(
   7     pck0, ck_1356meg, ck_1356megb,
   8     pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
   9     adc_d, adc_clk,
  10     ssp_frame, ssp_din, ssp_dout, ssp_clk,
  11     cross_hi, cross_lo,
  12     dbg,
  13     xcorr_is_848, snoop, xcorr_quarter_freq
  14 );
  15     input pck0, ck_1356meg, ck_1356megb;
  16     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
  17     input [7:0] adc_d;
  18     output adc_clk;
  19     input ssp_dout;
  20     output ssp_frame, ssp_din, ssp_clk;
  21     input cross_hi, cross_lo;
  22     output dbg;
  23     input xcorr_is_848, snoop, xcorr_quarter_freq;
  24
  25 // Carrier is steady on through this, unless we're snooping.
  26 assign pwr_hi = ck_1356megb & (~snoop);
  27 assign pwr_oe1 = 1'b0;
  28 assign pwr_oe3 = 1'b0;
  29 assign pwr_oe4 = 1'b0;
  30
  31 reg [2:0] fc_div;
  32 always @(negedge ck_1356megb)
  33     fc_div <= fc_div + 1;
  34
  35 (* clock_signal = "yes" *) reg adc_clk;                         // sample frequency, always 16 * fc
  36 always @(ck_1356megb, xcorr_is_848, xcorr_quarter_freq, fc_div)
  37         if (xcorr_is_848 & ~xcorr_quarter_freq)                 // fc = 847.5 kHz
  38                 adc_clk <= ck_1356megb;
  39         else if (~xcorr_is_848 & ~xcorr_quarter_freq)   // fc = 424.25 kHz
  40                 adc_clk <= fc_div[0];
  41         else if (xcorr_is_848 & xcorr_quarter_freq)             // fc = 212.125 kHz
  42                 adc_clk <= fc_div[1];
  43         else                                                                                    // fc = 106.0625 kHz
  44                 adc_clk <= fc_div[2];
  45
  46 // When we're a reader, we just need to do the BPSK demod; but when we're an
  47 // eavesdropper, we also need to pick out the commands sent by the reader,
  48 // using AM. Do this the same way that we do it for the simulated tag.
  49 reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev;
  50 reg [11:0] has_been_low_for;
  51 always @(negedge adc_clk)
  52 begin
  53     if(& adc_d[7:0]) after_hysteresis <= 1'b1;
  54     else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
  55
  56     if(after_hysteresis)
  57     begin
  58         has_been_low_for <= 7'b0;
  59     end
  60     else
  61     begin
  62         if(has_been_low_for == 12'd4095)
  63         begin
  64             has_been_low_for <= 12'd0;
  65             after_hysteresis <= 1'b1;
  66         end
  67         else
  68             has_been_low_for <= has_been_low_for + 1;
  69     end
  70 end
  71
  72 // Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,
  73 // so we need a 6-bit counter.
  74 reg [5:0] corr_i_cnt;
  75 // And a couple of registers in which to accumulate the correlations.
  76 // we would add/sub at most 32 times adc_d, the signed result can be held in 14 bits.
  77 reg signed [13:0] corr_i_accum;
  78 reg signed [13:0] corr_q_accum;
  79 reg signed [7:0] corr_i_out;
  80 reg signed [7:0] corr_q_out;
  81 // clock and frame signal for communication to ARM
  82 reg ssp_clk;
  83 reg ssp_frame;
  84
  85
  86 always @(negedge adc_clk)
  87 begin
  88         corr_i_cnt <= corr_i_cnt + 1;
  89 end
  90
  91
  92 // ADC data appears on the rising edge, so sample it on the falling edge
  93 always @(negedge adc_clk)
  94 begin
  95     // These are the correlators: we correlate against in-phase and quadrature
  96     // versions of our reference signal, and keep the (signed) result to
  97     // send out later over the SSP.
  98     if(corr_i_cnt == 6'd0)
  99     begin
 100         if(snoop)
 101         begin
 102                         // Send only 7 most significant bits of tag signal (signed), LSB is reader signal:
 103             corr_i_out <= {corr_i_accum[13:7], after_hysteresis_prev_prev};
 104             corr_q_out <= {corr_q_accum[13:7], after_hysteresis_prev};
 105                         after_hysteresis_prev_prev <= after_hysteresis;
 106         end
 107         else
 108         begin
 109             // 8 most significant bits of tag signal
 110             corr_i_out <= corr_i_accum[13:6];
 111             corr_q_out <= corr_q_accum[13:6];
 112         end
 113
 114         corr_i_accum <= adc_d;
 115         corr_q_accum <= adc_d;
 116     end
 117     else
 118     begin
 119         if(corr_i_cnt[3])
 120             corr_i_accum <= corr_i_accum - adc_d;
 121         else
 122             corr_i_accum <= corr_i_accum + adc_d;
 123
 124         if(corr_i_cnt[3] == corr_i_cnt[2])                      // phase shifted by pi/2
 125             corr_q_accum <= corr_q_accum + adc_d;
 126         else
 127             corr_q_accum <= corr_q_accum - adc_d;
 128
 129     end
 130
 131     // The logic in hi_simulate.v reports 4 samples per bit. We report two
 132     // (I, Q) pairs per bit, so we should do 2 samples per pair.
 133     if(corr_i_cnt == 6'd32)
 134         after_hysteresis_prev <= after_hysteresis;
 135
 136     // Then the result from last time is serialized and send out to the ARM.
 137     // We get one report each cycle, and each report is 16 bits, so the
 138     // ssp_clk should be the adc_clk divided by 64/16 = 4.
 139
 140     if(corr_i_cnt[1:0] == 2'b10)
 141         ssp_clk <= 1'b0;
 142
 143     if(corr_i_cnt[1:0] == 2'b00)
 144     begin
 145         ssp_clk <= 1'b1;
 146         // Don't shift if we just loaded new data, obviously.
 147         if(corr_i_cnt != 6'd0)
 148         begin
 149             corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
 150             corr_q_out[7:1] <= corr_q_out[6:0];
 151         end
 152     end
 153
 154         // set ssp_frame signal for corr_i_cnt = 0..3 and corr_i_cnt = 32..35
 155         // (send two frames with 8 Bits each)
 156     if(corr_i_cnt[5:2] == 4'b0000 || corr_i_cnt[5:2] == 4'b1000)
 157         ssp_frame = 1'b1;
 158     else
 159         ssp_frame = 1'b0;
 160
 161 end
 162
 163 assign ssp_din = corr_i_out[7];
 164
 165 assign dbg = corr_i_cnt[3];
 166
 167 // Unused.
 168 assign pwr_lo = 1'b0;
 169 assign pwr_oe2 = 1'b0;
 170
 171 endmodule