+`include "lo_read_org.v"\r
`include "lo_read.v"\r
-\r
/*\r
pck0 - input main 24Mhz clock (PLL / 4)\r
[7:0] adc_d - input data from A/D converter\r
reg pck0;\r
reg [7:0] adc_d;\r
reg lo_is_125khz;\r
+ reg [15:0] divisor;\r
\r
wire pwr_lo;\r
wire adc_clk;\r
wire cross_hi;\r
wire dbg;\r
\r
- lo_read #(5,200) dut(\r
+ lo_read_org #(5,10) dut1(\r
.pck0(pck0),\r
- .ck_1356meg(ck_1356meg),\r
- .ck_1356megb(ck_1356megb),\r
- .pwr_lo(pwr_lo),\r
- .pwr_hi(pwr_hi),\r
- .pwr_oe1(pwr_oe1),\r
- .pwr_oe2(pwr_oe2),\r
- .pwr_oe3(pwr_oe3),\r
- .pwr_oe4(pwr_oe4),\r
+ .ck_1356meg(ack_1356meg),\r
+ .ck_1356megb(ack_1356megb),\r
+ .pwr_lo(apwr_lo),\r
+ .pwr_hi(apwr_hi),\r
+ .pwr_oe1(apwr_oe1),\r
+ .pwr_oe2(apwr_oe2),\r
+ .pwr_oe3(apwr_oe3),\r
+ .pwr_oe4(apwr_oe4),\r
.adc_d(adc_d),\r
.adc_clk(adc_clk),\r
- .ssp_frame(ssp_frame),\r
- .ssp_din(ssp_din),\r
- .ssp_dout(ssp_dout),\r
- .ssp_clk(ssp_clk),\r
- .cross_hi(cross_hi),\r
- .cross_lo(cross_lo),\r
- .dbg(dbg),\r
+ .ssp_frame(assp_frame),\r
+ .ssp_din(assp_din),\r
+ .ssp_dout(assp_dout),\r
+ .ssp_clk(assp_clk),\r
+ .cross_hi(across_hi),\r
+ .cross_lo(across_lo),\r
+ .dbg(adbg),\r
.lo_is_125khz(lo_is_125khz)\r
);\r
\r
- integer idx, i;\r
+ lo_read #(5,10) dut2(\r
+ .pck0(pck0),\r
+ .ck_1356meg(bck_1356meg),\r
+ .ck_1356megb(bck_1356megb),\r
+ .pwr_lo(bpwr_lo),\r
+ .pwr_hi(bpwr_hi),\r
+ .pwr_oe1(bpwr_oe1),\r
+ .pwr_oe2(bpwr_oe2),\r
+ .pwr_oe3(bpwr_oe3),\r
+ .pwr_oe4(bpwr_oe4),\r
+ .adc_d(adc_d),\r
+ .adc_clk(badc_clk),\r
+ .ssp_frame(bssp_frame),\r
+ .ssp_din(bssp_din),\r
+ .ssp_dout(bssp_dout),\r
+ .ssp_clk(bssp_clk),\r
+ .cross_hi(bcross_hi),\r
+ .cross_lo(bcross_lo),\r
+ .dbg(bdbg),\r
+ .lo_is_125khz(lo_is_125khz),\r
+ .divisor(divisor)\r
+ );\r
+\r
+ integer idx, i, adc_val=8;\r
\r
// main clock\r
always #5 pck0 = !pck0;\r
\r
- //new A/D value available from ADC on positive edge\r
task crank_dut;\r
begin\r
@(posedge adc_clk) ;\r
- adc_d = $random;\r
+ adc_d = adc_val;\r
+ adc_val = (adc_val *2) + 53;\r
end\r
endtask\r
\r
// init inputs\r
pck0 = 0;\r
adc_d = 0;\r
-\r
- // simulate 4 A/D cycles at 134Khz\r
- lo_is_125khz=0;\r
- for (i = 0 ; i < 4 ; i = i + 1) begin\r
- crank_dut;\r
- end\r
+ lo_is_125khz = 1;\r
+ divisor=255; //min 19, 95=125Khz, max 255\r
\r
// simulate 4 A/D cycles at 125Khz\r
- lo_is_125khz=1;\r
- for (i = 0 ; i < 4 ; i = i + 1) begin\r
+ for (i = 0 ; i < 8 ; i = i + 1) begin\r
crank_dut;\r
end\r
$finish;\r
end\r
- \r
endmodule // main\r