revert removal of quarter frequency support for hi_read_rx_xcorr.v

diff --git a/armsrc/fpgaloader.h b/armsrc/fpgaloader.h
index 59c07ed89a5c391c5d8157d28df2f49dc9bc25f1..7dfc5c1265e539e8e8e419bb9ad68da857e6a061 100644 (file)
--- a/armsrc/fpgaloader.h
+++ b/armsrc/fpgaloader.h
@@ -58,6 +58,7 @@ void SetAdcMuxFor(uint32_t whichGpio);
 // Options for the HF reader, correlating against rx from tag
 #define FPGA_HF_READER_RX_XCORR_848_KHZ                                (1<<0)
 #define FPGA_HF_READER_RX_XCORR_SNOOP                          (1<<1)
 // Options for the HF reader, correlating against rx from tag
 #define FPGA_HF_READER_RX_XCORR_848_KHZ                                (1<<0)
 #define FPGA_HF_READER_RX_XCORR_SNOOP                          (1<<1)

+#define FPGA_HF_READER_RX_XCORR_QUARTER_FREQ           (1<<2)

 // Options for the HF simulated tag, how to modulate
 #define FPGA_HF_SIMULATOR_NO_MODULATION                                (0<<0)
 #define FPGA_HF_SIMULATOR_MODULATE_BPSK                                (1<<0)
 // Options for the HF simulated tag, how to modulate
 #define FPGA_HF_SIMULATOR_NO_MODULATION                                (0<<0)
 #define FPGA_HF_SIMULATOR_MODULATE_BPSK                                (1<<0)

diff --git a/fpga/fpga_hf.bit b/fpga/fpga_hf.bit
index 864b52394dcb821b24bb42ac9b8d6d01a34832f8..b9f2e6292e42801a73b57aa3e43dff00191ec8b9 100644 (file)
Binary files a/fpga/fpga_hf.bit and b/fpga/fpga_hf.bit differ

diff --git a/fpga/fpga_hf.v b/fpga/fpga_hf.v
index 264e1b0c61beea3dc1b3248f1b73293b5d41311f..f99a43dde9ea33360176d40ffe1803e280016805 100644 (file)
--- a/fpga/fpga_hf.v
+++ b/fpga/fpga_hf.v
@@ -73,6 +73,8 @@ wire hi_read_tx_shallow_modulation = conf_word[0];
 wire hi_read_rx_xcorr_848 = conf_word[0];
 // and whether to drive the coil (reader) or just short it (snooper)
 wire hi_read_rx_xcorr_snoop = conf_word[1];
 wire hi_read_rx_xcorr_848 = conf_word[0];
 // and whether to drive the coil (reader) or just short it (snooper)
 wire hi_read_rx_xcorr_snoop = conf_word[1];

+// divide subcarrier frequency by 4
+wire hi_read_rx_xcorr_quarter = conf_word[2];

 
 // For the high-frequency simulated tag: what kind of modulation to use.
 wire [2:0] hi_simulate_mod_type = conf_word[2:0];
 
 // For the high-frequency simulated tag: what kind of modulation to use.
 wire [2:0] hi_simulate_mod_type = conf_word[2:0];


@@ -100,7 +102,7 @@ hi_read_rx_xcorr hrxc(
        hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
        cross_hi, cross_lo,
        hrxc_dbg,
        hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
        cross_hi, cross_lo,
        hrxc_dbg,

-       hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop
+       hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter

 );
 
 hi_simulate hs(
 );
 
 hi_simulate hs(

diff --git a/fpga/hi_read_rx_xcorr.v b/fpga/hi_read_rx_xcorr.v
index 80e363275fd6ed6ab6f56c369e1b42827852022b..afa46c4437a2870f3065c03d4ed0cd7759f7ef4d 100644 (file)
--- a/fpga/hi_read_rx_xcorr.v
+++ b/fpga/hi_read_rx_xcorr.v
@@ -10,7 +10,7 @@ module hi_read_rx_xcorr(
     ssp_frame, ssp_din, ssp_dout, ssp_clk,
     cross_hi, cross_lo,
     dbg,
     ssp_frame, ssp_din, ssp_dout, ssp_clk,
     cross_hi, cross_lo,
     dbg,

-    xcorr_is_848, snoop
+    xcorr_is_848, snoop, xcorr_quarter_freq

 );
     input pck0, ck_1356meg, ck_1356megb;
     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
 );
     input pck0, ck_1356meg, ck_1356megb;
     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;


@@ -20,7 +20,7 @@ module hi_read_rx_xcorr(
     output ssp_frame, ssp_din, ssp_clk;
     input cross_hi, cross_lo;
     output dbg;
     output ssp_frame, ssp_din, ssp_clk;
     input cross_hi, cross_lo;
     output dbg;

-    input xcorr_is_848, snoop;
+    input xcorr_is_848, snoop, xcorr_quarter_freq;

 
 // Carrier is steady on through this, unless we're snooping.
 assign pwr_hi = ck_1356megb & (~snoop);
 
 // Carrier is steady on through this, unless we're snooping.
 assign pwr_hi = ck_1356megb & (~snoop);


@@ -28,19 +28,21 @@ assign pwr_oe1 = 1'b0;
 assign pwr_oe3 = 1'b0;
 assign pwr_oe4 = 1'b0;
 
 assign pwr_oe3 = 1'b0;
 assign pwr_oe4 = 1'b0;
 

-// Clock divider
-reg [0:0] fc_divider;
+reg [2:0] fc_div;

 always @(negedge ck_1356megb)
 always @(negedge ck_1356megb)

-    fc_divider <= fc_divider + 1;
-wire fc_div2 = fc_divider[0];
+    fc_div <= fc_div + 1;

 
 

-reg adc_clk;
-always @(ck_1356megb)
-       if (xcorr_is_848)
+(* clock_signal = "yes" *) reg adc_clk;                                // sample frequency, always 16 * fc
+always @(ck_1356megb, xcorr_is_848, xcorr_quarter_freq, fc_div)
+       if (xcorr_is_848 & ~xcorr_quarter_freq)                 // fc = 847.5 kHz

                adc_clk <= ck_1356megb;
                adc_clk <= ck_1356megb;

-       else
-               adc_clk <= fc_div2;
-
+       else if (~xcorr_is_848 & ~xcorr_quarter_freq)   // fc = 424.25 kHz 
+               adc_clk <= fc_div[0];
+       else if (xcorr_is_848 & xcorr_quarter_freq)             // fc = 212.125 kHz
+               adc_clk <= fc_div[1];
+       else                                                                                    // fc = 106.0625 kHz
+               adc_clk <= fc_div[2];
+               

 // When we're a reader, we just need to do the BPSK demod; but when we're an
 // eavesdropper, we also need to pick out the commands sent by the reader,
 // using AM. Do this the same way that we do it for the simulated tag.
 // When we're a reader, we just need to do the BPSK demod; but when we're an
 // eavesdropper, we also need to pick out the commands sent by the reader,
 // using AM. Do this the same way that we do it for the simulated tag.


@@ -71,8 +73,7 @@ end
 // so we need a 6-bit counter.
 reg [5:0] corr_i_cnt;
 // And a couple of registers in which to accumulate the correlations.
 // so we need a 6-bit counter.
 reg [5:0] corr_i_cnt;
 // And a couple of registers in which to accumulate the correlations.

-// we would add at most 32 times adc_d, the result can be held in 13 bits. 
-// Need one additional bit because it can be negative as well
+// we would add/sub at most 32 times adc_d, the signed result can be held in 14 bits. 

 reg signed [13:0] corr_i_accum;
 reg signed [13:0] corr_q_accum;
 reg signed [7:0] corr_i_out;
 reg signed [13:0] corr_i_accum;
 reg signed [13:0] corr_q_accum;
 reg signed [7:0] corr_i_out;


@@ -84,7 +85,7 @@ reg ssp_frame;
 
 always @(negedge adc_clk)
 begin
 
 always @(negedge adc_clk)
 begin

-               corr_i_cnt <= corr_i_cnt + 1;
+       corr_i_cnt <= corr_i_cnt + 1;

 end            
                
 
 end