+++ /dev/null
-;\r
-; Copyright Model Technology, a Mentor Graphics\r
-; Corporation company 2003, - All rights reserved.\r
-; \r
-[Library]\r
-std = $MODEL_TECH/../std\r
-ieee = $MODEL_TECH/../ieee\r
-verilog = $MODEL_TECH/../verilog\r
-vital2000 = $MODEL_TECH/../vital2000\r
-std_developerskit = $MODEL_TECH/../std_developerskit\r
-synopsys = $MODEL_TECH/../synopsys\r
-modelsim_lib = $MODEL_TECH/../modelsim_lib\r
-\r
-\r
-; VHDL Section\r
-unisim = $MODEL_TECH/../xilinx/vhdl/unisim\r
-simprim = $MODEL_TECH/../xilinx/vhdl/simprim\r
-xilinxcorelib = $MODEL_TECH/../xilinx/vhdl/xilinxcorelib\r
-aim = $MODEL_TECH/../xilinx/vhdl/aim\r
-pls = $MODEL_TECH/../xilinx/vhdl/pls\r
-cpld = $MODEL_TECH/../xilinx/vhdl/cpld\r
-\r
-; Verilog Section\r
-unisims_ver = $MODEL_TECH/../xilinx/verilog/unisims_ver\r
-uni9000_ver = $MODEL_TECH/../xilinx/verilog/uni9000_ver\r
-simprims_ver = $MODEL_TECH/../xilinx/verilog/simprims_ver\r
-xilinxcorelib_ver = $MODEL_TECH/../xilinx/verilog/xilinxcorelib_ver\r
-aim_ver = $MODEL_TECH/../xilinx/verilog/aim_ver\r
-cpld_ver = $MODEL_TECH/../xilinx/verilog/cpld_ver\r
-\r
-work = work
-[vcom]\r
-; Turn on VHDL-1993 as the default. Normally is off.\r
-VHDL93 = 1\r
-\r
-; Show source line containing error. Default is off.\r
-; Show_source = 1\r
-\r
-; Turn off unbound-component warnings. Default is on.\r
-; Show_Warning1 = 0\r
-\r
-; Turn off process-without-a-wait-statement warnings. Default is on.\r
-; Show_Warning2 = 0\r
-\r
-; Turn off null-range warnings. Default is on.\r
-; Show_Warning3 = 0\r
-\r
-; Turn off no-space-in-time-literal warnings. Default is on.\r
-; Show_Warning4 = 0\r
-\r
-; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.\r
-; Show_Warning5 = 0\r
-\r
-; Turn off optimization for IEEE std_logic_1164 package. Default is on.\r
-; Optimize_1164 = 0\r
-\r
-; Turn on resolving of ambiguous function overloading in favor of the\r
-; "explicit" function declaration (not the one automatically created by\r
-; the compiler for each type declaration). Default is off.\r
- Explicit = 1\r
-\r
-; Turn off VITAL compliance checking. Default is checking on.\r
-; NoVitalCheck = 1\r
-\r
-; Ignore VITAL compliance checking errors. Default is to not ignore.\r
-; IgnoreVitalErrors = 1\r
-\r
-; Turn off VITAL compliance checking warnings. Default is to show warnings.\r
-; Show_VitalChecksWarnings = false\r
-\r
-; Turn off "loading..." messages. Default is messages on.\r
-; Quiet = 1\r
-\r
-; Turn on some limited synthesis rule compliance checking. Checks only:\r
-; -- signals used (read) by a process must be in the sensitivity list\r
-; CheckSynthesis = 1\r
-\r
-[vlog]\r
-\r
-; Turn off "loading..." messages. Default is messages on.\r
-; Quiet = 1\r
-\r
-; Turn on Verilog hazard checking (order-dependent accessing of global vars).\r
-; Default is off.\r
-; Hazard = 1\r
-\r
-; Turn on converting regular Verilog identifiers to uppercase. Allows case\r
-; insensitivity for module names. Default is no conversion.\r
-; UpCase = 1\r
-\r
-; Turns on incremental compilation of modules \r
-; Incremental = 1\r
-\r
-[vsim]\r
-; Simulator resolution\r
-; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.\r
-Resolution = ps\r
-\r
-; User time unit for run commands\r
-; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the\r
-; unit specified for Resolution. For example, if Resolution is 100ps,\r
-; then UserTimeUnit defaults to ps.\r
-UserTimeUnit = default\r
-\r
-; Default run length\r
-RunLength = 100\r
-\r
-; Maximum iterations that can be run without advancing simulation time\r
-IterationLimit = 5000\r
-\r
-; Directive to license manager:\r
-; vhdl Immediately reserve a VHDL license\r
-; vlog Immediately reserve a Verilog license\r
-; plus Immediately reserve a VHDL and Verilog license\r
-; nomgc Do not look for Mentor Graphics Licenses\r
-; nomti Do not look for Model Technology Licenses\r
-; noqueue Do not wait in the license queue when a license isn't available\r
-; License = plus\r
-\r
-; Stop the simulator after an assertion message\r
-; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal\r
-BreakOnAssertion = 3\r
-\r
-; Assertion Message Format\r
-; %S - Severity Level \r
-; %R - Report Message\r
-; %T - Time of assertion\r
-; %D - Delta\r
-; %I - Instance or Region pathname (if available)\r
-; %% - print '%' character\r
-; AssertionFormat = "** %S: %R\n Timf: %T Iteration: %D%I\n"\r
-\r
-; Assertion File - alternate file for storing assertion messages\r
-; AssertFile = assert.log\r
-\r
-; Default radix for all windows and commands...\r
-; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned\r
-DefaultRadix = symbolic\r
-\r
-; VSIM Startup command\r
-; Startup = do startup.do\r
-\r
-; File for saving command transcript\r
-TranscriptFile = transcript\r
-\r
-; File for saving command history \r
-;CommandHistory = cmdhist.log\r
-\r
-; Specify whether paths in simulator commands should be described \r
-; in VHDL or Verilog format. For VHDL, PathSeparator = /\r
-; for Verilog, PathSeparator = .\r
-PathSeparator = /\r
-\r
-; Specify the dataset separator for fully rooted contexts.\r
-; The default is ':'. For example, sim:/top\r
-; Must not be the same character as PathSeparator.\r
-DatasetSeparator = :\r
-\r
-; Disable assertion messages\r
-; IgnoreNote = 1\r
-; IgnoreWarning = 1\r
-; IgnoreError = 1\r
-; IgnoreFailure = 1\r
-\r
-; Default force kind. May be freeze, drive, or deposit \r
-; or in other terms, fixed, wired or charged.\r
-; DefaultForceKind = freeze\r
-\r
-; If zero, open files when elaborated\r
-; else open files on first read or write\r
-; DelayFileOpen = 0\r
-\r
-; Control VHDL files opened for write\r
-; 0 = Buffered, 1 = Unbuffered\r
-UnbufferedOutput = 0\r
-\r
-; Control number of VHDL files open concurrently\r
-; This number should always be less then the \r
-; current ulimit setting for max file descriptors\r
-; 0 = unlimited\r
-ConcurrentFileLimit = 40\r
-\r
-; This controls the number of hierarchical regions displayed as\r
-; part of a signal name shown in the waveform window. The default\r
-; value or a value of zero tells VSIM to display the full name.\r
-; WaveSignalNameWidth = 0\r
-\r
-; Turn off warnings from the std_logic_arith, std_logic_unsigned\r
-; and std_logic_signed packages.\r
-; StdArithNoWarnings = 1\r
-\r
-; Turn off warnings from the IEEE numeric_std and numeric_bit\r
-; packages.\r
-; NumericStdNoWarnings = 1\r
-\r
-; Control the format of a generate statement label. Don't quote it.\r
-; GenerateFormat = %s__%d\r
-\r
-; Specify whether checkpoint files should be compressed.\r
-; The default is to be compressed.\r
-; CheckpointCompressMode = 0\r
-\r
-; List of dynamically loaded objects for Verilog PLI applications\r
-; Veriuser = veriuser.sl\r
-\r
-[lmc]\r
-[Project]
-Project_Version = 5
-Project_DefaultLib = work
-Project_SortMethod = unused
-Project_Files_Count = 13
-Project_File_0 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/fpga_tb.v
-Project_File_P_0 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1179836462 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 2 dont_compile 0
-Project_File_1 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/hi_simulate.v
-Project_File_P_1 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1225963633 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 6 dont_compile 0
-Project_File_2 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/testbed_hi_simulate.v
-Project_File_P_2 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1225964050 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 12 dont_compile 0
-Project_File_3 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/fpga.v
-Project_File_P_3 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1207888760 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 1 dont_compile 0
-Project_File_4 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/hi_read_tx.v
-Project_File_P_4 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1225960972 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 5 dont_compile 0
-Project_File_5 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/testbed_hi_read_tx.v
-Project_File_P_5 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1225962515 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 11 dont_compile 0
-Project_File_6 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/hi_iso14443a.v
-Project_File_P_6 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1207889732 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 3 dont_compile 0
-Project_File_7 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/lo_simulate.v
-Project_File_P_7 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1179836462 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 8 dont_compile 0
-Project_File_8 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/lo_read.v
-Project_File_P_8 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1225797126 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 7 dont_compile 0
-Project_File_9 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/util.v
-Project_File_P_9 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1179836462 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 0 dont_compile 0
-Project_File_10 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/testbed_lo_read.v
-Project_File_P_10 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1225960239 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 9 dont_compile 0
-Project_File_11 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/testbed_lo_simulate.v
-Project_File_P_11 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1225960231 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 10 dont_compile 0
-Project_File_12 = G:/RFID/Hardware/Proxmark3/Sources/prox_work/fpga/hi_read_rx_xcorr.v
-Project_File_P_12 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1179836462 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 4 dont_compile 0
-Project_Sim_Count = 0
-Project_Folder_Count = 0
projects / proxmark3-svn / commitdiff