void LCDSend(unsigned int data)\r
{\r
// 9th bit set for data, clear for command\r
- while ((SPI_STATUS & SPI_STATUS_TX_EMPTY) == 0); // wait for the transfer to complete\r
+ while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete\r
// For clarity's sake we pass data with 9th bit clear and commands with 9th\r
// bit set since they're implemented as defines, se we need to invert bit\r
- SPI_TX_DATA = data^0x100; // Send the data/command\r
+ AT91C_BASE_SPI->SPI_TDR = data^0x100; // Send the data/command\r
}\r
\r
void LCDSetXY(unsigned char x, unsigned char y)\r
{\r
LED_A_ON();\r
SetupSpi(SPI_LCD_MODE);\r
- LCD_RESET_LOW();\r
+ LOW(GPIO_LRST);\r
SpinDelay(100);\r
\r
- LCD_RESET_HIGH();\r
+ HIGH(GPIO_LRST);\r
SpinDelay(100);\r
LED_A_OFF();\r
}\r
#ifndef __LCD\r
#define __LCD\r
\r
-#define LCD_RESET_HIGH() PIO_OUTPUT_DATA_SET |= (1<<GPIO_LRST)\r
-#define LCD_RESET_LOW() PIO_OUTPUT_DATA_CLEAR |= (1<<GPIO_LRST)\r
-\r
// The resolution of the LCD\r
#define LCD_XRES 132\r
#define LCD_YRES 132\r
-//-----------------------------------------------------------------------------
-// The main application code. This is the first thing called after start.c
-// executes.
-// Jonathan Westhues, Mar 2006
-// Edits by Gerhard de Koning Gans, Sep 2007 (##)
-//-----------------------------------------------------------------------------
-
-#include <proxmark3.h>
-#include <stdlib.h>
-#include "apps.h"
-#ifdef WITH_LCD
-#include "fonts.h"
-#include "LCD.h"
-#endif
-
-//=============================================================================
-// A buffer where we can queue things up to be sent through the FPGA, for
-// any purpose (fake tag, as reader, whatever). We go MSB first, since that
-// is the order in which they go out on the wire.
-//=============================================================================
-
-BYTE ToSend[256];
-int ToSendMax;
-static int ToSendBit;
-struct common_area common_area __attribute__((section(".commonarea")));
-
-void BufferClear(void)
-{
- memset(BigBuf,0,sizeof(BigBuf));
- DbpString("Buffer cleared");
-}
-
-void ToSendReset(void)
-{
- ToSendMax = -1;
- ToSendBit = 8;
-}
-
-void ToSendStuffBit(int b)
-{
- if(ToSendBit >= 8) {
- ToSendMax++;
- ToSend[ToSendMax] = 0;
- ToSendBit = 0;
- }
-
- if(b) {
- ToSend[ToSendMax] |= (1 << (7 - ToSendBit));
- }
-
- ToSendBit++;
-
- if(ToSendBit >= sizeof(ToSend)) {
- ToSendBit = 0;
- DbpString("ToSendStuffBit overflowed!");
- }
-}
-
-//=============================================================================
-// Debug print functions, to go out over USB, to the usual PC-side client.
-//=============================================================================
-
-void DbpString(char *str)
-{
- /* this holds up stuff unless we're connected to usb */
- if (!UsbConnected())
- return;
-
- UsbCommand c;
- c.cmd = CMD_DEBUG_PRINT_STRING;
- c.ext1 = strlen(str);
- memcpy(c.d.asBytes, str, c.ext1);
-
- UsbSendPacket((BYTE *)&c, sizeof(c));
- // TODO fix USB so stupid things like this aren't req'd
- SpinDelay(50);
-}
-
-void DbpIntegers(int x1, int x2, int x3)
-{
- /* this holds up stuff unless we're connected to usb */
- if (!UsbConnected())
- return;
-
- UsbCommand c;
- c.cmd = CMD_DEBUG_PRINT_INTEGERS;
- c.ext1 = x1;
- c.ext2 = x2;
- c.ext3 = x3;
-
- UsbSendPacket((BYTE *)&c, sizeof(c));
- // XXX
- SpinDelay(50);
-}
-
-//-----------------------------------------------------------------------------
-// Read an ADC channel and block till it completes, then return the result
-// in ADC units (0 to 1023). Also a routine to average 32 samples and
-// return that.
-//-----------------------------------------------------------------------------
-static int ReadAdc(int ch)
-{
- DWORD d;
-
- ADC_CONTROL = ADC_CONTROL_RESET;
- ADC_MODE = ADC_MODE_PRESCALE(32) | ADC_MODE_STARTUP_TIME(16) |
- ADC_MODE_SAMPLE_HOLD_TIME(8);
- ADC_CHANNEL_ENABLE = ADC_CHANNEL(ch);
-
- ADC_CONTROL = ADC_CONTROL_START;
- while(!(ADC_STATUS & ADC_END_OF_CONVERSION(ch)))
- ;
- d = ADC_CHANNEL_DATA(ch);
-
- return d;
-}
-
-static int AvgAdc(int ch)
-{
- int i;
- int a = 0;
-
- for(i = 0; i < 32; i++) {
- a += ReadAdc(ch);
- }
-
- return (a + 15) >> 5;
-}
-
-void MeasureAntennaTuning(void)
-{
- BYTE *dest = (BYTE *)BigBuf;
- int i, ptr = 0, adcval = 0, peak = 0, peakv = 0, peakf = 0;;
- int vLf125 = 0, vLf134 = 0, vHf = 0; // in mV
-
- UsbCommand c;
-
- DbpString("Measuring antenna characteristics, please wait.");
- memset(BigBuf,0,sizeof(BigBuf));
-
-/*
- * Sweeps the useful LF range of the proxmark from
- * 46.8kHz (divisor=255) to 600kHz (divisor=19) and
- * read the voltage in the antenna, the result left
- * in the buffer is a graph which should clearly show
- * the resonating frequency of your LF antenna
- * ( hopefully around 95 if it is tuned to 125kHz!)
- */
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
- for (i=255; i>19; i--) {
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, i);
- SpinDelay(20);
- // Vref = 3.3V, and a 10000:240 voltage divider on the input
- // can measure voltages up to 137500 mV
- adcval = ((137500 * AvgAdc(ADC_CHAN_LF)) >> 10);
- if (i==95) vLf125 = adcval; // voltage at 125Khz
- if (i==89) vLf134 = adcval; // voltage at 134Khz
-
- dest[i] = adcval>>8; // scale int to fit in byte for graphing purposes
- if(dest[i] > peak) {
- peakv = adcval;
- peak = dest[i];
- peakf = i;
- ptr = i;
- }
- }
-
- // Let the FPGA drive the high-frequency antenna around 13.56 MHz.
- FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);
- SpinDelay(20);
- // Vref = 3300mV, and an 10:1 voltage divider on the input
- // can measure voltages up to 33000 mV
- vHf = (33000 * AvgAdc(ADC_CHAN_HF)) >> 10;
-
- c.cmd = CMD_MEASURED_ANTENNA_TUNING;
- c.ext1 = (vLf125 << 0) | (vLf134 << 16);
- c.ext2 = vHf;
- c.ext3 = peakf | (peakv << 16);
- UsbSendPacket((BYTE *)&c, sizeof(c));
-}
-
-void SimulateTagHfListen(void)
-{
- BYTE *dest = (BYTE *)BigBuf;
- int n = sizeof(BigBuf);
- BYTE v = 0;
- int i;
- int p = 0;
-
- // We're using this mode just so that I can test it out; the simulated
- // tag mode would work just as well and be simpler.
- FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP);
-
- // We need to listen to the high-frequency, peak-detected path.
- SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
-
- FpgaSetupSsc();
-
- i = 0;
- for(;;) {
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {
- SSC_TRANSMIT_HOLDING = 0xff;
- }
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {
- BYTE r = (BYTE)SSC_RECEIVE_HOLDING;
-
- v <<= 1;
- if(r & 1) {
- v |= 1;
- }
- p++;
-
- if(p >= 8) {
- dest[i] = v;
- v = 0;
- p = 0;
- i++;
-
- if(i >= n) {
- break;
- }
- }
- }
- }
- DbpString("simulate tag (now type bitsamples)");
-}
-
-void ReadMem(int addr)
-{
- const DWORD *data = ((DWORD *)addr);
- int i;
-
- DbpString("Reading memory at address");
- DbpIntegers(0, 0, addr);
- for (i = 0; i < 8; i+= 2)
- DbpIntegers(0, data[i], data[i+1]);
-}
-
-/* osimage version information is linked in */
-extern struct version_information version_information;
-/* bootrom version information is pointed to from _bootphase1_version_pointer */
-extern char *_bootphase1_version_pointer, _flash_start, _flash_end;
-void SendVersion(void)
-{
- char temp[48]; /* Limited data payload in USB packets */
- DbpString("Prox/RFID mark3 RFID instrument");
-
- /* Try to find the bootrom version information. Expect to find a pointer at
- * symbol _bootphase1_version_pointer, perform slight sanity checks on the
- * pointer, then use it.
- */
- char *bootrom_version = *(char**)&_bootphase1_version_pointer;
- if( bootrom_version < &_flash_start || bootrom_version >= &_flash_end ) {
- DbpString("bootrom version information appears invalid");
- } else {
- FormatVersionInformation(temp, sizeof(temp), "bootrom: ", bootrom_version);
- DbpString(temp);
- }
-
- FormatVersionInformation(temp, sizeof(temp), "os: ", &version_information);
- DbpString(temp);
-
- FpgaGatherVersion(temp, sizeof(temp));
- DbpString(temp);
-}
-
-// samy's sniff and repeat routine
-void SamyRun()
-{
- DbpString("Stand-alone mode! No PC necessary.");
-
- // 3 possible options? no just 2 for now
-#define OPTS 2
-
- int high[OPTS], low[OPTS];
-
- // Oooh pretty -- notify user we're in elite samy mode now
- LED(LED_RED, 200);
- LED(LED_ORANGE, 200);
- LED(LED_GREEN, 200);
- LED(LED_ORANGE, 200);
- LED(LED_RED, 200);
- LED(LED_ORANGE, 200);
- LED(LED_GREEN, 200);
- LED(LED_ORANGE, 200);
- LED(LED_RED, 200);
-
- int selected = 0;
- int playing = 0;
-
- // Turn on selected LED
- LED(selected + 1, 0);
-
- for (;;)
- {
- UsbPoll(FALSE);
- WDT_HIT();
-
- // Was our button held down or pressed?
- int button_pressed = BUTTON_HELD(1000);
- SpinDelay(300);
-
- // Button was held for a second, begin recording
- if (button_pressed > 0)
- {
- LEDsoff();
- LED(selected + 1, 0);
- LED(LED_RED2, 0);
-
- // record
- DbpString("Starting recording");
-
- // wait for button to be released
- while(BUTTON_PRESS())
- WDT_HIT();
-
- /* need this delay to prevent catching some weird data */
- SpinDelay(500);
-
- CmdHIDdemodFSK(1, &high[selected], &low[selected], 0);
- DbpString("Recorded");
- DbpIntegers(selected, high[selected], low[selected]);
-
- LEDsoff();
- LED(selected + 1, 0);
- // Finished recording
-
- // If we were previously playing, set playing off
- // so next button push begins playing what we recorded
- playing = 0;
- }
-
- // Change where to record (or begin playing)
- else if (button_pressed)
- {
- // Next option if we were previously playing
- if (playing)
- selected = (selected + 1) % OPTS;
- playing = !playing;
-
- LEDsoff();
- LED(selected + 1, 0);
-
- // Begin transmitting
- if (playing)
- {
- LED(LED_GREEN, 0);
- DbpString("Playing");
- // wait for button to be released
- while(BUTTON_PRESS())
- WDT_HIT();
- DbpIntegers(selected, high[selected], low[selected]);
- CmdHIDsimTAG(high[selected], low[selected], 0);
- DbpString("Done playing");
- if (BUTTON_HELD(1000) > 0)
- {
- DbpString("Exiting");
- LEDsoff();
- return;
- }
-
- /* We pressed a button so ignore it here with a delay */
- SpinDelay(300);
-
- // when done, we're done playing, move to next option
- selected = (selected + 1) % OPTS;
- playing = !playing;
- LEDsoff();
- LED(selected + 1, 0);
- }
- else
- while(BUTTON_PRESS())
- WDT_HIT();
- }
- }
-}
-
-
-/*
-OBJECTIVE
-Listen and detect an external reader. Determine the best location
-for the antenna.
-
-INSTRUCTIONS:
-Inside the ListenReaderField() function, there is two mode.
-By default, when you call the function, you will enter mode 1.
-If you press the PM3 button one time, you will enter mode 2.
-If you press the PM3 button a second time, you will exit the function.
-
-DESCRIPTION OF MODE 1:
-This mode just listens for an external reader field and lights up green
-for HF and/or red for LF. This is the original mode of the detectreader
-function.
-
-DESCRIPTION OF MODE 2:
-This mode will visually represent, using the LEDs, the actual strength of the
-current compared to the maximum current detected. Basically, once you know
-what kind of external reader is present, it will help you spot the best location to place
-your antenna. You will probably not get some good results if there is a LF and a HF reader
-at the same place! :-)
-
-LIGHT SCHEME USED:
-*/
-static const char LIGHT_SCHEME[] = {
- 0x0, /* ---- | No field detected */
- 0x1, /* X--- | 14% of maximum current detected */
- 0x2, /* -X-- | 29% of maximum current detected */
- 0x4, /* --X- | 43% of maximum current detected */
- 0x8, /* ---X | 57% of maximum current detected */
- 0xC, /* --XX | 71% of maximum current detected */
- 0xE, /* -XXX | 86% of maximum current detected */
- 0xF, /* XXXX | 100% of maximum current detected */
-};
-static const int LIGHT_LEN = sizeof(LIGHT_SCHEME)/sizeof(LIGHT_SCHEME[0]);
-
-void ListenReaderField(int limit)
-{
- int lf_av, lf_av_new, lf_baseline= 0, lf_count= 0, lf_max;
- int hf_av, hf_av_new, hf_baseline= 0, hf_count= 0, hf_max;
- int mode=1, display_val, display_max, i;
-
-#define LF_ONLY 1
-#define HF_ONLY 2
-
- LEDsoff();
-
- lf_av=lf_max=ReadAdc(ADC_CHAN_LF);
-
- if(limit != HF_ONLY) {
- DbpString("LF 125/134 Baseline:");
- DbpIntegers(lf_av,0,0);
- lf_baseline= lf_av;
- }
-
- hf_av=hf_max=ReadAdc(ADC_CHAN_HF);
-
- if (limit != LF_ONLY) {
- DbpString("HF 13.56 Baseline:");
- DbpIntegers(hf_av,0,0);
- hf_baseline= hf_av;
- }
-
- for(;;) {
- if (BUTTON_PRESS()) {
- SpinDelay(500);
- switch (mode) {
- case 1:
- mode=2;
- DbpString("Signal Strength Mode");
- break;
- case 2:
- default:
- DbpString("Stopped");
- LEDsoff();
- return;
- break;
- }
- }
- WDT_HIT();
-
- if (limit != HF_ONLY) {
- if(mode==1) {
- if (abs(lf_av - lf_baseline) > 10) LED_D_ON();
- else LED_D_OFF();
- }
-
- ++lf_count;
- lf_av_new= ReadAdc(ADC_CHAN_LF);
- // see if there's a significant change
- if(abs(lf_av - lf_av_new) > 10) {
- DbpString("LF 125/134 Field Change:");
- DbpIntegers(lf_av,lf_av_new,lf_count);
- lf_av= lf_av_new;
- if (lf_av > lf_max)
- lf_max = lf_av;
- lf_count= 0;
- }
- }
-
- if (limit != LF_ONLY) {
- if (mode == 1){
- if (abs(hf_av - hf_baseline) > 10) LED_B_ON();
- else LED_B_OFF();
- }
-
- ++hf_count;
- hf_av_new= ReadAdc(ADC_CHAN_HF);
- // see if there's a significant change
- if(abs(hf_av - hf_av_new) > 10) {
- DbpString("HF 13.56 Field Change:");
- DbpIntegers(hf_av,hf_av_new,hf_count);
- hf_av= hf_av_new;
- if (hf_av > hf_max)
- hf_max = hf_av;
- hf_count= 0;
- }
- }
-
- if(mode == 2) {
- if (limit == LF_ONLY) {
- display_val = lf_av;
- display_max = lf_max;
- } else if (limit == HF_ONLY) {
- display_val = hf_av;
- display_max = hf_max;
- } else { /* Pick one at random */
- if( (hf_max - hf_baseline) > (lf_max - lf_baseline) ) {
- display_val = hf_av;
- display_max = hf_max;
- } else {
- display_val = lf_av;
- display_max = lf_max;
- }
- }
- for (i=0; i<LIGHT_LEN; i++) {
- if (display_val >= ((display_max/LIGHT_LEN)*i) && display_val <= ((display_max/LIGHT_LEN)*(i+1))) {
- if (LIGHT_SCHEME[i] & 0x1) LED_C_ON(); else LED_C_OFF();
- if (LIGHT_SCHEME[i] & 0x2) LED_A_ON(); else LED_A_OFF();
- if (LIGHT_SCHEME[i] & 0x4) LED_B_ON(); else LED_B_OFF();
- if (LIGHT_SCHEME[i] & 0x8) LED_D_ON(); else LED_D_OFF();
- break;
- }
- }
- }
- }
-}
-
-void UsbPacketReceived(BYTE *packet, int len)
-{
- UsbCommand *c = (UsbCommand *)packet;
-
- switch(c->cmd) {
- case CMD_ACQUIRE_RAW_ADC_SAMPLES_125K:
- AcquireRawAdcSamples125k(c->ext1);
- break;
-
- case CMD_MOD_THEN_ACQUIRE_RAW_ADC_SAMPLES_125K:
- ModThenAcquireRawAdcSamples125k(c->ext1,c->ext2,c->ext3,c->d.asBytes);
- break;
-
- case CMD_ACQUIRE_RAW_ADC_SAMPLES_ISO_15693:
- AcquireRawAdcSamplesIso15693();
- break;
-
- case CMD_BUFF_CLEAR:
- BufferClear();
- break;
-
- case CMD_READER_ISO_15693:
- ReaderIso15693(c->ext1);
- break;
-
- case CMD_SIMTAG_ISO_15693:
- SimTagIso15693(c->ext1);
- break;
-
- case CMD_ACQUIRE_RAW_ADC_SAMPLES_ISO_14443:
- AcquireRawAdcSamplesIso14443(c->ext1);
- break;
-
- case CMD_READ_SRI512_TAG:
- ReadSRI512Iso14443(c->ext1);
- break;
-
- case CMD_READER_ISO_14443a:
- ReaderIso14443a(c->ext1);
- break;
-
- case CMD_SNOOP_ISO_14443:
- SnoopIso14443();
- break;
-
- case CMD_SNOOP_ISO_14443a:
- SnoopIso14443a();
- break;
-
- case CMD_SIMULATE_TAG_HF_LISTEN:
- SimulateTagHfListen();
- break;
-
- case CMD_SIMULATE_TAG_ISO_14443:
- SimulateIso14443Tag();
- break;
-
- case CMD_SIMULATE_TAG_ISO_14443a:
- SimulateIso14443aTag(c->ext1, c->ext2); // ## Simulate iso14443a tag - pass tag type & UID
- break;
-
- case CMD_MEASURE_ANTENNA_TUNING:
- MeasureAntennaTuning();
- break;
-
- case CMD_LISTEN_READER_FIELD:
- ListenReaderField(c->ext1);
- break;
-
- case CMD_HID_DEMOD_FSK:
- CmdHIDdemodFSK(0, 0, 0, 1); // Demodulate HID tag
- break;
-
- case CMD_HID_SIM_TAG:
- CmdHIDsimTAG(c->ext1, c->ext2, 1); // Simulate HID tag by ID
- break;
-
- case CMD_FPGA_MAJOR_MODE_OFF: // ## FPGA Control
- FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
- SpinDelay(200);
- LED_D_OFF(); // LED D indicates field ON or OFF
- break;
-
- case CMD_READ_TI_TYPE:
- ReadTItag();
- break;
-
- case CMD_WRITE_TI_TYPE:
- WriteTItag(c->ext1,c->ext2,c->ext3);
- break;
-
- case CMD_DOWNLOAD_RAW_ADC_SAMPLES_125K: {
- UsbCommand n;
- if(c->cmd == CMD_DOWNLOAD_RAW_ADC_SAMPLES_125K) {
- n.cmd = CMD_DOWNLOADED_RAW_ADC_SAMPLES_125K;
- } else {
- n.cmd = CMD_DOWNLOADED_RAW_BITS_TI_TYPE;
- }
- n.ext1 = c->ext1;
- memcpy(n.d.asDwords, BigBuf+c->ext1, 12*sizeof(DWORD));
- UsbSendPacket((BYTE *)&n, sizeof(n));
- break;
- }
- case CMD_DOWNLOADED_SIM_SAMPLES_125K: {
- BYTE *b = (BYTE *)BigBuf;
- memcpy(b+c->ext1, c->d.asBytes, 48);
- break;
- }
- case CMD_SIMULATE_TAG_125K:
- LED_A_ON();
- SimulateTagLowFrequency(c->ext1, 1);
- LED_A_OFF();
- break;
- case CMD_READ_MEM:
- ReadMem(c->ext1);
- break;
- case CMD_SET_LF_DIVISOR:
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, c->ext1);
- break;
- case CMD_VERSION:
- SendVersion();
- break;
- case CMD_LF_SIMULATE_BIDIR:
- SimulateTagLowFrequencyBidir(c->ext1, c->ext2);
- break;
-#ifdef WITH_LCD
- case CMD_LCD_RESET:
- LCDReset();
- break;
- case CMD_LCD:
- LCDSend(c->ext1);
- break;
-#endif
- case CMD_SETUP_WRITE:
- case CMD_FINISH_WRITE:
- case CMD_HARDWARE_RESET:
- USB_D_PLUS_PULLUP_OFF();
- SpinDelay(1000);
- SpinDelay(1000);
- RSTC_CONTROL = RST_CONTROL_KEY | RST_CONTROL_PROCESSOR_RESET;
- for(;;) {
- // We're going to reset, and the bootrom will take control.
- }
- break;
- case CMD_START_FLASH:
- if(common_area.flags.bootrom_present) {
- common_area.command = COMMON_AREA_COMMAND_ENTER_FLASH_MODE;
- }
- USB_D_PLUS_PULLUP_OFF();
- RSTC_CONTROL = RST_CONTROL_KEY | RST_CONTROL_PROCESSOR_RESET;
- for(;;);
- break;
-
- case CMD_DEVICE_INFO: {
- UsbCommand c;
- c.cmd = CMD_DEVICE_INFO;
- c.ext1 = DEVICE_INFO_FLAG_OSIMAGE_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_OS;
- if(common_area.flags.bootrom_present) c.ext1 |= DEVICE_INFO_FLAG_BOOTROM_PRESENT;
- UsbSendPacket((BYTE*)&c, sizeof(c));
- }
- break;
- default:
- DbpString("unknown command");
- break;
- }
-}
-
-void __attribute__((noreturn)) AppMain(void)
-{
- SpinDelay(100);
-
- if(common_area.magic != COMMON_AREA_MAGIC || common_area.version != 1) {
- /* Initialize common area */
- memset(&common_area, 0, sizeof(common_area));
- common_area.magic = COMMON_AREA_MAGIC;
- common_area.version = 1;
- }
- common_area.flags.osimage_present = 1;
-
- LED_D_OFF();
- LED_C_OFF();
- LED_B_OFF();
- LED_A_OFF();
-
- UsbStart();
-
- // The FPGA gets its clock from us from PCK0 output, so set that up.
- PIO_PERIPHERAL_B_SEL = (1 << GPIO_PCK0);
- PIO_DISABLE = (1 << GPIO_PCK0);
- PMC_SYS_CLK_ENABLE = PMC_SYS_CLK_PROGRAMMABLE_CLK_0;
- // PCK0 is PLL clock / 4 = 96Mhz / 4 = 24Mhz
- PMC_PROGRAMMABLE_CLK_0 = PMC_CLK_SELECTION_PLL_CLOCK |
- PMC_CLK_PRESCALE_DIV_4;
- PIO_OUTPUT_ENABLE = (1 << GPIO_PCK0);
-
- // Reset SPI
- SPI_CONTROL = SPI_CONTROL_RESET;
- // Reset SSC
- SSC_CONTROL = SSC_CONTROL_RESET;
-
- // Load the FPGA image, which we have stored in our flash.
- FpgaDownloadAndGo();
-
-#ifdef WITH_LCD
-
- LCDInit();
-
- // test text on different colored backgrounds
- LCDString(" The quick brown fox ", (char *)&FONT6x8,1,1+8*0,WHITE ,BLACK );
- LCDString(" jumped over the ", (char *)&FONT6x8,1,1+8*1,BLACK ,WHITE );
- LCDString(" lazy dog. ", (char *)&FONT6x8,1,1+8*2,YELLOW ,RED );
- LCDString(" AaBbCcDdEeFfGgHhIiJj ", (char *)&FONT6x8,1,1+8*3,RED ,GREEN );
- LCDString(" KkLlMmNnOoPpQqRrSsTt ", (char *)&FONT6x8,1,1+8*4,MAGENTA,BLUE );
- LCDString("UuVvWwXxYyZz0123456789", (char *)&FONT6x8,1,1+8*5,BLUE ,YELLOW);
- LCDString("`-=[]_;',./~!@#$%^&*()", (char *)&FONT6x8,1,1+8*6,BLACK ,CYAN );
- LCDString(" _+{}|:\\\"<>? ",(char *)&FONT6x8,1,1+8*7,BLUE ,MAGENTA);
-
- // color bands
- LCDFill(0, 1+8* 8, 132, 8, BLACK);
- LCDFill(0, 1+8* 9, 132, 8, WHITE);
- LCDFill(0, 1+8*10, 132, 8, RED);
- LCDFill(0, 1+8*11, 132, 8, GREEN);
- LCDFill(0, 1+8*12, 132, 8, BLUE);
- LCDFill(0, 1+8*13, 132, 8, YELLOW);
- LCDFill(0, 1+8*14, 132, 8, CYAN);
- LCDFill(0, 1+8*15, 132, 8, MAGENTA);
-
-#endif
-
- for(;;) {
- UsbPoll(FALSE);
- WDT_HIT();
-
- if (BUTTON_HELD(1000) > 0)
- SamyRun();
- }
-}
+//-----------------------------------------------------------------------------\r
+// The main application code. This is the first thing called after start.c\r
+// executes.\r
+// Jonathan Westhues, Mar 2006\r
+// Edits by Gerhard de Koning Gans, Sep 2007 (##)\r
+//-----------------------------------------------------------------------------\r
+\r
+#include <proxmark3.h>\r
+#include <stdlib.h>\r
+#include "apps.h"\r
+#ifdef WITH_LCD\r
+#include "fonts.h"\r
+#include "LCD.h"\r
+#endif\r
+\r
+//=============================================================================\r
+// A buffer where we can queue things up to be sent through the FPGA, for\r
+// any purpose (fake tag, as reader, whatever). We go MSB first, since that\r
+// is the order in which they go out on the wire.\r
+//=============================================================================\r
+\r
+BYTE ToSend[256];\r
+int ToSendMax;\r
+static int ToSendBit;\r
+struct common_area common_area __attribute__((section(".commonarea")));\r
+\r
+void BufferClear(void)\r
+{\r
+ memset(BigBuf,0,sizeof(BigBuf));\r
+ DbpString("Buffer cleared");\r
+}\r
+\r
+void ToSendReset(void)\r
+{\r
+ ToSendMax = -1;\r
+ ToSendBit = 8;\r
+}\r
+\r
+void ToSendStuffBit(int b)\r
+{\r
+ if(ToSendBit >= 8) {\r
+ ToSendMax++;\r
+ ToSend[ToSendMax] = 0;\r
+ ToSendBit = 0;\r
+ }\r
+\r
+ if(b) {\r
+ ToSend[ToSendMax] |= (1 << (7 - ToSendBit));\r
+ }\r
+\r
+ ToSendBit++;\r
+\r
+ if(ToSendBit >= sizeof(ToSend)) {\r
+ ToSendBit = 0;\r
+ DbpString("ToSendStuffBit overflowed!");\r
+ }\r
+}\r
+\r
+//=============================================================================\r
+// Debug print functions, to go out over USB, to the usual PC-side client.\r
+//=============================================================================\r
+\r
+void DbpString(char *str)\r
+{\r
+ /* this holds up stuff unless we're connected to usb */\r
+ if (!UsbConnected())\r
+ return;\r
+\r
+ UsbCommand c;\r
+ c.cmd = CMD_DEBUG_PRINT_STRING;\r
+ c.ext1 = strlen(str);\r
+ memcpy(c.d.asBytes, str, c.ext1);\r
+\r
+ UsbSendPacket((BYTE *)&c, sizeof(c));\r
+ // TODO fix USB so stupid things like this aren't req'd\r
+ SpinDelay(50);\r
+}\r
+\r
+void DbpIntegers(int x1, int x2, int x3)\r
+{\r
+ /* this holds up stuff unless we're connected to usb */\r
+ if (!UsbConnected())\r
+ return;\r
+\r
+ UsbCommand c;\r
+ c.cmd = CMD_DEBUG_PRINT_INTEGERS;\r
+ c.ext1 = x1;\r
+ c.ext2 = x2;\r
+ c.ext3 = x3;\r
+\r
+ UsbSendPacket((BYTE *)&c, sizeof(c));\r
+ // XXX\r
+ SpinDelay(50);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Read an ADC channel and block till it completes, then return the result\r
+// in ADC units (0 to 1023). Also a routine to average 32 samples and\r
+// return that.\r
+//-----------------------------------------------------------------------------\r
+static int ReadAdc(int ch)\r
+{\r
+ DWORD d;\r
+\r
+ AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;\r
+ AT91C_BASE_ADC->ADC_MR =\r
+ ADC_MODE_PRESCALE(32) |\r
+ ADC_MODE_STARTUP_TIME(16) |\r
+ ADC_MODE_SAMPLE_HOLD_TIME(8);\r
+ AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ch);\r
+\r
+ AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;\r
+ while(!(AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ch)))\r
+ ;\r
+ d = AT91C_BASE_ADC->ADC_CDR[ch];\r
+\r
+ return d;\r
+}\r
+\r
+static int AvgAdc(int ch)\r
+{\r
+ int i;\r
+ int a = 0;\r
+\r
+ for(i = 0; i < 32; i++) {\r
+ a += ReadAdc(ch);\r
+ }\r
+\r
+ return (a + 15) >> 5;\r
+}\r
+\r
+void MeasureAntennaTuning(void)\r
+{\r
+ BYTE *dest = (BYTE *)BigBuf;\r
+ int i, ptr = 0, adcval = 0, peak = 0, peakv = 0, peakf = 0;;\r
+ int vLf125 = 0, vLf134 = 0, vHf = 0; // in mV\r
+\r
+ UsbCommand c;\r
+\r
+ DbpString("Measuring antenna characteristics, please wait.");\r
+ memset(BigBuf,0,sizeof(BigBuf));\r
+\r
+/*\r
+ * Sweeps the useful LF range of the proxmark from\r
+ * 46.8kHz (divisor=255) to 600kHz (divisor=19) and\r
+ * read the voltage in the antenna, the result left\r
+ * in the buffer is a graph which should clearly show\r
+ * the resonating frequency of your LF antenna\r
+ * ( hopefully around 95 if it is tuned to 125kHz!)\r
+ */\r
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
+ for (i=255; i>19; i--) {\r
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, i);\r
+ SpinDelay(20);\r
+ // Vref = 3.3V, and a 10000:240 voltage divider on the input\r
+ // can measure voltages up to 137500 mV\r
+ adcval = ((137500 * AvgAdc(ADC_CHAN_LF)) >> 10);\r
+ if (i==95) vLf125 = adcval; // voltage at 125Khz\r
+ if (i==89) vLf134 = adcval; // voltage at 134Khz\r
+\r
+ dest[i] = adcval>>8; // scale int to fit in byte for graphing purposes\r
+ if(dest[i] > peak) {\r
+ peakv = adcval;\r
+ peak = dest[i];\r
+ peakf = i;\r
+ ptr = i;\r
+ }\r
+ }\r
+\r
+ // Let the FPGA drive the high-frequency antenna around 13.56 MHz.\r
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);\r
+ SpinDelay(20);\r
+ // Vref = 3300mV, and an 10:1 voltage divider on the input\r
+ // can measure voltages up to 33000 mV\r
+ vHf = (33000 * AvgAdc(ADC_CHAN_HF)) >> 10;\r
+\r
+ c.cmd = CMD_MEASURED_ANTENNA_TUNING;\r
+ c.ext1 = (vLf125 << 0) | (vLf134 << 16);\r
+ c.ext2 = vHf;\r
+ c.ext3 = peakf | (peakv << 16);\r
+ UsbSendPacket((BYTE *)&c, sizeof(c));\r
+}\r
+\r
+void SimulateTagHfListen(void)\r
+{\r
+ BYTE *dest = (BYTE *)BigBuf;\r
+ int n = sizeof(BigBuf);\r
+ BYTE v = 0;\r
+ int i;\r
+ int p = 0;\r
+\r
+ // We're using this mode just so that I can test it out; the simulated\r
+ // tag mode would work just as well and be simpler.\r
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP);\r
+\r
+ // We need to listen to the high-frequency, peak-detected path.\r
+ SetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r
+\r
+ FpgaSetupSsc();\r
+\r
+ i = 0;\r
+ for(;;) {\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = 0xff;\r
+ }\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+ BYTE r = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
+\r
+ v <<= 1;\r
+ if(r & 1) {\r
+ v |= 1;\r
+ }\r
+ p++;\r
+\r
+ if(p >= 8) {\r
+ dest[i] = v;\r
+ v = 0;\r
+ p = 0;\r
+ i++;\r
+\r
+ if(i >= n) {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ DbpString("simulate tag (now type bitsamples)");\r
+}\r
+\r
+void ReadMem(int addr)\r
+{\r
+ const DWORD *data = ((DWORD *)addr);\r
+ int i;\r
+\r
+ DbpString("Reading memory at address");\r
+ DbpIntegers(0, 0, addr);\r
+ for (i = 0; i < 8; i+= 2)\r
+ DbpIntegers(0, data[i], data[i+1]);\r
+}\r
+\r
+/* osimage version information is linked in */\r
+extern struct version_information version_information;\r
+/* bootrom version information is pointed to from _bootphase1_version_pointer */\r
+extern char *_bootphase1_version_pointer, _flash_start, _flash_end;\r
+void SendVersion(void)\r
+{\r
+ char temp[48]; /* Limited data payload in USB packets */\r
+ DbpString("Prox/RFID mark3 RFID instrument");\r
+ \r
+ /* Try to find the bootrom version information. Expect to find a pointer at \r
+ * symbol _bootphase1_version_pointer, perform slight sanity checks on the\r
+ * pointer, then use it.\r
+ */\r
+ char *bootrom_version = *(char**)&_bootphase1_version_pointer;\r
+ if( bootrom_version < &_flash_start || bootrom_version >= &_flash_end ) {\r
+ DbpString("bootrom version information appears invalid");\r
+ } else {\r
+ FormatVersionInformation(temp, sizeof(temp), "bootrom: ", bootrom_version);\r
+ DbpString(temp);\r
+ }\r
+ \r
+ FormatVersionInformation(temp, sizeof(temp), "os: ", &version_information);\r
+ DbpString(temp);\r
+ \r
+ FpgaGatherVersion(temp, sizeof(temp));\r
+ DbpString(temp);\r
+}\r
+\r
+// samy's sniff and repeat routine\r
+void SamyRun()\r
+{\r
+ DbpString("Stand-alone mode! No PC necessary.");\r
+\r
+ // 3 possible options? no just 2 for now\r
+#define OPTS 2\r
+\r
+ int high[OPTS], low[OPTS];\r
+\r
+ // Oooh pretty -- notify user we're in elite samy mode now\r
+ LED(LED_RED, 200);\r
+ LED(LED_ORANGE, 200);\r
+ LED(LED_GREEN, 200);\r
+ LED(LED_ORANGE, 200);\r
+ LED(LED_RED, 200);\r
+ LED(LED_ORANGE, 200);\r
+ LED(LED_GREEN, 200);\r
+ LED(LED_ORANGE, 200);\r
+ LED(LED_RED, 200);\r
+\r
+ int selected = 0;\r
+ int playing = 0;\r
+\r
+ // Turn on selected LED\r
+ LED(selected + 1, 0);\r
+\r
+ for (;;)\r
+ {\r
+ UsbPoll(FALSE);\r
+ WDT_HIT();\r
+\r
+ // Was our button held down or pressed?\r
+ int button_pressed = BUTTON_HELD(1000);\r
+ SpinDelay(300);\r
+\r
+ // Button was held for a second, begin recording\r
+ if (button_pressed > 0)\r
+ {\r
+ LEDsoff();\r
+ LED(selected + 1, 0);\r
+ LED(LED_RED2, 0);\r
+\r
+ // record\r
+ DbpString("Starting recording");\r
+\r
+ // wait for button to be released\r
+ while(BUTTON_PRESS())\r
+ WDT_HIT();\r
+\r
+ /* need this delay to prevent catching some weird data */\r
+ SpinDelay(500);\r
+\r
+ CmdHIDdemodFSK(1, &high[selected], &low[selected], 0);\r
+ DbpString("Recorded");\r
+ DbpIntegers(selected, high[selected], low[selected]);\r
+\r
+ LEDsoff();\r
+ LED(selected + 1, 0);\r
+ // Finished recording\r
+\r
+ // If we were previously playing, set playing off\r
+ // so next button push begins playing what we recorded\r
+ playing = 0;\r
+ }\r
+\r
+ // Change where to record (or begin playing)\r
+ else if (button_pressed)\r
+ {\r
+ // Next option if we were previously playing\r
+ if (playing)\r
+ selected = (selected + 1) % OPTS;\r
+ playing = !playing;\r
+\r
+ LEDsoff();\r
+ LED(selected + 1, 0);\r
+\r
+ // Begin transmitting\r
+ if (playing)\r
+ {\r
+ LED(LED_GREEN, 0);\r
+ DbpString("Playing");\r
+ // wait for button to be released\r
+ while(BUTTON_PRESS())\r
+ WDT_HIT();\r
+ DbpIntegers(selected, high[selected], low[selected]);\r
+ CmdHIDsimTAG(high[selected], low[selected], 0);\r
+ DbpString("Done playing");\r
+ if (BUTTON_HELD(1000) > 0)\r
+ {\r
+ DbpString("Exiting");\r
+ LEDsoff();\r
+ return;\r
+ }\r
+\r
+ /* We pressed a button so ignore it here with a delay */\r
+ SpinDelay(300);\r
+\r
+ // when done, we're done playing, move to next option\r
+ selected = (selected + 1) % OPTS;\r
+ playing = !playing;\r
+ LEDsoff();\r
+ LED(selected + 1, 0);\r
+ }\r
+ else\r
+ while(BUTTON_PRESS())\r
+ WDT_HIT();\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+OBJECTIVE\r
+Listen and detect an external reader. Determine the best location\r
+for the antenna.\r
+\r
+INSTRUCTIONS:\r
+Inside the ListenReaderField() function, there is two mode.\r
+By default, when you call the function, you will enter mode 1.\r
+If you press the PM3 button one time, you will enter mode 2.\r
+If you press the PM3 button a second time, you will exit the function.\r
+\r
+DESCRIPTION OF MODE 1:\r
+This mode just listens for an external reader field and lights up green\r
+for HF and/or red for LF. This is the original mode of the detectreader\r
+function.\r
+\r
+DESCRIPTION OF MODE 2:\r
+This mode will visually represent, using the LEDs, the actual strength of the\r
+current compared to the maximum current detected. Basically, once you know\r
+what kind of external reader is present, it will help you spot the best location to place\r
+your antenna. You will probably not get some good results if there is a LF and a HF reader\r
+at the same place! :-)\r
+\r
+LIGHT SCHEME USED:\r
+*/\r
+static const char LIGHT_SCHEME[] = {\r
+ 0x0, /* ---- | No field detected */\r
+ 0x1, /* X--- | 14% of maximum current detected */\r
+ 0x2, /* -X-- | 29% of maximum current detected */\r
+ 0x4, /* --X- | 43% of maximum current detected */\r
+ 0x8, /* ---X | 57% of maximum current detected */\r
+ 0xC, /* --XX | 71% of maximum current detected */\r
+ 0xE, /* -XXX | 86% of maximum current detected */\r
+ 0xF, /* XXXX | 100% of maximum current detected */\r
+};\r
+static const int LIGHT_LEN = sizeof(LIGHT_SCHEME)/sizeof(LIGHT_SCHEME[0]);\r
+\r
+void ListenReaderField(int limit)\r
+{\r
+ int lf_av, lf_av_new, lf_baseline= 0, lf_count= 0, lf_max;\r
+ int hf_av, hf_av_new, hf_baseline= 0, hf_count= 0, hf_max;\r
+ int mode=1, display_val, display_max, i;\r
+\r
+#define LF_ONLY 1\r
+#define HF_ONLY 2\r
+\r
+ LEDsoff();\r
+\r
+ lf_av=lf_max=ReadAdc(ADC_CHAN_LF);\r
+\r
+ if(limit != HF_ONLY) {\r
+ DbpString("LF 125/134 Baseline:");\r
+ DbpIntegers(lf_av,0,0);\r
+ lf_baseline= lf_av;\r
+ }\r
+\r
+ hf_av=hf_max=ReadAdc(ADC_CHAN_HF);\r
+\r
+ if (limit != LF_ONLY) {\r
+ DbpString("HF 13.56 Baseline:");\r
+ DbpIntegers(hf_av,0,0);\r
+ hf_baseline= hf_av;\r
+ }\r
+\r
+ for(;;) {\r
+ if (BUTTON_PRESS()) {\r
+ SpinDelay(500);\r
+ switch (mode) {\r
+ case 1:\r
+ mode=2;\r
+ DbpString("Signal Strength Mode");\r
+ break;\r
+ case 2:\r
+ default:\r
+ DbpString("Stopped");\r
+ LEDsoff();\r
+ return;\r
+ break;\r
+ }\r
+ }\r
+ WDT_HIT();\r
+\r
+ if (limit != HF_ONLY) {\r
+ if(mode==1) {\r
+ if (abs(lf_av - lf_baseline) > 10) LED_D_ON();\r
+ else LED_D_OFF();\r
+ }\r
+ \r
+ ++lf_count;\r
+ lf_av_new= ReadAdc(ADC_CHAN_LF);\r
+ // see if there's a significant change\r
+ if(abs(lf_av - lf_av_new) > 10) {\r
+ DbpString("LF 125/134 Field Change:");\r
+ DbpIntegers(lf_av,lf_av_new,lf_count);\r
+ lf_av= lf_av_new;\r
+ if (lf_av > lf_max)\r
+ lf_max = lf_av;\r
+ lf_count= 0;\r
+ }\r
+ }\r
+\r
+ if (limit != LF_ONLY) {\r
+ if (mode == 1){\r
+ if (abs(hf_av - hf_baseline) > 10) LED_B_ON();\r
+ else LED_B_OFF();\r
+ }\r
+ \r
+ ++hf_count;\r
+ hf_av_new= ReadAdc(ADC_CHAN_HF);\r
+ // see if there's a significant change\r
+ if(abs(hf_av - hf_av_new) > 10) {\r
+ DbpString("HF 13.56 Field Change:");\r
+ DbpIntegers(hf_av,hf_av_new,hf_count);\r
+ hf_av= hf_av_new;\r
+ if (hf_av > hf_max)\r
+ hf_max = hf_av;\r
+ hf_count= 0;\r
+ }\r
+ }\r
+ \r
+ if(mode == 2) {\r
+ if (limit == LF_ONLY) {\r
+ display_val = lf_av;\r
+ display_max = lf_max;\r
+ } else if (limit == HF_ONLY) {\r
+ display_val = hf_av;\r
+ display_max = hf_max;\r
+ } else { /* Pick one at random */\r
+ if( (hf_max - hf_baseline) > (lf_max - lf_baseline) ) {\r
+ display_val = hf_av;\r
+ display_max = hf_max;\r
+ } else {\r
+ display_val = lf_av;\r
+ display_max = lf_max;\r
+ }\r
+ }\r
+ for (i=0; i<LIGHT_LEN; i++) {\r
+ if (display_val >= ((display_max/LIGHT_LEN)*i) && display_val <= ((display_max/LIGHT_LEN)*(i+1))) {\r
+ if (LIGHT_SCHEME[i] & 0x1) LED_C_ON(); else LED_C_OFF();\r
+ if (LIGHT_SCHEME[i] & 0x2) LED_A_ON(); else LED_A_OFF();\r
+ if (LIGHT_SCHEME[i] & 0x4) LED_B_ON(); else LED_B_OFF();\r
+ if (LIGHT_SCHEME[i] & 0x8) LED_D_ON(); else LED_D_OFF();\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+void UsbPacketReceived(BYTE *packet, int len)\r
+{\r
+ UsbCommand *c = (UsbCommand *)packet;\r
+\r
+ switch(c->cmd) {\r
+ case CMD_ACQUIRE_RAW_ADC_SAMPLES_125K:\r
+ AcquireRawAdcSamples125k(c->ext1);\r
+ break;\r
+\r
+ case CMD_MOD_THEN_ACQUIRE_RAW_ADC_SAMPLES_125K:\r
+ ModThenAcquireRawAdcSamples125k(c->ext1,c->ext2,c->ext3,c->d.asBytes);\r
+ break;\r
+\r
+ case CMD_ACQUIRE_RAW_ADC_SAMPLES_ISO_15693:\r
+ AcquireRawAdcSamplesIso15693();\r
+ break;\r
+\r
+ case CMD_BUFF_CLEAR:\r
+ BufferClear();\r
+ break;\r
+\r
+ case CMD_READER_ISO_15693:\r
+ ReaderIso15693(c->ext1);\r
+ break;\r
+\r
+ case CMD_SIMTAG_ISO_15693:\r
+ SimTagIso15693(c->ext1);\r
+ break;\r
+\r
+ case CMD_ACQUIRE_RAW_ADC_SAMPLES_ISO_14443:\r
+ AcquireRawAdcSamplesIso14443(c->ext1);\r
+ break;\r
+\r
+ case CMD_READ_SRI512_TAG:\r
+ ReadSRI512Iso14443(c->ext1);\r
+ break;\r
+\r
+ case CMD_READER_ISO_14443a:\r
+ ReaderIso14443a(c->ext1);\r
+ break;\r
+\r
+ case CMD_SNOOP_ISO_14443:\r
+ SnoopIso14443();\r
+ break;\r
+\r
+ case CMD_SNOOP_ISO_14443a:\r
+ SnoopIso14443a();\r
+ break;\r
+\r
+ case CMD_SIMULATE_TAG_HF_LISTEN:\r
+ SimulateTagHfListen();\r
+ break;\r
+\r
+ case CMD_SIMULATE_TAG_ISO_14443:\r
+ SimulateIso14443Tag();\r
+ break;\r
+\r
+ case CMD_SIMULATE_TAG_ISO_14443a:\r
+ SimulateIso14443aTag(c->ext1, c->ext2); // ## Simulate iso14443a tag - pass tag type & UID\r
+ break;\r
+\r
+ case CMD_MEASURE_ANTENNA_TUNING:\r
+ MeasureAntennaTuning();\r
+ break;\r
+\r
+ case CMD_LISTEN_READER_FIELD:\r
+ ListenReaderField(c->ext1);\r
+ break;\r
+\r
+ case CMD_HID_DEMOD_FSK:\r
+ CmdHIDdemodFSK(0, 0, 0, 1); // Demodulate HID tag\r
+ break;\r
+\r
+ case CMD_HID_SIM_TAG:\r
+ CmdHIDsimTAG(c->ext1, c->ext2, 1); // Simulate HID tag by ID\r
+ break;\r
+\r
+ case CMD_FPGA_MAJOR_MODE_OFF: // ## FPGA Control\r
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
+ SpinDelay(200);\r
+ LED_D_OFF(); // LED D indicates field ON or OFF\r
+ break;\r
+\r
+ case CMD_READ_TI_TYPE:\r
+ ReadTItag();\r
+ break;\r
+\r
+ case CMD_WRITE_TI_TYPE:\r
+ WriteTItag(c->ext1,c->ext2,c->ext3);\r
+ break;\r
+\r
+ case CMD_DOWNLOAD_RAW_ADC_SAMPLES_125K: {\r
+ UsbCommand n;\r
+ if(c->cmd == CMD_DOWNLOAD_RAW_ADC_SAMPLES_125K) {\r
+ n.cmd = CMD_DOWNLOADED_RAW_ADC_SAMPLES_125K;\r
+ } else {\r
+ n.cmd = CMD_DOWNLOADED_RAW_BITS_TI_TYPE;\r
+ }\r
+ n.ext1 = c->ext1;\r
+ memcpy(n.d.asDwords, BigBuf+c->ext1, 12*sizeof(DWORD));\r
+ UsbSendPacket((BYTE *)&n, sizeof(n));\r
+ break;\r
+ }\r
+ case CMD_DOWNLOADED_SIM_SAMPLES_125K: {\r
+ BYTE *b = (BYTE *)BigBuf;\r
+ memcpy(b+c->ext1, c->d.asBytes, 48);\r
+ break;\r
+ }\r
+ case CMD_SIMULATE_TAG_125K:\r
+ LED_A_ON();\r
+ SimulateTagLowFrequency(c->ext1, 1);\r
+ LED_A_OFF();\r
+ break;\r
+ case CMD_READ_MEM:\r
+ ReadMem(c->ext1);\r
+ break;\r
+ case CMD_SET_LF_DIVISOR:\r
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, c->ext1);\r
+ break;\r
+ case CMD_VERSION:\r
+ SendVersion();\r
+ break;\r
+ case CMD_LF_SIMULATE_BIDIR:\r
+ SimulateTagLowFrequencyBidir(c->ext1, c->ext2);\r
+ break;\r
+#ifdef WITH_LCD\r
+ case CMD_LCD_RESET:\r
+ LCDReset();\r
+ break;\r
+ case CMD_LCD:\r
+ LCDSend(c->ext1);\r
+ break;\r
+#endif\r
+ case CMD_SETUP_WRITE:\r
+ case CMD_FINISH_WRITE:\r
+ case CMD_HARDWARE_RESET:\r
+ USB_D_PLUS_PULLUP_OFF();\r
+ SpinDelay(1000);\r
+ SpinDelay(1000);\r
+ AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;\r
+ for(;;) {\r
+ // We're going to reset, and the bootrom will take control.\r
+ }\r
+ break;\r
+ case CMD_START_FLASH:\r
+ if(common_area.flags.bootrom_present) {\r
+ common_area.command = COMMON_AREA_COMMAND_ENTER_FLASH_MODE;\r
+ }\r
+ USB_D_PLUS_PULLUP_OFF();\r
+ AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;\r
+ for(;;);\r
+ break;\r
+ \r
+ case CMD_DEVICE_INFO: {\r
+ UsbCommand c;\r
+ c.cmd = CMD_DEVICE_INFO;\r
+ c.ext1 = DEVICE_INFO_FLAG_OSIMAGE_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_OS;\r
+ if(common_area.flags.bootrom_present) c.ext1 |= DEVICE_INFO_FLAG_BOOTROM_PRESENT;\r
+ UsbSendPacket((BYTE*)&c, sizeof(c));\r
+ }\r
+ break;\r
+ default:\r
+ DbpString("unknown command");\r
+ break;\r
+ }\r
+}\r
+\r
+void __attribute__((noreturn)) AppMain(void)\r
+{\r
+ SpinDelay(100);\r
+ \r
+ if(common_area.magic != COMMON_AREA_MAGIC || common_area.version != 1) {\r
+ /* Initialize common area */\r
+ memset(&common_area, 0, sizeof(common_area));\r
+ common_area.magic = COMMON_AREA_MAGIC;\r
+ common_area.version = 1;\r
+ }\r
+ common_area.flags.osimage_present = 1;\r
+\r
+ LED_D_OFF();\r
+ LED_C_OFF();\r
+ LED_B_OFF();\r
+ LED_A_OFF();\r
+\r
+ UsbStart();\r
+\r
+ // The FPGA gets its clock from us from PCK0 output, so set that up.\r
+ AT91C_BASE_PIOA->PIO_BSR = GPIO_PCK0;\r
+ AT91C_BASE_PIOA->PIO_PDR = GPIO_PCK0;\r
+ AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK0;\r
+ // PCK0 is PLL clock / 4 = 96Mhz / 4 = 24Mhz\r
+ AT91C_BASE_PMC->PMC_PCKR[0] = AT91C_PMC_CSS_PLL_CLK |\r
+ AT91C_PMC_PRES_CLK_4;\r
+ AT91C_BASE_PIOA->PIO_OER = GPIO_PCK0;\r
+\r
+ // Reset SPI\r
+ AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;\r
+ // Reset SSC\r
+ AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;\r
+\r
+ // Load the FPGA image, which we have stored in our flash.\r
+ FpgaDownloadAndGo();\r
+\r
+#ifdef WITH_LCD\r
+\r
+ LCDInit();\r
+\r
+ // test text on different colored backgrounds\r
+ LCDString(" The quick brown fox ", (char *)&FONT6x8,1,1+8*0,WHITE ,BLACK );\r
+ LCDString(" jumped over the ", (char *)&FONT6x8,1,1+8*1,BLACK ,WHITE );\r
+ LCDString(" lazy dog. ", (char *)&FONT6x8,1,1+8*2,YELLOW ,RED );\r
+ LCDString(" AaBbCcDdEeFfGgHhIiJj ", (char *)&FONT6x8,1,1+8*3,RED ,GREEN );\r
+ LCDString(" KkLlMmNnOoPpQqRrSsTt ", (char *)&FONT6x8,1,1+8*4,MAGENTA,BLUE );\r
+ LCDString("UuVvWwXxYyZz0123456789", (char *)&FONT6x8,1,1+8*5,BLUE ,YELLOW);\r
+ LCDString("`-=[]_;',./~!@#$%^&*()", (char *)&FONT6x8,1,1+8*6,BLACK ,CYAN );\r
+ LCDString(" _+{}|:\\\"<>? ",(char *)&FONT6x8,1,1+8*7,BLUE ,MAGENTA);\r
+\r
+ // color bands\r
+ LCDFill(0, 1+8* 8, 132, 8, BLACK);\r
+ LCDFill(0, 1+8* 9, 132, 8, WHITE);\r
+ LCDFill(0, 1+8*10, 132, 8, RED);\r
+ LCDFill(0, 1+8*11, 132, 8, GREEN);\r
+ LCDFill(0, 1+8*12, 132, 8, BLUE);\r
+ LCDFill(0, 1+8*13, 132, 8, YELLOW);\r
+ LCDFill(0, 1+8*14, 132, 8, CYAN);\r
+ LCDFill(0, 1+8*15, 132, 8, MAGENTA);\r
+\r
+#endif\r
+\r
+ for(;;) {\r
+ UsbPoll(FALSE);\r
+ WDT_HIT();\r
+\r
+ if (BUTTON_HELD(1000) > 0)\r
+ SamyRun();\r
+ }\r
+}\r
void FpgaSetupSsc(void);\r
void SetupSpi(int mode);\r
void FpgaSetupSscDma(BYTE *buf, int len);\r
-void SetAdcMuxFor(int whichGpio);\r
+void SetAdcMuxFor(DWORD whichGpio);\r
\r
// Definitions for the FPGA commands.\r
-#define FPGA_CMD_SET_CONFREG (1<<12)\r
-#define FPGA_CMD_SET_DIVISOR (2<<12)\r
+#define FPGA_CMD_SET_CONFREG (1<<12)\r
+#define FPGA_CMD_SET_DIVISOR (2<<12)\r
// Definitions for the FPGA configuration word.\r
-#define FPGA_MAJOR_MODE_LF_READER (0<<5)\r
+#define FPGA_MAJOR_MODE_LF_READER (0<<5)\r
#define FPGA_MAJOR_MODE_LF_SIMULATOR (1<<5)\r
#define FPGA_MAJOR_MODE_HF_READER_TX (2<<5)\r
-#define FPGA_MAJOR_MODE_HF_READER_RX_XCORR (3<<5)\r
+#define FPGA_MAJOR_MODE_HF_READER_RX_XCORR (3<<5)\r
#define FPGA_MAJOR_MODE_HF_SIMULATOR (4<<5)\r
#define FPGA_MAJOR_MODE_HF_ISO14443A (5<<5)\r
#define FPGA_MAJOR_MODE_LF_PASSTHRU (6<<5)\r
-#define FPGA_MAJOR_MODE_OFF (7<<5)\r
+#define FPGA_MAJOR_MODE_OFF (7<<5)\r
// Options for the HF reader, tx to tag\r
#define FPGA_HF_READER_TX_SHALLOW_MOD (1<<0)\r
// Options for the HF reader, correlating against rx from tag\r
-#define FPGA_HF_READER_RX_XCORR_848_KHZ (1<<0)\r
+#define FPGA_HF_READER_RX_XCORR_848_KHZ (1<<0)\r
#define FPGA_HF_READER_RX_XCORR_SNOOP (1<<1)\r
// Options for the HF simulated tag, how to modulate\r
-#define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0)\r
-#define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0)\r
+#define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0)\r
+#define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0)\r
// Options for ISO14443A\r
-#define FPGA_HF_ISO14443A_SNIFFER (0<<0)\r
-#define FPGA_HF_ISO14443A_TAGSIM_LISTEN (1<<0)\r
+#define FPGA_HF_ISO14443A_SNIFFER (0<<0)\r
+#define FPGA_HF_ISO14443A_TAGSIM_LISTEN (1<<0)\r
#define FPGA_HF_ISO14443A_TAGSIM_MOD (2<<0)\r
-#define FPGA_HF_ISO14443A_READER_LISTEN (3<<0)\r
+#define FPGA_HF_ISO14443A_READER_LISTEN (3<<0)\r
#define FPGA_HF_ISO14443A_READER_MOD (4<<0)\r
\r
/// lfops.h\r
// PA14 -> SPI_SPCK Serial Clock\r
\r
// Disable PIO control of the following pins, allows use by the SPI peripheral\r
- PIO_DISABLE = (1 << GPIO_NCS0) |\r
- (1 << GPIO_NCS2) |\r
- (1 << GPIO_MISO) |\r
- (1 << GPIO_MOSI) |\r
- (1 << GPIO_SPCK);\r
+ AT91C_BASE_PIOA->PIO_PDR =\r
+ GPIO_NCS0 |\r
+ GPIO_NCS2 |\r
+ GPIO_MISO |\r
+ GPIO_MOSI |\r
+ GPIO_SPCK;\r
\r
- PIO_PERIPHERAL_A_SEL = (1 << GPIO_NCS0) |\r
- (1 << GPIO_MISO) |\r
- (1 << GPIO_MOSI) |\r
- (1 << GPIO_SPCK);\r
+ AT91C_BASE_PIOA->PIO_ASR =\r
+ GPIO_NCS0 |\r
+ GPIO_MISO |\r
+ GPIO_MOSI |\r
+ GPIO_SPCK;\r
\r
- PIO_PERIPHERAL_B_SEL = (1 << GPIO_NCS2);\r
+ AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2;\r
\r
//enable the SPI Peripheral clock\r
- PMC_PERIPHERAL_CLK_ENABLE = (1<<PERIPH_SPI);\r
+ AT91C_BASE_PMC->PMC_PCER = (1<<AT91C_ID_SPI);\r
// Enable SPI\r
- SPI_CONTROL = SPI_CONTROL_ENABLE;\r
+ AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;\r
\r
switch (mode) {\r
case SPI_FPGA_MODE:\r
- SPI_MODE =\r
+ AT91C_BASE_SPI->SPI_MR =\r
( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)\r
(14 << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)\r
( 0 << 7) | // Local Loopback Disabled\r
( 0 << 2) | // Chip selects connected directly to peripheral\r
( 0 << 1) | // Fixed Peripheral Select\r
( 1 << 0); // Master Mode\r
- SPI_FOR_CHIPSEL_0 =\r
+ AT91C_BASE_SPI->SPI_CSR[0] =\r
( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)\r
( 1 << 16) | // Delay Before SPCK (1 MCK period)\r
( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
( 0 << 0); // Clock Polarity inactive state is logic 0\r
break;\r
case SPI_LCD_MODE:\r
- SPI_MODE =\r
+ AT91C_BASE_SPI->SPI_MR =\r
( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)\r
(11 << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)\r
( 0 << 7) | // Local Loopback Disabled\r
( 0 << 2) | // Chip selects connected directly to peripheral\r
( 0 << 1) | // Fixed Peripheral Select\r
( 1 << 0); // Master Mode\r
- SPI_FOR_CHIPSEL_2 =\r
+ AT91C_BASE_SPI->SPI_CSR[2] =\r
( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)\r
( 1 << 16) | // Delay Before SPCK (1 MCK period)\r
( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
( 0 << 0); // Clock Polarity inactive state is logic 0\r
break;\r
default: // Disable SPI\r
- SPI_CONTROL = SPI_CONTROL_DISABLE;\r
+ AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;\r
break;\r
}\r
}\r
void FpgaSetupSsc(void)\r
{\r
// First configure the GPIOs, and get ourselves a clock.\r
- PIO_PERIPHERAL_A_SEL = (1 << GPIO_SSC_FRAME) |\r
- (1 << GPIO_SSC_DIN) |\r
- (1 << GPIO_SSC_DOUT) |\r
- (1 << GPIO_SSC_CLK);\r
- PIO_DISABLE = (1 << GPIO_SSC_DOUT);\r
+ AT91C_BASE_PIOA->PIO_ASR =\r
+ GPIO_SSC_FRAME |\r
+ GPIO_SSC_DIN |\r
+ GPIO_SSC_DOUT |\r
+ GPIO_SSC_CLK;\r
+ AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;\r
\r
- PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_SSC);\r
+ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SSC);\r
\r
// Now set up the SSC proper, starting from a known state.\r
- SSC_CONTROL = SSC_CONTROL_RESET;\r
+ AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;\r
\r
// RX clock comes from TX clock, RX starts when TX starts, data changes\r
// on RX clock rising edge, sampled on falling edge\r
- SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);\r
+ AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);\r
\r
// 8 bits per transfer, no loopback, MSB first, 1 transfer per sync\r
// pulse, no output sync, start on positive-going edge of sync\r
- SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(8) |\r
- SSC_FRAME_MODE_MSB_FIRST | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);\r
+ AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) |\r
+ AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);\r
\r
// clock comes from TK pin, no clock output, outputs change on falling\r
// edge of TK, start on rising edge of TF\r
- SSC_TRANSMIT_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(2) |\r
+ AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) |\r
SSC_CLOCK_MODE_START(5);\r
\r
// tx framing is the same as the rx framing\r
- SSC_TRANSMIT_FRAME_MODE = SSC_RECEIVE_FRAME_MODE;\r
+ AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;\r
\r
- SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;\r
+ AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;\r
}\r
\r
//-----------------------------------------------------------------------------\r
//-----------------------------------------------------------------------------\r
void FpgaSetupSscDma(BYTE *buf, int len)\r
{\r
- PDC_RX_POINTER(SSC_BASE) = (DWORD)buf;\r
- PDC_RX_COUNTER(SSC_BASE) = len;\r
- PDC_RX_NEXT_POINTER(SSC_BASE) = (DWORD)buf;\r
- PDC_RX_NEXT_COUNTER(SSC_BASE) = len;\r
- PDC_CONTROL(SSC_BASE) = PDC_RX_ENABLE;\r
+ AT91C_BASE_PDC_SSC->PDC_RPR = (DWORD)buf;\r
+ AT91C_BASE_PDC_SSC->PDC_RCR = len;\r
+ AT91C_BASE_PDC_SSC->PDC_RNPR = (DWORD)buf;\r
+ AT91C_BASE_PDC_SSC->PDC_RNCR = len;\r
+ AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;\r
}\r
\r
static void DownloadFPGA_byte(unsigned char w)\r
{\r
int i=0;\r
\r
- PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);\r
- PIO_ENABLE = (1 << GPIO_FPGA_ON);\r
+ AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;\r
+ AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;\r
HIGH(GPIO_FPGA_ON); // ensure everything is powered on\r
\r
SpinDelay(50);\r
LED_D_ON();\r
\r
// These pins are inputs\r
- PIO_OUTPUT_DISABLE = (1 << GPIO_FPGA_NINIT) | (1 << GPIO_FPGA_DONE);\r
+ AT91C_BASE_PIOA->PIO_ODR =\r
+ GPIO_FPGA_NINIT |\r
+ GPIO_FPGA_DONE;\r
// PIO controls the following pins\r
- PIO_ENABLE = (1 << GPIO_FPGA_NINIT) | (1 << GPIO_FPGA_DONE);\r
+ AT91C_BASE_PIOA->PIO_PER =\r
+ GPIO_FPGA_NINIT |\r
+ GPIO_FPGA_DONE;\r
// Enable pull-ups\r
- PIO_NO_PULL_UP_DISABLE = (1 << GPIO_FPGA_NINIT) | (1 << GPIO_FPGA_DONE);\r
+ AT91C_BASE_PIOA->PIO_PPUER =\r
+ GPIO_FPGA_NINIT |\r
+ GPIO_FPGA_DONE;\r
\r
// setup initial logic state\r
HIGH(GPIO_FPGA_NPROGRAM);\r
LOW(GPIO_FPGA_CCLK);\r
LOW(GPIO_FPGA_DIN);\r
// These pins are outputs\r
- PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_NPROGRAM) |\r
- (1 << GPIO_FPGA_CCLK) |\r
- (1 << GPIO_FPGA_DIN);\r
+ AT91C_BASE_PIOA->PIO_OER =\r
+ GPIO_FPGA_NPROGRAM |\r
+ GPIO_FPGA_CCLK |\r
+ GPIO_FPGA_DIN;\r
\r
// enter FPGA configuration mode\r
LOW(GPIO_FPGA_NPROGRAM);\r
\r
i=100000;\r
// wait for FPGA ready to accept data signal\r
- while ((i) && ( !(PIO_PIN_DATA_STATUS & (1<<GPIO_FPGA_NINIT) ) ) ) {\r
+ while ((i) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_NINIT ) ) ) {\r
i--;\r
}\r
\r
\r
// continue to clock FPGA until ready signal goes high\r
i=100000;\r
- while ( (i--) && ( !(PIO_PIN_DATA_STATUS & (1<<GPIO_FPGA_DONE) ) ) ) {\r
+ while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {\r
HIGH(GPIO_FPGA_CCLK);\r
LOW(GPIO_FPGA_CCLK);\r
}\r
* 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01\r
* After that the format is 1 byte section type (ASCII character), 2 byte length\r
* (big endian), <length> bytes content. Except for section 'e' which has 4 bytes\r
- * length.
+ * length.\r
*/\r
static const char _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};\r
static int bitparse_init(void * start_address, void *end_address)\r
extern char _binary_fpga_bit_start, _binary_fpga_bit_end;\r
void FpgaDownloadAndGo(void)\r
{\r
- /* Check for the new flash image format: Should have the .bit file at &_binary_fpga_bit_start
+ /* Check for the new flash image format: Should have the .bit file at &_binary_fpga_bit_start\r
*/\r
if(bitparse_init(&_binary_fpga_bit_start, &_binary_fpga_bit_end)) {\r
/* Successfully initialized the .bit parser. Find the 'e' section and\r
- * send its contents to the FPGA.
+ * send its contents to the FPGA.\r
*/\r
char *bitstream_start;\r
unsigned int bitstream_length;\r
* = 10,524 DWORDs, stored as DWORDS e.g. little-endian in memory, but each DWORD\r
* is still to be transmitted in MSBit first order. Set the invert flag to indicate\r
* that the DownloadFPGA function should invert every 4 byte sequence when doing\r
- * the bytewise download.
+ * the bytewise download.\r
*/\r
if( *(DWORD*)0x102000 == 0xFFFFFFFF && *(DWORD*)0x102004 == 0xAA995566 )\r
DownloadFPGA((char*)0x102000, 10524*4, 1);\r
void FpgaSendCommand(WORD cmd, WORD v)\r
{\r
SetupSpi(SPI_FPGA_MODE);\r
- while ((SPI_STATUS & SPI_STATUS_TX_EMPTY) == 0); // wait for the transfer to complete\r
- SPI_TX_DATA = SPI_CONTROL_LAST_TRANSFER | cmd | v; // send the data\r
+ while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete\r
+ AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v; // send the data\r
}\r
//-----------------------------------------------------------------------------\r
// Write the FPGA setup word (that determines what mode the logic is in, read\r
// closable, but should only close one at a time. Not an FPGA thing, but\r
// the samples from the ADC always flow through the FPGA.\r
//-----------------------------------------------------------------------------\r
-void SetAdcMuxFor(int whichGpio)\r
+void SetAdcMuxFor(DWORD whichGpio)\r
{\r
- PIO_OUTPUT_ENABLE = (1 << GPIO_MUXSEL_HIPKD) |\r
- (1 << GPIO_MUXSEL_LOPKD) |\r
- (1 << GPIO_MUXSEL_LORAW) |\r
- (1 << GPIO_MUXSEL_HIRAW);\r
-\r
- PIO_ENABLE = (1 << GPIO_MUXSEL_HIPKD) |\r
- (1 << GPIO_MUXSEL_LOPKD) |\r
- (1 << GPIO_MUXSEL_LORAW) |\r
- (1 << GPIO_MUXSEL_HIRAW);\r
+ AT91C_BASE_PIOA->PIO_OER =\r
+ GPIO_MUXSEL_HIPKD |\r
+ GPIO_MUXSEL_LOPKD |\r
+ GPIO_MUXSEL_LORAW |\r
+ GPIO_MUXSEL_HIRAW;\r
+\r
+ AT91C_BASE_PIOA->PIO_PER =\r
+ GPIO_MUXSEL_HIPKD |\r
+ GPIO_MUXSEL_LOPKD |\r
+ GPIO_MUXSEL_LORAW |\r
+ GPIO_MUXSEL_HIRAW;\r
\r
LOW(GPIO_MUXSEL_HIPKD);\r
LOW(GPIO_MUXSEL_HIRAW);\r
\r
if(BUTTON_PRESS()) return FALSE;\r
\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = 0x00;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = 0x00;\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
- BYTE b = (BYTE)SSC_RECEIVE_HOLDING;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+ BYTE b = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
\r
mask = 0x80;\r
for(i = 0; i < 8; i++, mask >>= 1) {\r
LED_D_OFF();\r
FpgaWriteConfWord(\r
FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);\r
- SSC_TRANSMIT_HOLDING = 0xff;\r
+ AT91C_BASE_SSC->SSC_THR = 0xff;\r
FpgaSetupSsc();\r
\r
// Transmit the response.\r
i = 0;\r
for(;;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
BYTE b = resp[i];\r
\r
- SSC_TRANSMIT_HOLDING = b;\r
+ AT91C_BASE_SSC->SSC_THR = b;\r
\r
i++;\r
if(i > respLen) {\r
break;\r
}\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
- volatile BYTE b = (BYTE)SSC_RECEIVE_HOLDING;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+ volatile BYTE b = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
(void)b;\r
}\r
}\r
*\r
* Returns: true if we received a EOF\r
* false if we are still waiting for some more\r
- *
+ *\r
*/\r
static BOOL Handle14443SamplesDemod(int ci, int cq)\r
{\r
* Demodulate the samples we received from the tag\r
* weTx: set to 'TRUE' if we behave like a reader\r
* set to 'FALSE' if we behave like a snooper\r
- * quiet: set to 'TRUE' to disable debug output
+ * quiet: set to 'TRUE' to disable debug output\r
*/\r
static void GetSamplesFor14443Demod(BOOL weTx, int n, BOOL quiet)\r
{\r
(weTx ? 0 : FPGA_HF_READER_RX_XCORR_SNOOP));\r
\r
for(;;) {\r
- int behindBy = lastRxCounter - PDC_RX_COUNTER(SSC_BASE);\r
+ int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;\r
if(behindBy > max) max = behindBy;\r
\r
- while(((lastRxCounter-PDC_RX_COUNTER(SSC_BASE)) & (DMA_BUFFER_SIZE-1))\r
+ while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (DMA_BUFFER_SIZE-1))\r
> 2)\r
{\r
ci = upTo[0];\r
upTo += 2;\r
if(upTo - dmaBuf > DMA_BUFFER_SIZE) {\r
upTo -= DMA_BUFFER_SIZE;\r
- PDC_RX_NEXT_POINTER(SSC_BASE) = (DWORD)upTo;\r
- PDC_RX_NEXT_COUNTER(SSC_BASE) = DMA_BUFFER_SIZE;\r
+ AT91C_BASE_PDC_SSC->PDC_RNPR = (DWORD)upTo;\r
+ AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;\r
}\r
lastRxCounter -= 2;\r
if(lastRxCounter <= 0) {\r
break;\r
}\r
}\r
- PDC_CONTROL(SSC_BASE) = PDC_RX_DISABLE;\r
+ AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;\r
if (!quiet) DbpIntegers(max, gotFrame, Demod.len);\r
}\r
\r
\r
c = 0;\r
for(;;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = 0x43;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = 0x43;\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
SBYTE b;\r
- b = (SBYTE)SSC_RECEIVE_HOLDING;\r
+ b = (SBYTE)AT91C_BASE_SSC->SSC_RHR;\r
\r
dest[c++] = (BYTE)b;\r
\r
\r
FpgaSetupSsc();\r
\r
- while(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = 0xff;\r
+ while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = 0xff;\r
}\r
\r
// Signal field is ON with the appropriate Red LED\r
FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);\r
\r
for(c = 0; c < 10;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = 0xff;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = 0xff;\r
c++;\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
- volatile DWORD r = SSC_RECEIVE_HOLDING;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+ volatile DWORD r = AT91C_BASE_SSC->SSC_RHR;\r
(void)r;\r
}\r
WDT_HIT();\r
\r
c = 0;\r
for(;;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = ToSend[c];\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = ToSend[c];\r
c++;\r
if(c >= ToSendMax) {\r
break;\r
}\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
- volatile DWORD r = SSC_RECEIVE_HOLDING;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+ volatile DWORD r = AT91C_BASE_SSC->SSC_RHR;\r
(void)r;\r
}\r
WDT_HIT();\r
\r
//-----------------------------------------------------------------------------\r
// Read an ISO 14443 tag. We send it some set of commands, and record the\r
-// responses.
-// The command name is misleading, it actually decodes the reponse in HEX
+// responses.\r
+// The command name is misleading, it actually decodes the reponse in HEX\r
// into the output buffer (read the result using hexsamples, not hisamples)\r
//-----------------------------------------------------------------------------\r
void AcquireRawAdcSamplesIso14443(DWORD parameter)\r
GetSamplesFor14443Demod(TRUE, 2000, FALSE);\r
// LED_A_OFF();\r
}\r
-
+\r
//-----------------------------------------------------------------------------\r
// Read a SRI512 ISO 14443 tag.\r
-//
-// SRI512 tags are just simple memory tags, here we're looking at making a dump
-// of the contents of the memory. No anticollision algorithm is done, we assume
-// we have a single tag in the field.
-//
+//\r
+// SRI512 tags are just simple memory tags, here we're looking at making a dump\r
+// of the contents of the memory. No anticollision algorithm is done, we assume\r
+// we have a single tag in the field.\r
+//\r
// I tried to be systematic and check every answer of the tag, every CRC, etc...\r
//-----------------------------------------------------------------------------\r
void ReadSRI512Iso14443(DWORD parameter)\r
{\r
- BYTE i = 0x00;
+ BYTE i = 0x00;\r
\r
// Make sure that we start from off, since the tags are stateful;\r
// confusing things will happen if we don't reset them between reads.\r
FpgaWriteConfWord(\r
FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);\r
SpinDelay(200);\r
-
+\r
// First command: wake up the tag using the INITIATE command\r
BYTE cmd1[] = { 0x06, 0x00, 0x97, 0x5b};\r
CodeIso14443bAsReader(cmd1, sizeof(cmd1));\r
// LED_A_ON();\r
GetSamplesFor14443Demod(TRUE, 2000,TRUE);\r
// LED_A_OFF();\r
-
- if (Demod.len == 0) {
- DbpString("No response from tag");
- return;
- } else {
- DbpString("Randomly generated UID from tag (+ 2 byte CRC):");
- DbpIntegers(Demod.output[0], Demod.output[1],Demod.output[2]);
- }
- // There is a response, SELECT the uid
- DbpString("Now SELECT tag:");
- cmd1[0] = 0x0E; // 0x0E is SELECT
- cmd1[1] = Demod.output[0];
+\r
+ if (Demod.len == 0) {\r
+ DbpString("No response from tag");\r
+ return;\r
+ } else {\r
+ DbpString("Randomly generated UID from tag (+ 2 byte CRC):");\r
+ DbpIntegers(Demod.output[0], Demod.output[1],Demod.output[2]);\r
+ }\r
+ // There is a response, SELECT the uid\r
+ DbpString("Now SELECT tag:");\r
+ cmd1[0] = 0x0E; // 0x0E is SELECT\r
+ cmd1[1] = Demod.output[0];\r
ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);\r
CodeIso14443bAsReader(cmd1, sizeof(cmd1));\r
TransmitFor14443();\r
// LED_A_ON();\r
GetSamplesFor14443Demod(TRUE, 2000,TRUE);\r
// LED_A_OFF();\r
- if (Demod.len != 3) {
- DbpString("Expected 3 bytes from tag, got:");
- DbpIntegers(Demod.len,0x0,0x0);
- return;
- }
- // Check the CRC of the answer:
+ if (Demod.len != 3) {\r
+ DbpString("Expected 3 bytes from tag, got:");\r
+ DbpIntegers(Demod.len,0x0,0x0);\r
+ return;\r
+ }\r
+ // Check the CRC of the answer:\r
ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]);\r
if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) {\r
- DbpString("CRC Error reading select response.");
- return;
- }
- // Check response from the tag: should be the same UID as the command we just sent:
- if (cmd1[1] != Demod.output[0]) {
- DbpString("Bad response to SELECT from Tag, aborting:");
- DbpIntegers(cmd1[1],Demod.output[0],0x0);
- return;
- }
- // Tag is now selected,
- // First get the tag's UID:
- cmd1[0] = 0x0B;
- ComputeCrc14443(CRC_14443_B, cmd1, 1 , &cmd1[1], &cmd1[2]);
+ DbpString("CRC Error reading select response.");\r
+ return;\r
+ }\r
+ // Check response from the tag: should be the same UID as the command we just sent:\r
+ if (cmd1[1] != Demod.output[0]) {\r
+ DbpString("Bad response to SELECT from Tag, aborting:");\r
+ DbpIntegers(cmd1[1],Demod.output[0],0x0);\r
+ return;\r
+ }\r
+ // Tag is now selected,\r
+ // First get the tag's UID:\r
+ cmd1[0] = 0x0B;\r
+ ComputeCrc14443(CRC_14443_B, cmd1, 1 , &cmd1[1], &cmd1[2]);\r
CodeIso14443bAsReader(cmd1, 3); // Only first three bytes for this one\r
TransmitFor14443();\r
// LED_A_ON();\r
GetSamplesFor14443Demod(TRUE, 2000,TRUE);\r
// LED_A_OFF();\r
- if (Demod.len != 10) {
- DbpString("Expected 10 bytes from tag, got:");
- DbpIntegers(Demod.len,0x0,0x0);
- return;
- }
- // The check the CRC of the answer (use cmd1 as temporary variable):
+ if (Demod.len != 10) {\r
+ DbpString("Expected 10 bytes from tag, got:");\r
+ DbpIntegers(Demod.len,0x0,0x0);\r
+ return;\r
+ }\r
+ // The check the CRC of the answer (use cmd1 as temporary variable):\r
ComputeCrc14443(CRC_14443_B, Demod.output, 8, &cmd1[2], &cmd1[3]);\r
if(cmd1[2] != Demod.output[8] || cmd1[3] != Demod.output[9]) {\r
- DbpString("CRC Error reading block! - Below: expected, got");
- DbpIntegers( (cmd1[2]<<8)+cmd1[3], (Demod.output[8]<<8)+Demod.output[9],0);
- // Do not return;, let's go on... (we should retry, maybe ?)
- }
- DbpString("Tag UID (64 bits):");
- DbpIntegers((Demod.output[7]<<24) + (Demod.output[6]<<16) + (Demod.output[5]<<8) + Demod.output[4], (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0], 0);
-
- // Now loop to read all 16 blocks, address from 0 to 15
- DbpString("Tag memory dump, block 0 to 15");
- cmd1[0] = 0x08;
- i = 0x00;
- for (;;) {
- if (i == 0x10) {
- DbpString("System area block (0xff):");
- i = 0xff;
- }
- cmd1[1] = i;
+ DbpString("CRC Error reading block! - Below: expected, got");\r
+ DbpIntegers( (cmd1[2]<<8)+cmd1[3], (Demod.output[8]<<8)+Demod.output[9],0);\r
+ // Do not return;, let's go on... (we should retry, maybe ?)\r
+ }\r
+ DbpString("Tag UID (64 bits):");\r
+ DbpIntegers((Demod.output[7]<<24) + (Demod.output[6]<<16) + (Demod.output[5]<<8) + Demod.output[4], (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0], 0);\r
+\r
+ // Now loop to read all 16 blocks, address from 0 to 15\r
+ DbpString("Tag memory dump, block 0 to 15");\r
+ cmd1[0] = 0x08;\r
+ i = 0x00;\r
+ for (;;) {\r
+ if (i == 0x10) {\r
+ DbpString("System area block (0xff):");\r
+ i = 0xff;\r
+ }\r
+ cmd1[1] = i;\r
ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);\r
CodeIso14443bAsReader(cmd1, sizeof(cmd1));\r
TransmitFor14443();\r
// LED_A_ON();\r
GetSamplesFor14443Demod(TRUE, 2000,TRUE);\r
-// LED_A_OFF();
- if (Demod.len != 6) { // Check if we got an answer from the tag
- DbpString("Expected 6 bytes from tag, got less...");
- return;
- }
- // The check the CRC of the answer (use cmd1 as temporary variable):
+// LED_A_OFF();\r
+ if (Demod.len != 6) { // Check if we got an answer from the tag\r
+ DbpString("Expected 6 bytes from tag, got less...");\r
+ return;\r
+ }\r
+ // The check the CRC of the answer (use cmd1 as temporary variable):\r
ComputeCrc14443(CRC_14443_B, Demod.output, 4, &cmd1[2], &cmd1[3]);\r
if(cmd1[2] != Demod.output[4] || cmd1[3] != Demod.output[5]) {\r
- DbpString("CRC Error reading block! - Below: expected, got");
- DbpIntegers( (cmd1[2]<<8)+cmd1[3], (Demod.output[4]<<8)+Demod.output[5],0);
- // Do not return;, let's go on... (we should retry, maybe ?)
- }
- // Now print out the memory location:
- DbpString("Address , Contents, CRC");
- DbpIntegers(i, (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0], (Demod.output[4]<<8)+Demod.output[5]);
- if (i == 0xff) {
- break;
- }
- i++;
- }
+ DbpString("CRC Error reading block! - Below: expected, got");\r
+ DbpIntegers( (cmd1[2]<<8)+cmd1[3], (Demod.output[4]<<8)+Demod.output[5],0);\r
+ // Do not return;, let's go on... (we should retry, maybe ?)\r
+ }\r
+ // Now print out the memory location:\r
+ DbpString("Address , Contents, CRC");\r
+ DbpIntegers(i, (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0], (Demod.output[4]<<8)+Demod.output[5]);\r
+ if (i == 0xff) {\r
+ break;\r
+ }\r
+ i++;\r
+ }\r
}\r
-
+\r
\r
//=============================================================================\r
// Finally, the `sniffer' combines elements from both the reader and\r
* 0-1023 : Demodulated samples receive (1024 bytes)\r
* 1024-1535 : Last Received command, 512 bytes (reader->tag)\r
* 1536-2047 : Last Received command, 512 bytes(tag->reader)\r
- * 2048-2304 : DMA Buffer, 256 bytes (samples)
+ * 2048-2304 : DMA Buffer, 256 bytes (samples)\r
*/\r
void SnoopIso14443(void)\r
{\r
FpgaSetupSscDma((BYTE *)dmaBuf, DMA_BUFFER_SIZE);\r
// And now we loop, receiving samples.\r
for(;;) {\r
- int behindBy = (lastRxCounter - PDC_RX_COUNTER(SSC_BASE)) &\r
+ int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) &\r
(DMA_BUFFER_SIZE-1);\r
if(behindBy > maxBehindBy) {\r
maxBehindBy = behindBy;\r
if(upTo - dmaBuf > DMA_BUFFER_SIZE) {\r
upTo -= DMA_BUFFER_SIZE;\r
lastRxCounter += DMA_BUFFER_SIZE;\r
- PDC_RX_NEXT_POINTER(SSC_BASE) = (DWORD) upTo;\r
- PDC_RX_NEXT_COUNTER(SSC_BASE) = DMA_BUFFER_SIZE;\r
+ AT91C_BASE_PDC_SSC->PDC_RNPR = (DWORD) upTo;\r
+ AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;\r
}\r
\r
samples += 2;\r
\r
done:\r
LED_D_OFF();\r
- PDC_CONTROL(SSC_BASE) = PDC_RX_DISABLE;\r
+ AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;\r
}\r
// And now we loop, receiving samples.\r
for(;;) {\r
WDT_HIT();\r
- int behindBy = (lastRxCounter - PDC_RX_COUNTER(SSC_BASE)) &\r
+ int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) &\r
(DMA_BUFFER_SIZE-1);\r
if(behindBy > maxBehindBy) {\r
maxBehindBy = behindBy;\r
if(upTo - dmaBuf > DMA_BUFFER_SIZE) {\r
upTo -= DMA_BUFFER_SIZE;\r
lastRxCounter += DMA_BUFFER_SIZE;\r
- PDC_RX_NEXT_POINTER(SSC_BASE) = (DWORD)upTo;\r
- PDC_RX_NEXT_COUNTER(SSC_BASE) = DMA_BUFFER_SIZE;\r
+ AT91C_BASE_PDC_SSC->PDC_RNPR = (DWORD)upTo;\r
+ AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;\r
}\r
\r
samples += 4;\r
DbpIntegers(Uart.byteCntMax, traceLen, (int)Uart.output[0]);\r
\r
done:\r
- PDC_CONTROL(SSC_BASE) = PDC_RX_DISABLE;\r
+ AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;\r
DbpIntegers(maxBehindBy, Uart.state, Uart.byteCnt);\r
DbpIntegers(Uart.byteCntMax, traceLen, (int)Uart.output[0]);\r
LED_A_OFF();\r
\r
if(BUTTON_PRESS()) return FALSE;\r
\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = 0x00;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = 0x00;\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
- BYTE b = (BYTE)SSC_RECEIVE_HOLDING;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+ BYTE b = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
if(MillerDecoding((b & 0xf0) >> 4)) {\r
*len = Uart.byteCnt;\r
return TRUE;\r
\r
// Modulate Manchester\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);\r
- SSC_TRANSMIT_HOLDING = 0x00;\r
+ AT91C_BASE_SSC->SSC_THR = 0x00;\r
FpgaSetupSsc();\r
\r
// ### Transmit the response ###\r
b = 0x00;\r
fdt_indicator = FALSE;\r
for(;;) {\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
- volatile BYTE b = (BYTE)SSC_RECEIVE_HOLDING;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+ volatile BYTE b = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
(void)b;\r
}\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
if(i > respLen) {\r
b = 0x00;\r
u++;\r
b = resp[i];\r
i++;\r
}\r
- SSC_TRANSMIT_HOLDING = b;\r
+ AT91C_BASE_SSC->SSC_THR = b;\r
\r
if(u > 4) {\r
break;\r
if(*wait < 10) { *wait = 10; }\r
\r
for(c = 0; c < *wait;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = 0x00; // For exact timing!\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing!\r
c++;\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
- volatile DWORD r = SSC_RECEIVE_HOLDING;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+ volatile DWORD r = AT91C_BASE_SSC->SSC_RHR;\r
(void)r;\r
}\r
WDT_HIT();\r
\r
c = 0;\r
for(;;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = cmd[c];\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = cmd[c];\r
c++;\r
if(c >= len) {\r
break;\r
}\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
- volatile DWORD r = SSC_RECEIVE_HOLDING;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+ volatile DWORD r = AT91C_BASE_SSC->SSC_RHR;\r
(void)r;\r
}\r
WDT_HIT();\r
for(;;) {\r
WDT_HIT();\r
\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = 0x00; // To make use of exact timing of next command from reader!!\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = 0x00; // To make use of exact timing of next command from reader!!\r
(*elapsed)++;\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
if(c < 512) { c++; } else { return FALSE; }\r
- b = (BYTE)SSC_RECEIVE_HOLDING;\r
+ b = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
if(ManchesterDecoding((b & 0xf0) >> 4)) {\r
*samples = ((c - 1) << 3) + 4;\r
return TRUE;\r
if(*wait < 10) { *wait = 10; }\r
\r
// for(c = 0; c < *wait;) {\r
-// if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
-// SSC_TRANSMIT_HOLDING = 0x00; // For exact timing!\r
+// if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+// AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing!\r
// c++;\r
// }\r
-// if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
-// volatile DWORD r = SSC_RECEIVE_HOLDING;\r
+// if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+// volatile DWORD r = AT91C_BASE_SSC->SSC_RHR;\r
// (void)r;\r
// }\r
// WDT_HIT();\r
\r
c = 0;\r
for(;;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = cmd[c];\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = cmd[c];\r
c++;\r
if(c >= len) {\r
break;\r
}\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
- volatile DWORD r = SSC_RECEIVE_HOLDING;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+ volatile DWORD r = AT91C_BASE_SSC->SSC_RHR;\r
(void)r;\r
}\r
WDT_HIT();\r
\r
c = 0;\r
for(;;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = cmd[c];\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = cmd[c];\r
c++;\r
if(c >= len) {\r
break;\r
}\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
- volatile DWORD r = SSC_RECEIVE_HOLDING;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+ volatile DWORD r = AT91C_BASE_SSC->SSC_RHR;\r
(void)r;\r
}\r
WDT_HIT();\r
c = 0;\r
getNext = FALSE;\r
for(;;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = 0x43;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = 0x43;\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
SBYTE b;\r
- b = (SBYTE)SSC_RECEIVE_HOLDING;\r
+ b = (SBYTE)AT91C_BASE_SSC->SSC_RHR;\r
\r
// The samples are correlations against I and Q versions of the\r
// tone that the tag AM-modulates, so every other sample is I,\r
c = 0;\r
getNext = FALSE;\r
for(;;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = 0x43;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = 0x43;\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
SBYTE b;\r
- b = (SBYTE)SSC_RECEIVE_HOLDING;\r
+ b = (SBYTE)AT91C_BASE_SSC->SSC_RHR;\r
\r
// The samples are correlations against I and Q versions of the\r
// tone that the tag AM-modulates, so every other sample is I,\r
\r
c = 0;\r
for(;;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = ToSend[c];\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = ToSend[c];\r
c++;\r
if(c == ToSendMax+3) {\r
break;\r
}\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
- volatile DWORD r = SSC_RECEIVE_HOLDING;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+ volatile DWORD r = AT91C_BASE_SSC->SSC_RHR;\r
(void)r;\r
}\r
WDT_HIT();\r
c = 0;\r
getNext = FALSE;\r
for(;;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = 0x43;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = 0x43;\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
SBYTE b;\r
- b = (SBYTE)SSC_RECEIVE_HOLDING;\r
+ b = (SBYTE)AT91C_BASE_SSC->SSC_RHR;\r
\r
// The samples are correlations against I and Q versions of the\r
// tone that the tag AM-modulates, so every other sample is I,\r
memset(dest,0,n);\r
i = 0;\r
for(;;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = 0x43;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = 0x43;\r
LED_D_ON();\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
- dest[i] = (BYTE)SSC_RECEIVE_HOLDING;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+ dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
i++;\r
LED_D_OFF();\r
if(i >= n) {\r
{\r
if (b&(1<<i)) {\r
// stop modulating antenna\r
- PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);\r
+ LOW(GPIO_SSC_DOUT);\r
SpinDelayUs(1000);\r
// modulate antenna\r
- PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);\r
+ HIGH(GPIO_SSC_DOUT);\r
SpinDelayUs(1000);\r
} else {\r
// stop modulating antenna\r
- PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);\r
+ LOW(GPIO_SSC_DOUT);\r
SpinDelayUs(300);\r
// modulate antenna\r
- PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);\r
+ HIGH(GPIO_SSC_DOUT);\r
SpinDelayUs(1700);\r
}\r
}\r
memset(BigBuf,0,sizeof(BigBuf));\r
\r
// Set up the synchronous serial port\r
- PIO_DISABLE = (1<<GPIO_SSC_DIN);\r
- PIO_PERIPHERAL_A_SEL = (1<<GPIO_SSC_DIN);\r
+ AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;\r
+ AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;\r
\r
// steal this pin from the SSP and use it to control the modulation\r
- PIO_ENABLE = (1<<GPIO_SSC_DOUT);\r
- PIO_OUTPUT_ENABLE = (1<<GPIO_SSC_DOUT);\r
+ AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r
+ AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
\r
- SSC_CONTROL = SSC_CONTROL_RESET;\r
- SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;\r
+ AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;\r
+ AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;\r
\r
- // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long\r
- // 48/2 = 24 MHz clock must be divided by 12\r
- SSC_CLOCK_DIVISOR = 12;\r
+ // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long\r
+ // 48/2 = 24 MHz clock must be divided by 12\r
+ AT91C_BASE_SSC->SSC_CMR = 12;\r
\r
- SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(0);\r
- SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(32) | SSC_FRAME_MODE_MSB_FIRST;\r
- SSC_TRANSMIT_CLOCK_MODE = 0;\r
- SSC_TRANSMIT_FRAME_MODE = 0;\r
+ AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);\r
+ AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;\r
+ AT91C_BASE_SSC->SSC_TCMR = 0;\r
+ AT91C_BASE_SSC->SSC_TFMR = 0;\r
\r
LED_D_ON();\r
\r
// modulate antenna\r
- PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);\r
+ HIGH(GPIO_SSC_DOUT);\r
\r
// Charge TI tag for 50ms.\r
SpinDelay(50);\r
\r
// stop modulating antenna and listen\r
- PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);\r
+ LOW(GPIO_SSC_DOUT);\r
\r
LED_D_OFF();\r
\r
i = 0;\r
for(;;) {\r
- if(SSC_STATUS & SSC_STATUS_RX_READY) {\r
- BigBuf[i] = SSC_RECEIVE_HOLDING; // store 32 bit values in buffer\r
- i++; if(i >= TIBUFLEN) break;\r
- }\r
- WDT_HIT();\r
+ if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r
+ BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer\r
+ i++; if(i >= TIBUFLEN) break;\r
+ }\r
+ WDT_HIT();\r
}\r
\r
// return stolen pin to SSP\r
- PIO_DISABLE = (1<<GPIO_SSC_DOUT);\r
- PIO_PERIPHERAL_A_SEL = (1<<GPIO_SSC_DIN) | (1<<GPIO_SSC_DOUT);\r
+ AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;\r
+ AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;\r
\r
char *dest = (char *)BigBuf;\r
n = TIBUFLEN*32;\r
LED_A_ON();\r
\r
// steal this pin from the SSP and use it to control the modulation\r
- PIO_ENABLE = (1<<GPIO_SSC_DOUT);\r
- PIO_OUTPUT_ENABLE = (1<<GPIO_SSC_DOUT);\r
+ AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r
+ AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
\r
// writing algorithm:\r
// a high bit consists of a field off for 1ms and field on for 1ms\r
// finish with 15ms programming time\r
\r
// modulate antenna\r
- PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);\r
+ HIGH(GPIO_SSC_DOUT);\r
SpinDelay(50); // charge time\r
\r
WriteTIbyte(0xbb); // keyword\r
WriteTIbyte( (crc>>8 )&0xff ); // crc hi\r
WriteTIbyte(0x00); // write frame lo\r
WriteTIbyte(0x03); // write frame hi\r
- PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);\r
+ HIGH(GPIO_SSC_DOUT);\r
SpinDelay(50); // programming time\r
\r
LED_A_OFF();\r
\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
\r
- PIO_ENABLE = (1 << GPIO_SSC_DOUT) | (1 << GPIO_SSC_CLK);\r
+ AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;\r
\r
- PIO_OUTPUT_ENABLE = (1 << GPIO_SSC_DOUT);\r
- PIO_OUTPUT_DISABLE = (1 << GPIO_SSC_CLK);\r
+ AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
+ AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;\r
\r
#define SHORT_COIL() LOW(GPIO_SSC_DOUT)\r
-#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)\r
+#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)\r
\r
i = 0;\r
for(;;) {\r
- while(!(PIO_PIN_DATA_STATUS & (1<<GPIO_SSC_CLK))) {\r
+ while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {\r
if(BUTTON_PRESS()) {\r
DbpString("Stopped");\r
return;\r
if (ledcontrol)\r
LED_D_OFF();\r
\r
- while(PIO_PIN_DATA_STATUS & (1<<GPIO_SSC_CLK)) {\r
+ while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {\r
if(BUTTON_PRESS()) {\r
DbpString("Stopped");\r
return;\r
hitag2_init();\r
\r
/* Set up simulator mode, frequency divisor which will drive the FPGA\r
- * and analog mux selection.
+ * and analog mux selection.\r
*/\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);\r
/* Set up Timer 1:\r
* Capture mode, timer source MCK/2 (TIMER_CLOCK1), TIOA is external trigger,\r
* external trigger rising edge, load RA on rising edge of TIOA, load RB on rising\r
- * edge of TIOA. Assign PA15 to TIOA1 (peripheral B)
+ * edge of TIOA. Assign PA15 to TIOA1 (peripheral B)\r
*/\r
\r
- PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_TC1);\r
- PIO_PERIPHERAL_B_SEL = (1 << GPIO_SSC_FRAME);\r
- TC1_CCR = TC_CCR_CLKDIS;\r
- TC1_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_ETRGEDG_RISING | TC_CMR_ABETRG |\r
- TC_CMR_LDRA_RISING | TC_CMR_LDRB_RISING;\r
- TC1_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;\r
+ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);\r
+ AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;\r
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r
+ AT91C_BASE_TC1->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 |\r
+ AT91C_TC_ETRGEDG_RISING |\r
+ AT91C_TC_ABETRG |\r
+ AT91C_TC_LDRA_RISING |\r
+ AT91C_TC_LDRB_RISING;\r
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN |\r
+ AT91C_TC_SWTRG;\r
\r
/* calculate the new value for the carrier period in terms of TC1 values */\r
t0 = t0/2;\r
int overflow = 0;\r
while(!BUTTON_PRESS()) {\r
WDT_HIT();\r
- if(TC1_SR & TC_SR_LDRAS) {\r
- int ra = TC1_RA;\r
+ if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {\r
+ int ra = AT91C_BASE_TC1->TC_RA;\r
if((ra > t0*HITAG_T_EOF) | overflow) ra = t0*HITAG_T_EOF+1;\r
#if DEBUG_RA_VALUES\r
if(ra > 255 || overflow) ra = 255;\r
overflow = 0;\r
LED_D_ON();\r
} else {\r
- if(TC1_CV > t0*HITAG_T_EOF) {\r
+ if(AT91C_BASE_TC1->TC_CV > t0*HITAG_T_EOF) {\r
/* Minor nuisance: In Capture mode, the timer can not be\r
* stopped by a Compare C. There's no way to stop the clock\r
* in software, so we'll just have to note the fact that an\r
* overflow happened and the next loaded timer value might\r
* have wrapped. Also, this marks the end of frame, and the\r
* still running counter can be used to determine the correct\r
- * time for the start of the reply.
+ * time for the start of the reply.\r
*/ \r
overflow = 1;\r
\r
/* Manchester: Loaded, then unloaded */\r
LED_A_ON();\r
SHORT_COIL();\r
- while(TC1_CV < t0*15);\r
+ while(AT91C_BASE_TC1->TC_CV < t0*15);\r
OPEN_COIL();\r
- while(TC1_CV < t0*31);\r
+ while(AT91C_BASE_TC1->TC_CV < t0*31);\r
LED_A_OFF();\r
} else if(bit == 0) {\r
/* Manchester: Unloaded, then loaded */\r
LED_B_ON();\r
OPEN_COIL();\r
- while(TC1_CV < t0*15);\r
+ while(AT91C_BASE_TC1->TC_CV < t0*15);\r
SHORT_COIL();\r
- while(TC1_CV < t0*31);\r
+ while(AT91C_BASE_TC1->TC_CV < t0*31);\r
LED_B_OFF();\r
}\r
- TC1_CCR = TC_CCR_SWTRG; /* Reset clock for the next bit */\r
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset clock for the next bit */\r
\r
}\r
static void hitag_send_frame(int t0, int frame_len, const char const * frame, int fdt)\r
{\r
OPEN_COIL();\r
- PIO_OUTPUT_ENABLE = (1 << GPIO_SSC_DOUT);\r
+ AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
\r
/* Wait for HITAG_T_WRESP carrier periods after the last reader bit,\r
* not that since the clock counts since the rising edge, but T_wresp is\r
* with respect to the falling edge, we need to wait actually (T_wresp - T_g)\r
- * periods. The gap time T_g varies (4..10).
+ * periods. The gap time T_g varies (4..10).\r
*/\r
- while(TC1_CV < t0*(fdt-8));\r
+ while(AT91C_BASE_TC1->TC_CV < t0*(fdt-8));\r
\r
- int saved_cmr = TC1_CMR;\r
- TC1_CMR &= ~TC_CMR_ETRGEDG; /* Disable external trigger for the clock */\r
- TC1_CCR = TC_CCR_SWTRG; /* Reset the clock and use it for response timing */\r
+ int saved_cmr = AT91C_BASE_TC1->TC_CMR;\r
+ AT91C_BASE_TC1->TC_CMR &= ~AT91C_TC_ETRGEDG; /* Disable external trigger for the clock */\r
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset the clock and use it for response timing */\r
\r
int i;\r
for(i=0; i<5; i++)\r
}\r
\r
OPEN_COIL();\r
- TC1_CMR = saved_cmr;\r
+ AT91C_BASE_TC1->TC_CMR = saved_cmr;\r
}\r
\r
/* Callback structure to cleanly separate tag emulation code from the radio layer. */\r
m = sizeof(BigBuf);\r
memset(dest,128,m);\r
for(;;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = 0x43;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = 0x43;\r
if (ledcontrol)\r
LED_D_ON();\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
- dest[i] = (BYTE)SSC_RECEIVE_HOLDING;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+ dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
// we don't care about actual value, only if it's more or less than a\r
// threshold essentially we capture zero crossings for later analysis\r
if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;\r
return BUTTON_NO_CLICK;\r
\r
// Borrow a PWM unit for my real-time clock\r
- PWM_ENABLE = PWM_CHANNEL(0);\r
+ AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);\r
// 48 MHz / 1024 gives 46.875 kHz\r
- PWM_CH_MODE(0) = PWM_CH_MODE_PRESCALER(10);\r
- PWM_CH_DUTY_CYCLE(0) = 0;\r
- PWM_CH_PERIOD(0) = 0xffff;\r
+ AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);\r
+ AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;\r
+ AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;\r
\r
- WORD start = (WORD)PWM_CH_COUNTER(0);\r
+ WORD start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;\r
\r
int letoff = 0;\r
for(;;)\r
{\r
- WORD now = (WORD)PWM_CH_COUNTER(0);\r
+ WORD now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;\r
\r
// We haven't let off the button yet\r
if (!letoff)\r
letoff = 1;\r
\r
// reset our timer for 500ms\r
- start = (WORD)PWM_CH_COUNTER(0);\r
+ start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;\r
ticks = (48000 * (500)) >> 10;\r
}\r
\r
return BUTTON_NO_CLICK;\r
\r
// Borrow a PWM unit for my real-time clock\r
- PWM_ENABLE = PWM_CHANNEL(0);\r
+ AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);\r
// 48 MHz / 1024 gives 46.875 kHz\r
- PWM_CH_MODE(0) = PWM_CH_MODE_PRESCALER(10);\r
- PWM_CH_DUTY_CYCLE(0) = 0;\r
- PWM_CH_PERIOD(0) = 0xffff;\r
+ AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);\r
+ AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;\r
+ AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;\r
\r
- WORD start = (WORD)PWM_CH_COUNTER(0);\r
+ WORD start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;\r
\r
for(;;)\r
{\r
- WORD now = (WORD)PWM_CH_COUNTER(0);\r
+ WORD now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;\r
\r
// As soon as our button let go, we didn't hold long enough\r
if (!BUTTON_PRESS())\r
int ticks = (48*us) >> 10;\r
\r
// Borrow a PWM unit for my real-time clock\r
- PWM_ENABLE = PWM_CHANNEL(0);\r
+ AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);\r
// 48 MHz / 1024 gives 46.875 kHz\r
- PWM_CH_MODE(0) = PWM_CH_MODE_PRESCALER(10);\r
- PWM_CH_DUTY_CYCLE(0) = 0;\r
- PWM_CH_PERIOD(0) = 0xffff;\r
+ AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);\r
+ AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;\r
+ AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;\r
\r
- WORD start = (WORD)PWM_CH_COUNTER(0);\r
+ WORD start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;\r
\r
for(;;) {\r
- WORD now = (WORD)PWM_CH_COUNTER(0);\r
+ WORD now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;\r
if (now == (WORD)(start + ticks))\r
return;\r
\r
/* Similar to FpgaGatherVersion this formats stored version information\r
* into a string representation. It takes a pointer to the struct version_information,\r
* verifies the magic properties, then stores a formatted string, prefixed by\r
- * prefix in dst.
+ * prefix in dst.\r
*/\r
void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information)\r
{\r
#include <proxmark3.h>\r
\r
struct common_area common_area __attribute__((section(".commonarea")));\r
-unsigned int start_addr, end_addr, bootrom_unlocked; \r
+unsigned int start_addr, end_addr, bootrom_unlocked;\r
extern char _bootrom_start, _bootrom_end, _flash_start, _flash_end;\r
\r
static void ConfigClocks(void)\r
// slow clock runs at 32Khz typical regardless of crystal\r
\r
// enable system clock and USB clock\r
- PMC_SYS_CLK_ENABLE = PMC_SYS_CLK_PROCESSOR_CLK | PMC_SYS_CLK_UDP_CLK;\r
+ AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK | AT91C_PMC_UDP;\r
\r
// enable the clock to the following peripherals\r
- PMC_PERIPHERAL_CLK_ENABLE =\r
- (1<<PERIPH_PIOA) |\r
- (1<<PERIPH_ADC) |\r
- (1<<PERIPH_SPI) |\r
- (1<<PERIPH_SSC) |\r
- (1<<PERIPH_PWMC) |\r
- (1<<PERIPH_UDP);\r
+ AT91C_BASE_PMC->PMC_PCER =\r
+ (1<<AT91C_ID_PIOA) |\r
+ (1<<AT91C_ID_ADC) |\r
+ (1<<AT91C_ID_SPI) |\r
+ (1<<AT91C_ID_SSC) |\r
+ (1<<AT91C_ID_PWMC) |\r
+ (1<<AT91C_ID_UDP);\r
\r
// worst case scenario, with 16Mhz xtal startup delay is 14.5ms\r
// with a slow clock running at it worst case (max) frequency of 42khz\r
// max startup delay = (14.5ms*42k)/8 = 76 = 0x4C round up to 0x50\r
\r
// enable main oscillator and set startup delay\r
- PMC_MAIN_OSCILLATOR = PMC_MAIN_OSCILLATOR_ENABLE |\r
- PMC_MAIN_OSCILLATOR_STARTUP_DELAY(0x50);\r
+ AT91C_BASE_PMC->PMC_MOR =\r
+ PMC_MAIN_OSC_ENABLE |\r
+ PMC_MAIN_OSC_STARTUP_DELAY(0x50);\r
\r
// wait for main oscillator to stabilize\r
- while ( !(PMC_INTERRUPT_STATUS & PMC_MAIN_OSCILLATOR_STABILIZED) )\r
+ while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_STABILIZED) )\r
;\r
\r
// minimum PLL clock frequency is 80 MHz in range 00 (96 here so okay)\r
// frequency is crystal * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz\r
- PMC_PLL = PMC_PLL_DIVISOR(2) | PMC_PLL_COUNT_BEFORE_LOCK(0x50) |\r
- PMC_PLL_FREQUENCY_RANGE(0) | PMC_PLL_MULTIPLIER(12) |\r
- PMC_PLL_USB_DIVISOR(1);\r
+ AT91C_BASE_PMC->PMC_PLLR =\r
+ PMC_PLL_DIVISOR(2) |\r
+ PMC_PLL_COUNT_BEFORE_LOCK(0x50) |\r
+ PMC_PLL_FREQUENCY_RANGE(0) |\r
+ PMC_PLL_MULTIPLIER(12) |\r
+ PMC_PLL_USB_DIVISOR(1);\r
\r
// wait for PLL to lock\r
- while ( !(PMC_INTERRUPT_STATUS & PMC_MAIN_OSCILLATOR_PLL_LOCK) )\r
+ while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_PLL_LOCK) )\r
;\r
\r
// we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz\r
// as per datasheet, this register must be programmed in two operations\r
// when changing to PLL, program the prescaler first then the source\r
- PMC_MASTER_CLK = PMC_CLK_PRESCALE_DIV_2;\r
+ AT91C_BASE_PMC->PMC_MCKR = PMC_CLK_PRESCALE_DIV_2;\r
\r
// wait for main clock ready signal\r
- while ( !(PMC_INTERRUPT_STATUS & PMC_MAIN_OSCILLATOR_MCK_READY) )\r
+ while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_MCK_READY) )\r
;\r
\r
// set the source to PLL\r
- PMC_MASTER_CLK = PMC_CLK_SELECTION_PLL_CLOCK | PMC_CLK_PRESCALE_DIV_2;\r
+ AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | PMC_CLK_PRESCALE_DIV_2;\r
\r
// wait for main clock ready signal\r
- while ( !(PMC_INTERRUPT_STATUS & PMC_MAIN_OSCILLATOR_MCK_READY) )\r
+ while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_MCK_READY) )\r
;\r
}\r
\r
case CMD_DEVICE_INFO:\r
dont_ack = 1;\r
c->cmd = CMD_DEVICE_INFO;\r
- c->ext1 = DEVICE_INFO_FLAG_BOOTROM_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM | \r
+ c->ext1 = DEVICE_INFO_FLAG_BOOTROM_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM |\r
DEVICE_INFO_FLAG_UNDERSTANDS_START_FLASH;\r
if(common_area.flags.osimage_present) c->ext1 |= DEVICE_INFO_FLAG_OSIMAGE_PRESENT;\r
UsbSendPacket(packet, len);\r
\r
case CMD_SETUP_WRITE:\r
/* The temporary write buffer of the embedded flash controller is mapped to the\r
- * whole memory region, only the last 8 bits are decoded.
+ * whole memory region, only the last 8 bits are decoded.\r
*/\r
p = (volatile DWORD *)&_flash_start;\r
for(i = 0; i < 12; i++) {\r
}\r
\r
/* Check that the address that we are supposed to write to is within our allowed region */\r
- if( ((c->ext1+FLASH_PAGE_SIZE_BYTES-1) >= end_addr) || (c->ext1 < start_addr) ) {\r
+ if( ((c->ext1+AT91C_IFLASH_PAGE_SIZE-1) >= end_addr) || (c->ext1 < start_addr) ) {\r
/* Disallow write */\r
dont_ack = 1;\r
c->cmd = CMD_NACK;\r
UsbSendPacket(packet, len);\r
} else {\r
/* Translate address to flash page and do flash, update here for the 512k part */\r
- MC_FLASH_COMMAND = MC_FLASH_COMMAND_KEY |\r
- MC_FLASH_COMMAND_PAGEN((c->ext1-(int)&_flash_start)/FLASH_PAGE_SIZE_BYTES) |\r
- FCMD_WRITE_PAGE;\r
+ AT91C_BASE_EFC0->EFC_FCR = MC_FLASH_COMMAND_KEY |\r
+ MC_FLASH_COMMAND_PAGEN((c->ext1-(int)&_flash_start)/AT91C_IFLASH_PAGE_SIZE) |\r
+ AT91C_MC_FCMD_START_PROG;\r
}\r
- while(!(MC_FLASH_STATUS & MC_FLASH_STATUS_READY))\r
+ while(!(AT91C_BASE_EFC0->EFC_FSR & MC_FLASH_STATUS_READY))\r
;\r
break;\r
\r
case CMD_HARDWARE_RESET:\r
USB_D_PLUS_PULLUP_OFF();\r
- RSTC_CONTROL = RST_CONTROL_KEY | RST_CONTROL_PROCESSOR_RESET;\r
+ AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;\r
break;\r
- \r
+\r
case CMD_START_FLASH:\r
if(c->ext3 == START_FLASH_MAGIC) bootrom_unlocked = 1;\r
else bootrom_unlocked = 0;\r
int allow_end = (int)&_flash_end;\r
int cmd_start = c->ext1;\r
int cmd_end = c->ext2;\r
- \r
+\r
/* Only allow command if the bootrom is unlocked, or the parameters are outside of the protected\r
- * bootrom area. In any case they must be within the flash area.
+ * bootrom area. In any case they must be within the flash area.\r
*/\r
if( (bootrom_unlocked || ((cmd_start >= prot_end) || (cmd_end < prot_start)))\r
&& (cmd_start >= allow_start) && (cmd_end <= allow_end) ) {\r
}\r
}\r
break;\r
- \r
+\r
default:\r
Fatal();\r
break;\r
start_addr = 0;\r
end_addr = 0;\r
bootrom_unlocked = 0;\r
- \r
+\r
UsbStart();\r
for(;;) {\r
WDT_HIT();\r
- \r
+\r
UsbPoll(TRUE);\r
- \r
+\r
if(!externally_entered && !BUTTON_PRESS()) {\r
/* Perform a reset to leave flash mode */\r
USB_D_PLUS_PULLUP_OFF();\r
LED_B_ON();\r
- RSTC_CONTROL = RST_CONTROL_KEY | RST_CONTROL_PROCESSOR_RESET;\r
+ AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;\r
for(;;);\r
}\r
if(externally_entered && BUTTON_PRESS()) {\r
\r
// Kill all the pullups, especially the one on USB D+; leave them for\r
// the unused pins, though.\r
- PIO_NO_PULL_UP_ENABLE = (1 << GPIO_USB_PU) |\r
- (1 << GPIO_LED_A) |\r
- (1 << GPIO_LED_B) |\r
- (1 << GPIO_LED_C) |\r
- (1 << GPIO_LED_D) |\r
- (1 << GPIO_FPGA_DIN) |\r
- (1 << GPIO_FPGA_DOUT) |\r
- (1 << GPIO_FPGA_CCLK) |\r
- (1 << GPIO_FPGA_NINIT) |\r
- (1 << GPIO_FPGA_NPROGRAM) |\r
- (1 << GPIO_FPGA_DONE) |\r
- (1 << GPIO_MUXSEL_HIPKD) |\r
- (1 << GPIO_MUXSEL_HIRAW) |\r
- (1 << GPIO_MUXSEL_LOPKD) |\r
- (1 << GPIO_MUXSEL_LORAW) |\r
- (1 << GPIO_RELAY) |\r
- (1 << GPIO_NVDD_ON);\r
- // (and add GPIO_FPGA_ON)\r
+ AT91C_BASE_PIOA->PIO_PPUDR =\r
+ GPIO_USB_PU |\r
+ GPIO_LED_A |\r
+ GPIO_LED_B |\r
+ GPIO_LED_C |\r
+ GPIO_LED_D |\r
+ GPIO_FPGA_DIN |\r
+ GPIO_FPGA_DOUT |\r
+ GPIO_FPGA_CCLK |\r
+ GPIO_FPGA_NINIT |\r
+ GPIO_FPGA_NPROGRAM |\r
+ GPIO_FPGA_DONE |\r
+ GPIO_MUXSEL_HIPKD |\r
+ GPIO_MUXSEL_HIRAW |\r
+ GPIO_MUXSEL_LOPKD |\r
+ GPIO_MUXSEL_LORAW |\r
+ GPIO_RELAY |\r
+ GPIO_NVDD_ON;\r
+ // (and add GPIO_FPGA_ON)\r
// These pins are outputs\r
- PIO_OUTPUT_ENABLE = (1 << GPIO_LED_A) |\r
- (1 << GPIO_LED_B) |\r
- (1 << GPIO_LED_C) |\r
- (1 << GPIO_LED_D) |\r
- (1 << GPIO_RELAY) |\r
- (1 << GPIO_NVDD_ON);\r
+ AT91C_BASE_PIOA->PIO_OER =\r
+ GPIO_LED_A |\r
+ GPIO_LED_B |\r
+ GPIO_LED_C |\r
+ GPIO_LED_D |\r
+ GPIO_RELAY |\r
+ GPIO_NVDD_ON;\r
// PIO controls the following pins\r
- PIO_ENABLE = (1 << GPIO_USB_PU) |\r
- (1 << GPIO_LED_A) |\r
- (1 << GPIO_LED_B) |\r
- (1 << GPIO_LED_C) |\r
- (1 << GPIO_LED_D);\r
+ AT91C_BASE_PIOA->PIO_PER =\r
+ GPIO_USB_PU |\r
+ GPIO_LED_A |\r
+ GPIO_LED_B |\r
+ GPIO_LED_C |\r
+ GPIO_LED_D;\r
\r
USB_D_PLUS_PULLUP_OFF();\r
LED_D_OFF();\r
LED_C_ON();\r
LED_B_OFF();\r
LED_A_OFF();\r
- \r
+\r
// if 512K FLASH part - TODO make some defines :)\r
- if ((DBGU_CIDR | 0xf00) == 0xa00) {\r
- MC_FLASH_MODE0 = MC_FLASH_MODE_FLASH_WAIT_STATES(1) |\r
- MC_FLASH_MODE_MASTER_CLK_IN_MHZ(0x48);\r
- MC_FLASH_MODE1 = MC_FLASH_MODE_FLASH_WAIT_STATES(1) |\r
- MC_FLASH_MODE_MASTER_CLK_IN_MHZ(0x48);\r
+ if ((AT91C_BASE_DBGU->DBGU_CIDR | 0xf00) == 0xa00) {\r
+ AT91C_BASE_EFC0->EFC_FMR =\r
+ MC_FLASH_MODE_FLASH_WAIT_STATES(1) |\r
+ MC_FLASH_MODE_MASTER_CLK_IN_MHZ(0x48);\r
+ AT91C_BASE_EFC1->EFC_FMR =\r
+ MC_FLASH_MODE_FLASH_WAIT_STATES(1) |\r
+ MC_FLASH_MODE_MASTER_CLK_IN_MHZ(0x48);\r
} else {\r
- MC_FLASH_MODE0 = MC_FLASH_MODE_FLASH_WAIT_STATES(0) |\r
- MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);\r
+ AT91C_BASE_EFC0->EFC_FMR =\r
+ MC_FLASH_MODE_FLASH_WAIT_STATES(0) |\r
+ MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);\r
}\r
- \r
+\r
// Initialize all system clocks\r
ConfigClocks();\r
- \r
+\r
LED_A_ON();\r
- \r
+\r
int common_area_present = 0;\r
- switch(RSTC_STATUS & RST_STATUS_TYPE_MASK) {\r
- case RST_STATUS_TYPE_WATCHDOG:\r
- case RST_STATUS_TYPE_SOFTWARE:\r
- case RST_STATUS_TYPE_USER:\r
+ switch(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_RSTTYP) {\r
+ case AT91C_RSTC_RSTTYP_WATCHDOG:\r
+ case AT91C_RSTC_RSTTYP_SOFTWARE:\r
+ case AT91C_RSTC_RSTTYP_USER:\r
/* In these cases the common_area in RAM should be ok, retain it if it's there */\r
if(common_area.magic == COMMON_AREA_MAGIC && common_area.version == 1) {\r
common_area_present = 1;\r
default: /* Otherwise, initialize it from scratch */\r
break;\r
}\r
- \r
+\r
if(!common_area_present){\r
/* Common area not ok, initialize it */\r
int i; for(i=0; i<sizeof(common_area); i++) { /* Makeshift memset, no need to drag util.c into this */\r
common_area.version = 1;\r
common_area.flags.bootrom_present = 1;\r
}\r
- \r
+\r
common_area.flags.bootrom_present = 1;\r
if(common_area.command == COMMON_AREA_COMMAND_ENTER_FLASH_MODE) {\r
common_area.command = COMMON_AREA_COMMAND_NONE;\r
# Also search prerequisites in the common directory (for usb.c), and the fpga directory (for fpga.bit)
VPATH = . ../common/ ../fpga/
-INCLUDES = ../include/proxmark3.h ../include/at91sam7s128.h ../include/config_gpio.h ../include/usb_cmd.h $(APP_INCLUDES)
+INCLUDES = ../include/proxmark3.h ../include/at91sam7s512.h ../include/config_gpio.h ../include/usb_cmd.h $(APP_INCLUDES)
CFLAGS = -c $(INCLUDE) -Wall -Werror -pedantic -std=gnu99 $(APP_CFLAGS)
len -= thisTime;\r
\r
for(i = 0; i < thisTime; i++) {\r
- UDP_ENDPOINT_FIFO(0) = *data;\r
+ AT91C_BASE_UDP->UDP_FDR[0] = *data;\r
data++;\r
}\r
\r
- if(UDP_ENDPOINT_CSR(0) & UDP_CSR_TX_PACKET_ACKED) {\r
- UDP_ENDPOINT_CSR(0) &= ~UDP_CSR_TX_PACKET_ACKED;\r
- while(UDP_ENDPOINT_CSR(0) & UDP_CSR_TX_PACKET_ACKED)\r
+ if(AT91C_BASE_UDP->UDP_CSR[0] & AT91C_UDP_TXCOMP) {\r
+ AT91C_BASE_UDP->UDP_CSR[0] &= ~AT91C_UDP_TXCOMP;\r
+ while(AT91C_BASE_UDP->UDP_CSR[0] & AT91C_UDP_TXCOMP)\r
;\r
}\r
\r
- UDP_ENDPOINT_CSR(0) |= UDP_CSR_TX_PACKET;\r
+ AT91C_BASE_UDP->UDP_CSR[0] |= AT91C_UDP_TXPKTRDY;\r
\r
do {\r
- if(UDP_ENDPOINT_CSR(0) & UDP_CSR_RX_PACKET_RECEIVED_BANK_0) {\r
+ if(AT91C_BASE_UDP->UDP_CSR[0] & AT91C_UDP_RX_DATA_BK0) {\r
// This means that the host is trying to write to us, so\r
// abandon our write to them.\r
- UDP_ENDPOINT_CSR(0) &= ~UDP_CSR_RX_PACKET_RECEIVED_BANK_0;\r
+ AT91C_BASE_UDP->UDP_CSR[0] &= ~AT91C_UDP_RX_DATA_BK0;\r
return;\r
}\r
- } while(!(UDP_ENDPOINT_CSR(0) & UDP_CSR_TX_PACKET_ACKED));\r
+ } while(!(AT91C_BASE_UDP->UDP_CSR[0] & AT91C_UDP_TXCOMP));\r
} while(len > 0);\r
\r
- if(UDP_ENDPOINT_CSR(0) & UDP_CSR_TX_PACKET_ACKED) {\r
- UDP_ENDPOINT_CSR(0) &= ~UDP_CSR_TX_PACKET_ACKED;\r
- while(UDP_ENDPOINT_CSR(0) & UDP_CSR_TX_PACKET_ACKED)\r
+ if(AT91C_BASE_UDP->UDP_CSR[0] & AT91C_UDP_TXCOMP) {\r
+ AT91C_BASE_UDP->UDP_CSR[0] &= ~AT91C_UDP_TXCOMP;\r
+ while(AT91C_BASE_UDP->UDP_CSR[0] & AT91C_UDP_TXCOMP)\r
;\r
}\r
}\r
\r
static void UsbSendZeroLength(void)\r
{\r
- UDP_ENDPOINT_CSR(0) |= UDP_CSR_TX_PACKET;\r
+ AT91C_BASE_UDP->UDP_CSR[0] |= AT91C_UDP_TXPKTRDY;\r
\r
- while(!(UDP_ENDPOINT_CSR(0) & UDP_CSR_TX_PACKET_ACKED))\r
+ while(!(AT91C_BASE_UDP->UDP_CSR[0] & AT91C_UDP_TXCOMP))\r
;\r
\r
- UDP_ENDPOINT_CSR(0) &= ~UDP_CSR_TX_PACKET_ACKED;\r
+ AT91C_BASE_UDP->UDP_CSR[0] &= ~AT91C_UDP_TXCOMP;\r
\r
- while(UDP_ENDPOINT_CSR(0) & UDP_CSR_TX_PACKET_ACKED)\r
+ while(AT91C_BASE_UDP->UDP_CSR[0] & AT91C_UDP_TXCOMP)\r
;\r
}\r
\r
static void UsbSendStall(void)\r
{\r
- UDP_ENDPOINT_CSR(0) |= UDP_CSR_FORCE_STALL;\r
+ AT91C_BASE_UDP->UDP_CSR[0] |= AT91C_UDP_FORCESTALL;\r
\r
- while(!(UDP_ENDPOINT_CSR(0) & UDP_CSR_STALL_SENT))\r
+ while(!(AT91C_BASE_UDP->UDP_CSR[0] & AT91C_UDP_STALLSENT))\r
;\r
\r
- UDP_ENDPOINT_CSR(0) &= ~UDP_CSR_STALL_SENT;\r
+ AT91C_BASE_UDP->UDP_CSR[0] &= ~AT91C_UDP_STALLSENT;\r
\r
- while(UDP_ENDPOINT_CSR(0) & UDP_CSR_STALL_SENT)\r
+ while(AT91C_BASE_UDP->UDP_CSR[0] & AT91C_UDP_STALLSENT)\r
;\r
}\r
\r
UsbSetupData usd;\r
\r
for(i = 0; i < sizeof(usd); i++) {\r
- ((BYTE *)&usd)[i] = UDP_ENDPOINT_FIFO(0);\r
+ ((BYTE *)&usd)[i] = AT91C_BASE_UDP->UDP_FDR[0];\r
}\r
\r
if(usd.bmRequestType & 0x80) {\r
- UDP_ENDPOINT_CSR(0) |= UDP_CSR_CONTROL_DATA_DIR;\r
- while(!(UDP_ENDPOINT_CSR(0) & UDP_CSR_CONTROL_DATA_DIR))\r
+ AT91C_BASE_UDP->UDP_CSR[0] |= AT91C_UDP_DIR;\r
+ while(!(AT91C_BASE_UDP->UDP_CSR[0] & AT91C_UDP_DIR))\r
;\r
}\r
\r
- UDP_ENDPOINT_CSR(0) &= ~UDP_CSR_RX_HAVE_READ_SETUP_DATA;\r
- while(UDP_ENDPOINT_CSR(0) & UDP_CSR_RX_HAVE_READ_SETUP_DATA)\r
+ AT91C_BASE_UDP->UDP_CSR[0] &= ~AT91C_UDP_RXSETUP;\r
+ while(AT91C_BASE_UDP->UDP_CSR[0] & AT91C_UDP_RXSETUP)\r
;\r
\r
switch(usd.bRequest) {\r
\r
case USB_REQUEST_SET_ADDRESS:\r
UsbSendZeroLength();\r
- UDP_FUNCTION_ADDR = UDP_FUNCTION_ADDR_ENABLED | usd.wValue ;\r
+ AT91C_BASE_UDP->UDP_FADDR = AT91C_UDP_FEN | usd.wValue ;\r
if(usd.wValue != 0) {\r
- UDP_GLOBAL_STATE = UDP_GLOBAL_STATE_ADDRESSED;\r
+ AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_FADDEN;\r
} else {\r
- UDP_GLOBAL_STATE = 0;\r
+ AT91C_BASE_UDP->UDP_GLBSTATE = 0;\r
}\r
break;\r
\r
case USB_REQUEST_SET_CONFIGURATION:\r
CurrentConfiguration = usd.wValue;\r
if(CurrentConfiguration) {\r
- UDP_GLOBAL_STATE = UDP_GLOBAL_STATE_CONFIGURED;\r
- UDP_ENDPOINT_CSR(1) = UDP_CSR_ENABLE_EP |\r
- UDP_CSR_EPTYPE_INTERRUPT_OUT;\r
- UDP_ENDPOINT_CSR(2) = UDP_CSR_ENABLE_EP |\r
- UDP_CSR_EPTYPE_INTERRUPT_IN;\r
+ AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_CONFG;\r
+ AT91C_BASE_UDP->UDP_CSR[1] = AT91C_UDP_EPEDS |\r
+ AT91C_UDP_EPTYPE_INT_OUT;\r
+ AT91C_BASE_UDP->UDP_CSR[2] = AT91C_UDP_EPEDS |\r
+ AT91C_UDP_EPTYPE_INT_IN;\r
} else {\r
- UDP_GLOBAL_STATE = UDP_GLOBAL_STATE_ADDRESSED;\r
- UDP_ENDPOINT_CSR(1) = 0;\r
- UDP_ENDPOINT_CSR(2) = 0;\r
+ AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_FADDEN;\r
+ AT91C_BASE_UDP->UDP_CSR[1] = 0;\r
+ AT91C_BASE_UDP->UDP_CSR[2] = 0;\r
}\r
UsbSendZeroLength();\r
break;\r
thisTime = min(len, 8);\r
\r
for(i = 0; i < thisTime; i++) {\r
- UDP_ENDPOINT_FIFO(2) = packet[i];\r
+ AT91C_BASE_UDP->UDP_FDR[2] = packet[i];\r
}\r
- UDP_ENDPOINT_CSR(2) |= UDP_CSR_TX_PACKET;\r
+ AT91C_BASE_UDP->UDP_CSR[2] |= AT91C_UDP_TXPKTRDY;\r
\r
- while(!(UDP_ENDPOINT_CSR(2) & UDP_CSR_TX_PACKET_ACKED))\r
+ while(!(AT91C_BASE_UDP->UDP_CSR[2] & AT91C_UDP_TXCOMP))\r
;\r
- UDP_ENDPOINT_CSR(2) &= ~UDP_CSR_TX_PACKET_ACKED;\r
+ AT91C_BASE_UDP->UDP_CSR[2] &= ~AT91C_UDP_TXCOMP;\r
\r
- while(UDP_ENDPOINT_CSR(2) & UDP_CSR_TX_PACKET_ACKED)\r
+ while(AT91C_BASE_UDP->UDP_CSR[2] & AT91C_UDP_TXCOMP)\r
;\r
\r
len -= thisTime;\r
{\r
int i, len;\r
\r
- if(UDP_ENDPOINT_CSR(1) & UDP_CSR_RX_PACKET_RECEIVED_BANK_0) {\r
- len = UDP_CSR_BYTES_RECEIVED(UDP_ENDPOINT_CSR(1));\r
+ if(AT91C_BASE_UDP->UDP_CSR[1] & AT91C_UDP_RX_DATA_BK0) {\r
+ len = UDP_CSR_BYTES_RECEIVED(AT91C_BASE_UDP->UDP_CSR[1]);\r
\r
for(i = 0; i < len; i++) {\r
- UsbBuffer[UsbSoFarCount] = UDP_ENDPOINT_FIFO(1);\r
+ UsbBuffer[UsbSoFarCount] = AT91C_BASE_UDP->UDP_FDR[1];\r
UsbSoFarCount++;\r
}\r
\r
- UDP_ENDPOINT_CSR(1) &= ~UDP_CSR_RX_PACKET_RECEIVED_BANK_0;\r
- while(UDP_ENDPOINT_CSR(1) & UDP_CSR_RX_PACKET_RECEIVED_BANK_0)\r
+ AT91C_BASE_UDP->UDP_CSR[1] &= ~AT91C_UDP_RX_DATA_BK0;\r
+ while(AT91C_BASE_UDP->UDP_CSR[1] & AT91C_UDP_RX_DATA_BK0)\r
;\r
\r
if(UsbSoFarCount >= 64) {\r
}\r
}\r
\r
- if(UDP_ENDPOINT_CSR(1) & UDP_CSR_RX_PACKET_RECEIVED_BANK_1) {\r
- len = UDP_CSR_BYTES_RECEIVED(UDP_ENDPOINT_CSR(1));\r
+ if(AT91C_BASE_UDP->UDP_CSR[1] & AT91C_UDP_RX_DATA_BK1) {\r
+ len = UDP_CSR_BYTES_RECEIVED(AT91C_BASE_UDP->UDP_CSR[1]);\r
\r
for(i = 0; i < len; i++) {\r
- UsbBuffer[UsbSoFarCount] = UDP_ENDPOINT_FIFO(1);\r
+ UsbBuffer[UsbSoFarCount] = AT91C_BASE_UDP->UDP_FDR[1];\r
UsbSoFarCount++;\r
}\r
\r
- UDP_ENDPOINT_CSR(1) &= ~UDP_CSR_RX_PACKET_RECEIVED_BANK_1;\r
- while(UDP_ENDPOINT_CSR(1) & UDP_CSR_RX_PACKET_RECEIVED_BANK_1)\r
+ AT91C_BASE_UDP->UDP_CSR[1] &= ~AT91C_UDP_RX_DATA_BK1;\r
+ while(AT91C_BASE_UDP->UDP_CSR[1] & AT91C_UDP_RX_DATA_BK1)\r
;\r
\r
if(UsbSoFarCount >= 64) {\r
\r
USB_D_PLUS_PULLUP_ON();\r
\r
- if(UDP_INTERRUPT_STATUS & UDP_INTERRUPT_END_OF_BUS_RESET) {\r
- UDP_INTERRUPT_CLEAR = UDP_INTERRUPT_END_OF_BUS_RESET;\r
+ if(AT91C_BASE_UDP->UDP_ISR & AT91C_UDP_ENDBUSRES) {\r
+ AT91C_BASE_UDP->UDP_ICR = AT91C_UDP_ENDBUSRES;\r
}\r
}\r
\r
BOOL UsbConnected()\r
{\r
- if (UDP_GLOBAL_STATE & UDP_GLOBAL_STATE_CONFIGURED)\r
+ if (AT91C_BASE_UDP->UDP_GLBSTATE & AT91C_UDP_CONFG)\r
return TRUE;\r
else\r
return FALSE;\r
{\r
BOOL ret = FALSE;\r
\r
- if(UDP_INTERRUPT_STATUS & UDP_INTERRUPT_END_OF_BUS_RESET) {\r
- UDP_INTERRUPT_CLEAR = UDP_INTERRUPT_END_OF_BUS_RESET;\r
+ if(AT91C_BASE_UDP->UDP_ISR & AT91C_UDP_ENDBUSRES) {\r
+ AT91C_BASE_UDP->UDP_ICR = AT91C_UDP_ENDBUSRES;\r
\r
// following a reset we should be ready to receive a setup packet\r
- UDP_RESET_ENDPOINT = 0xf;\r
- UDP_RESET_ENDPOINT = 0;\r
+ AT91C_BASE_UDP->UDP_RSTEP = 0xf;\r
+ AT91C_BASE_UDP->UDP_RSTEP = 0;\r
\r
- UDP_FUNCTION_ADDR = UDP_FUNCTION_ADDR_ENABLED;\r
+ AT91C_BASE_UDP->UDP_FADDR = AT91C_UDP_FEN;\r
\r
- UDP_ENDPOINT_CSR(0) = UDP_CSR_EPTYPE_CONTROL | UDP_CSR_ENABLE_EP;\r
+ AT91C_BASE_UDP->UDP_CSR[0] = AT91C_UDP_EPTYPE_CTRL | AT91C_UDP_EPEDS;\r
\r
CurrentConfiguration = 0;\r
\r
ret = TRUE;\r
}\r
\r
- if(UDP_INTERRUPT_STATUS & UDP_INTERRUPT_ENDPOINT(0)) {\r
- if(UDP_ENDPOINT_CSR(0) & UDP_CSR_RX_HAVE_READ_SETUP_DATA) {\r
+ if(AT91C_BASE_UDP->UDP_ISR & UDP_INTERRUPT_ENDPOINT(0)) {\r
+ if(AT91C_BASE_UDP->UDP_CSR[0] & AT91C_UDP_RXSETUP) {\r
HandleRxdSetupData();\r
ret = TRUE;\r
}\r
}\r
\r
- if(UDP_INTERRUPT_STATUS & UDP_INTERRUPT_ENDPOINT(1)) {\r
+ if(AT91C_BASE_UDP->UDP_ISR & UDP_INTERRUPT_ENDPOINT(1)) {\r
HandleRxdData();\r
ret = TRUE;\r
}\r
+++ /dev/null
-#include <at91sam7s512.h>\r
-\r
-#ifndef __AT91SAM7S128_H\r
-#define __AT91SAM7S128_H\r
-\r
-/***************************************************************\r
- * Start of translation between PM3 defines and AT91 defines\r
- * TODO these should be replaced throughout the code at some stage\r
- ***************************************************************/\r
-#define PERIPH_PIOA AT91C_ID_PIOA\r
-#define PERIPH_ADC AT91C_ID_ADC\r
-#define PERIPH_SPI AT91C_ID_SPI\r
-#define PERIPH_SSC AT91C_ID_SSC\r
-#define PERIPH_PWMC AT91C_ID_PWMC\r
-#define PERIPH_UDP AT91C_ID_UDP\r
-#define PERIPH_TC1 AT91C_ID_TC1\r
-\r
-#define SSC_BASE AT91C_BASE_SSC\r
-\r
-#define WDT_CONTROL AT91C_BASE_WDTC->WDTC_WDCR\r
-\r
-#define PWM_ENABLE AT91C_BASE_PWMC->PWMC_ENA\r
-\r
-// TODO WARNING these PWM defines MUST be replaced in the code ASAP before\r
-// someone starts using a value of x other than that selected below\r
-#define PWM_CH_PERIOD(x) AT91C_BASE_PWMC_CH0->PWMC_CPRDR\r
-#define PWM_CH_COUNTER(x) AT91C_BASE_PWMC_CH0->PWMC_CCNTR\r
-#define PWM_CH_MODE(x) AT91C_BASE_PWMC_CH0->PWMC_CMR\r
-#define PWM_CH_DUTY_CYCLE(x) AT91C_BASE_PWMC_CH0->PWMC_CDTYR\r
-\r
-#define PDC_RX_POINTER(x) AT91C_BASE_PDC_SSC->PDC_RPR\r
-#define PDC_RX_COUNTER(x) AT91C_BASE_PDC_SSC->PDC_RCR\r
-#define PDC_RX_NEXT_POINTER(x) AT91C_BASE_PDC_SSC->PDC_RNPR\r
-#define PDC_RX_NEXT_COUNTER(x) AT91C_BASE_PDC_SSC->PDC_RNCR\r
-#define PDC_CONTROL(x) AT91C_BASE_PDC_SSC->PDC_PTCR\r
-// End WARNING\r
-\r
-#define DBGU_CIDR AT91C_BASE_DBGU->DBGU_CIDR\r
-\r
-#define RSTC_CONTROL AT91C_BASE_RSTC->RSTC_RCR\r
-#define RSTC_STATUS AT91C_BASE_RSTC->RSTC_RSR\r
-\r
-#define MC_FLASH_COMMAND AT91C_BASE_EFC0->EFC_FCR\r
-#define MC_FLASH_MODE0 AT91C_BASE_EFC0->EFC_FMR\r
-#define MC_FLASH_MODE1 AT91C_BASE_EFC1->EFC_FMR\r
-#define MC_FLASH_STATUS AT91C_BASE_EFC0->EFC_FSR\r
-\r
-#define ADC_CONTROL AT91C_BASE_ADC->ADC_CR\r
-#define ADC_MODE AT91C_BASE_ADC->ADC_MR\r
-#define ADC_CHANNEL_ENABLE AT91C_BASE_ADC->ADC_CHER\r
-#define ADC_STATUS AT91C_BASE_ADC->ADC_SR\r
-#define ADC_CHANNEL_DATA(x) AT91C_BASE_ADC->ADC_CDR[x]\r
-\r
-#define PIO_ENABLE AT91C_BASE_PIOA->PIO_PER\r
-#define PIO_DISABLE AT91C_BASE_PIOA->PIO_PDR\r
-#define PIO_OUTPUT_ENABLE AT91C_BASE_PIOA->PIO_OER\r
-#define PIO_OUTPUT_DISABLE AT91C_BASE_PIOA->PIO_ODR\r
-#define PIO_OUTPUT_DATA_SET AT91C_BASE_PIOA->PIO_SODR\r
-#define PIO_OUTPUT_DATA_CLEAR AT91C_BASE_PIOA->PIO_CODR\r
-#define PIO_PIN_DATA_STATUS AT91C_BASE_PIOA->PIO_PDSR\r
-#define PIO_NO_PULL_UP_ENABLE AT91C_BASE_PIOA->PIO_PPUDR\r
-#define PIO_NO_PULL_UP_DISABLE AT91C_BASE_PIOA->PIO_PPUER\r
-#define PIO_PERIPHERAL_B_SEL AT91C_BASE_PIOA->PIO_BSR\r
-#define PIO_PERIPHERAL_A_SEL AT91C_BASE_PIOA->PIO_ASR\r
-\r
-#define PMC_SYS_CLK_ENABLE AT91C_BASE_PMC->PMC_SCER\r
-#define PMC_PERIPHERAL_CLK_ENABLE AT91C_BASE_PMC->PMC_PCER\r
-#define PMC_MAIN_OSCILLATOR AT91C_BASE_PMC->PMC_MOR\r
-#define PMC_PLL AT91C_BASE_PMC->PMC_PLLR\r
-#define PMC_MASTER_CLK AT91C_BASE_PMC->PMC_MCKR\r
-#define PMC_PROGRAMMABLE_CLK_0 AT91C_BASE_PMC->PMC_PCKR[0]\r
-#define PMC_INTERRUPT_STATUS AT91C_BASE_PMC->PMC_SR\r
-\r
-#define SSC_CONTROL AT91C_BASE_SSC->SSC_CR\r
-#define SSC_CLOCK_DIVISOR AT91C_BASE_SSC->SSC_CMR\r
-#define SSC_RECEIVE_CLOCK_MODE AT91C_BASE_SSC->SSC_RCMR\r
-#define SSC_RECEIVE_FRAME_MODE AT91C_BASE_SSC->SSC_RFMR\r
-#define SSC_TRANSMIT_CLOCK_MODE AT91C_BASE_SSC->SSC_TCMR\r
-#define SSC_TRANSMIT_FRAME_MODE AT91C_BASE_SSC->SSC_TFMR\r
-#define SSC_RECEIVE_HOLDING AT91C_BASE_SSC->SSC_RHR\r
-#define SSC_TRANSMIT_HOLDING AT91C_BASE_SSC->SSC_THR\r
-#define SSC_STATUS AT91C_BASE_SSC->SSC_SR\r
-\r
-#define SPI_CONTROL AT91C_BASE_SPI->SPI_CR\r
-#define SPI_MODE AT91C_BASE_SPI->SPI_MR\r
-#define SPI_TX_DATA AT91C_BASE_SPI->SPI_TDR\r
-#define SPI_STATUS AT91C_BASE_SPI->SPI_SR\r
-#define SPI_FOR_CHIPSEL_0 AT91C_BASE_SPI->SPI_CSR[0]\r
-#define SPI_FOR_CHIPSEL_1 AT91C_BASE_SPI->SPI_CSR[1]\r
-#define SPI_FOR_CHIPSEL_2 AT91C_BASE_SPI->SPI_CSR[2]\r
-#define SPI_FOR_CHIPSEL_3 AT91C_BASE_SPI->SPI_CSR[3]\r
-\r
-#define TC1_CCR AT91C_BASE_TC1->TC_CCR\r
-#define TC1_CMR AT91C_BASE_TC1->TC_CMR\r
-#define TC1_CV AT91C_BASE_TC1->TC_CV\r
-#define TC1_RA AT91C_BASE_TC1->TC_RA\r
-#define TC1_SR AT91C_BASE_TC1->TC_SR\r
-\r
-#define PDC_RX_ENABLE AT91C_PDC_RXTEN\r
-#define PDC_RX_DISABLE AT91C_PDC_RXTDIS\r
-\r
-#define TC_CMR_ETRGEDG_RISING AT91C_TC_ETRGEDG_RISING\r
-#define TC_CMR_ABETRG AT91C_TC_ABETRG\r
-#define TC_CMR_LDRA_RISING AT91C_TC_LDRA_RISING\r
-#define TC_CMR_LDRB_RISING AT91C_TC_LDRB_RISING\r
-#define TC_CCR_CLKEN AT91C_TC_CLKEN\r
-#define TC_CCR_SWTRG AT91C_TC_SWTRG\r
-#define TC_SR_LDRAS AT91C_TC_LDRAS\r
-#define TC_CMR_ETRGEDG AT91C_TC_ETRGEDG\r
-#define TC_CCR_CLKDIS AT91C_TC_CLKDIS\r
-\r
-#define ADC_CONTROL_RESET AT91C_ADC_SWRST\r
-#define ADC_CONTROL_START AT91C_ADC_START\r
-\r
-#define SPI_CONTROL_ENABLE AT91C_SPI_SPIEN\r
-#define SPI_CONTROL_LAST_TRANSFER AT91C_SPI_LASTXFER\r
-#define SPI_CONTROL_RESET AT91C_SPI_SWRST\r
-#define SPI_CONTROL_DISABLE AT91C_SPI_SPIDIS\r
-#define SPI_STATUS_TX_EMPTY AT91C_SPI_TXEMPTY\r
-\r
-#define SSC_CONTROL_RX_ENABLE AT91C_SSC_RXEN\r
-#define SSC_CONTROL_TX_ENABLE AT91C_SSC_TXEN\r
-#define SSC_FRAME_MODE_MSB_FIRST AT91C_SSC_MSBF\r
-#define SSC_CONTROL_RESET AT91C_SSC_SWRST\r
-#define SSC_STATUS_TX_READY AT91C_SSC_TXRDY\r
-#define SSC_STATUS_RX_READY AT91C_SSC_RXRDY\r
-\r
-#define FCMD_WRITE_PAGE AT91C_MC_FCMD_START_PROG\r
-#define FLASH_PAGE_SIZE_BYTES AT91C_IFLASH_PAGE_SIZE\r
-\r
-#define RST_CONTROL_PROCESSOR_RESET AT91C_RSTC_PROCRST\r
-#define RST_STATUS_TYPE_MASK AT91C_RSTC_RSTTYP\r
-#define RST_STATUS_TYPE_WATCHDOG AT91C_RSTC_RSTTYP_WATCHDOG\r
-#define RST_STATUS_TYPE_SOFTWARE AT91C_RSTC_RSTTYP_SOFTWARE\r
-#define RST_STATUS_TYPE_USER AT91C_RSTC_RSTTYP_USER\r
-\r
-#define PMC_SYS_CLK_PROCESSOR_CLK AT91C_PMC_PCK\r
-#define PMC_SYS_CLK_UDP_CLK AT91C_PMC_UDP\r
-#define PMC_CLK_SELECTION_PLL_CLOCK AT91C_PMC_CSS_PLL_CLK\r
-#define PMC_CLK_PRESCALE_DIV_4 AT91C_PMC_PRES_CLK_4\r
-#define PMC_SYS_CLK_PROGRAMMABLE_CLK_0 AT91C_PMC_PCK0\r
-\r
-#define UDP_INTERRUPT_STATUS AT91C_BASE_UDP->UDP_ISR\r
-#define UDP_INTERRUPT_CLEAR AT91C_BASE_UDP->UDP_ICR\r
-#define UDP_FUNCTION_ADDR AT91C_BASE_UDP->UDP_FADDR\r
-#define UDP_RESET_ENDPOINT AT91C_BASE_UDP->UDP_RSTEP\r
-#define UDP_GLOBAL_STATE AT91C_BASE_UDP->UDP_GLBSTATE\r
-#define UDP_ENDPOINT_CSR(x) AT91C_BASE_UDP->UDP_CSR[x]\r
-#define UDP_ENDPOINT_FIFO(x) AT91C_BASE_UDP->UDP_FDR[x]\r
-\r
-#define UDP_CSR_CONTROL_DATA_DIR AT91C_UDP_DIR\r
-#define UDP_CSR_ENABLE_EP AT91C_UDP_EPEDS\r
-#define UDP_CSR_EPTYPE_CONTROL AT91C_UDP_EPTYPE_CTRL\r
-#define UDP_CSR_EPTYPE_INTERRUPT_IN AT91C_UDP_EPTYPE_INT_IN\r
-#define UDP_CSR_EPTYPE_INTERRUPT_OUT AT91C_UDP_EPTYPE_INT_OUT\r
-#define UDP_CSR_FORCE_STALL AT91C_UDP_FORCESTALL\r
-#define UDP_CSR_RX_HAVE_READ_SETUP_DATA AT91C_UDP_RXSETUP\r
-#define UDP_CSR_RX_PACKET_RECEIVED_BANK_0 AT91C_UDP_RX_DATA_BK0\r
-#define UDP_CSR_RX_PACKET_RECEIVED_BANK_1 AT91C_UDP_RX_DATA_BK1\r
-#define UDP_CSR_STALL_SENT AT91C_UDP_STALLSENT\r
-#define UDP_CSR_TX_PACKET AT91C_UDP_TXPKTRDY\r
-#define UDP_CSR_TX_PACKET_ACKED AT91C_UDP_TXCOMP\r
-\r
-#define UDP_FUNCTION_ADDR_ENABLED AT91C_UDP_FEN\r
-#define UDP_GLOBAL_STATE_ADDRESSED AT91C_UDP_FADDEN\r
-#define UDP_GLOBAL_STATE_CONFIGURED AT91C_UDP_CONFG\r
-#define UDP_INTERRUPT_END_OF_BUS_RESET AT91C_UDP_ENDBUSRES\r
-/***************************************************************\r
- * end of translation between PM3 defines and AT91 defines\r
- ***************************************************************/\r
-\r
-/***************************************************************\r
- * the defines below this line have no AT91 equivalents and can\r
- * be ideally moved to proxmark3.h\r
- ***************************************************************/\r
-#define WDT_HIT() WDT_CONTROL = 0xa5000001\r
-\r
-#define PWM_CH_MODE_PRESCALER(x) ((x)<<0)\r
-#define PWM_CHANNEL(x) (1<<(x))\r
-\r
-#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0<<0)\r
-\r
-#define ADC_CHAN_LF 4\r
-#define ADC_CHAN_HF 5\r
-#define ADC_MODE_PRESCALE(x) ((x)<<8)\r
-#define ADC_MODE_STARTUP_TIME(x) ((x)<<16)\r
-#define ADC_MODE_SAMPLE_HOLD_TIME(x) ((x)<<24)\r
-#define ADC_CHANNEL(x) (1<<(x))\r
-#define ADC_END_OF_CONVERSION(x) (1<<(x))\r
-\r
-#define SSC_CLOCK_MODE_START(x) ((x)<<8)\r
-#define SSC_FRAME_MODE_WORDS_PER_TRANSFER(x) ((x)<<8)\r
-#define SSC_CLOCK_MODE_SELECT(x) ((x)<<0)\r
-#define SSC_FRAME_MODE_BITS_IN_WORD(x) (((x)-1)<<0)\r
-\r
-#define MC_FLASH_COMMAND_KEY ((0x5A)<<24)\r
-#define MC_FLASH_STATUS_READY (1<<0)\r
-#define MC_FLASH_MODE_FLASH_WAIT_STATES(x) ((x)<<8)\r
-#define MC_FLASH_MODE_MASTER_CLK_IN_MHZ(x) ((x)<<16)\r
-#define MC_FLASH_COMMAND_PAGEN(x) ((x)<<8)\r
-\r
-#define RST_CONTROL_KEY (0xA5<<24)\r
-\r
-#define PMC_MAIN_OSCILLATOR_ENABLE (1<<0)\r
-#define PMC_MAIN_OSCILLATOR_STABILIZED (1<<0)\r
-#define PMC_MAIN_OSCILLATOR_PLL_LOCK (1<<2)\r
-#define PMC_MAIN_OSCILLATOR_MCK_READY (1<<3)\r
-\r
-#define PMC_PLL_DIVISOR(x) (x)\r
-#define PMC_MAIN_OSCILLATOR_STARTUP_DELAY(x) ((x)<<8)\r
-#define PMC_CLK_PRESCALE_DIV_2 (1<<2)\r
-#define PMC_PLL_MULTIPLIER(x) (((x)-1)<<16)\r
-#define PMC_PLL_COUNT_BEFORE_LOCK(x) ((x)<<8)\r
-#define PMC_PLL_FREQUENCY_RANGE(x) ((x)<<14)\r
-#define PMC_PLL_USB_DIVISOR(x) ((x)<<28)\r
-\r
-#define UDP_INTERRUPT_ENDPOINT(x) (1<<(x))\r
-#define UDP_CSR_BYTES_RECEIVED(x) (((x) >> 16) & 0x7ff)\r
-\r
-#endif\r
#ifndef __CONFIG_GPIO_H\r
#define __CONFIG_GPIO_H\r
\r
-#define GPIO_LED_A 0\r
-#define GPIO_PA1 1\r
-#define GPIO_LED_D 2\r
-#define GPIO_NVDD_ON 3\r
-#define GPIO_FPGA_NINIT 4\r
-#define GPIO_PA5 5\r
-#define GPIO_PCK0 6\r
-#define GPIO_LRST 7\r
-#define GPIO_LED_B 8\r
-#define GPIO_LED_C 9\r
-#define GPIO_NCS2 10\r
-#define GPIO_NCS0 11\r
-#define GPIO_MISO 12\r
-#define GPIO_MOSI 13\r
-#define GPIO_SPCK 14\r
-#define GPIO_SSC_FRAME 15\r
-#define GPIO_SSC_CLK 16\r
-#define GPIO_SSC_DOUT 17\r
-#define GPIO_SSC_DIN 18\r
-#define GPIO_MUXSEL_HIPKD 19\r
-#define GPIO_MUXSEL_LOPKD 20\r
-#define GPIO_MUXSEL_HIRAW 21\r
-#define GPIO_MUXSEL_LORAW 22\r
-#define GPIO_BUTTON 23\r
-#define GPIO_USB_PU 24\r
-#define GPIO_RELAY 25\r
-#define GPIO_FPGA_ON 26\r
-#define GPIO_FPGA_DONE 27\r
-#define GPIO_FPGA_NPROGRAM 28\r
-#define GPIO_FPGA_CCLK 29\r
-#define GPIO_FPGA_DIN 30\r
-#define GPIO_FPGA_DOUT 31\r
-\r
-#define ANIN_AMPL_LO 4\r
-#define ANIN_AMPL_HI 5\r
+#define GPIO_LED_A AT91C_PIO_PA0\r
+#define GPIO_PA1 AT91C_PIO_PA1\r
+#define GPIO_LED_D AT91C_PIO_PA2\r
+#define GPIO_NVDD_ON AT91C_PIO_PA3\r
+#define GPIO_FPGA_NINIT AT91C_PIO_PA4\r
+#define GPIO_PA5 AT91C_PIO_PA5\r
+#define GPIO_PCK0 AT91C_PA6_PCK0\r
+#define GPIO_LRST AT91C_PIO_PA7\r
+#define GPIO_LED_B AT91C_PIO_PA8\r
+#define GPIO_LED_C AT91C_PIO_PA9\r
+#define GPIO_NCS2 AT91C_PA10_NPCS2\r
+#define GPIO_NCS0 AT91C_PA11_NPCS0\r
+#define GPIO_MISO AT91C_PA12_MISO\r
+#define GPIO_MOSI AT91C_PA13_MOSI\r
+#define GPIO_SPCK AT91C_PA14_SPCK\r
+#define GPIO_SSC_FRAME AT91C_PA15_TF\r
+#define GPIO_SSC_CLK AT91C_PA16_TK\r
+#define GPIO_SSC_DOUT AT91C_PA17_TD\r
+#define GPIO_SSC_DIN AT91C_PA18_RD\r
+#define GPIO_MUXSEL_HIPKD AT91C_PIO_PA19\r
+#define GPIO_MUXSEL_LOPKD AT91C_PIO_PA20\r
+#define GPIO_MUXSEL_HIRAW AT91C_PIO_PA21\r
+#define GPIO_MUXSEL_LORAW AT91C_PIO_PA22\r
+#define GPIO_BUTTON AT91C_PIO_PA23\r
+#define GPIO_USB_PU AT91C_PIO_PA24\r
+#define GPIO_RELAY AT91C_PIO_PA25\r
+#define GPIO_FPGA_ON AT91C_PIO_PA26\r
+#define GPIO_FPGA_DONE AT91C_PIO_PA27\r
+#define GPIO_FPGA_NPROGRAM AT91C_PIO_PA28\r
+#define GPIO_FPGA_CCLK AT91C_PIO_PA29\r
+#define GPIO_FPGA_DIN AT91C_PIO_PA30\r
+#define GPIO_FPGA_DOUT AT91C_PIO_PA31\r
\r
#endif\r
#define __PROXMARK3_H\r
\r
// Might as well have the hardware-specific defines everywhere.\r
-#include <at91sam7s128.h>\r
-\r
+#include <at91sam7s512.h>\r
#include <config_gpio.h>\r
-#define LOW(x) PIO_OUTPUT_DATA_CLEAR = (1 << (x))\r
-#define HIGH(x) PIO_OUTPUT_DATA_SET = (1 << (x))\r
+\r
+#define WDT_HIT() AT91C_BASE_WDTC->WDTC_WDCR = 0xa5000001\r
+\r
+#define PWM_CH_MODE_PRESCALER(x) ((x)<<0)\r
+#define PWM_CHANNEL(x) (1<<(x))\r
+\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0<<0)\r
+\r
+#define ADC_CHAN_LF 4\r
+#define ADC_CHAN_HF 5\r
+#define ADC_MODE_PRESCALE(x) ((x)<<8)\r
+#define ADC_MODE_STARTUP_TIME(x) ((x)<<16)\r
+#define ADC_MODE_SAMPLE_HOLD_TIME(x) ((x)<<24)\r
+#define ADC_CHANNEL(x) (1<<(x))\r
+#define ADC_END_OF_CONVERSION(x) (1<<(x))\r
+\r
+#define SSC_CLOCK_MODE_START(x) ((x)<<8)\r
+#define SSC_FRAME_MODE_WORDS_PER_TRANSFER(x) ((x)<<8)\r
+#define SSC_CLOCK_MODE_SELECT(x) ((x)<<0)\r
+#define SSC_FRAME_MODE_BITS_IN_WORD(x) (((x)-1)<<0)\r
+\r
+#define MC_FLASH_COMMAND_KEY ((0x5a)<<24)\r
+#define MC_FLASH_STATUS_READY (1<<0)\r
+#define MC_FLASH_MODE_FLASH_WAIT_STATES(x) ((x)<<8)\r
+#define MC_FLASH_MODE_MASTER_CLK_IN_MHZ(x) ((x)<<16)\r
+#define MC_FLASH_COMMAND_PAGEN(x) ((x)<<8)\r
+\r
+#define RST_CONTROL_KEY (0xa5<<24)\r
+\r
+#define PMC_MAIN_OSC_ENABLE (1<<0)\r
+#define PMC_MAIN_OSC_STABILIZED (1<<0)\r
+#define PMC_MAIN_OSC_PLL_LOCK (1<<2)\r
+#define PMC_MAIN_OSC_MCK_READY (1<<3)\r
+\r
+#define PMC_MAIN_OSC_STARTUP_DELAY(x) ((x)<<8)\r
+#define PMC_PLL_DIVISOR(x) (x)\r
+#define PMC_CLK_PRESCALE_DIV_2 (1<<2)\r
+#define PMC_PLL_MULTIPLIER(x) (((x)-1)<<16)\r
+#define PMC_PLL_COUNT_BEFORE_LOCK(x) ((x)<<8)\r
+#define PMC_PLL_FREQUENCY_RANGE(x) ((x)<<14)\r
+#define PMC_PLL_USB_DIVISOR(x) ((x)<<28)\r
+\r
+#define UDP_INTERRUPT_ENDPOINT(x) (1<<(x))\r
+#define UDP_CSR_BYTES_RECEIVED(x) (((x) >> 16) & 0x7ff)\r
+//**************************************************************\r
+\r
+#define LOW(x) AT91C_BASE_PIOA->PIO_CODR = (x)\r
+#define HIGH(x) AT91C_BASE_PIOA->PIO_SODR = (x)\r
\r
#define SPI_FPGA_MODE 0\r
#define SPI_LCD_MODE 1\r
#define PACKED __attribute__((__packed__))\r
\r
#define USB_D_PLUS_PULLUP_ON() { \\r
- PIO_OUTPUT_DATA_SET = (1<<GPIO_USB_PU); \\r
- PIO_OUTPUT_ENABLE = (1<<GPIO_USB_PU); \\r
+ HIGH(GPIO_USB_PU); \\r
+ AT91C_BASE_PIOA->PIO_OER = GPIO_USB_PU; \\r
}\r
-#define USB_D_PLUS_PULLUP_OFF() PIO_OUTPUT_DISABLE = (1<<GPIO_USB_PU)\r
-\r
-#define LED_A_ON() PIO_OUTPUT_DATA_SET = (1<<GPIO_LED_A)\r
-#define LED_A_OFF() PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_LED_A)\r
-#define LED_B_ON() PIO_OUTPUT_DATA_SET = (1<<GPIO_LED_B)\r
-#define LED_B_OFF() PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_LED_B)\r
-#define LED_C_ON() PIO_OUTPUT_DATA_SET = (1<<GPIO_LED_C)\r
-#define LED_C_OFF() PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_LED_C)\r
-#define LED_D_ON() PIO_OUTPUT_DATA_SET = (1<<GPIO_LED_D)\r
-#define LED_D_OFF() PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_LED_D)\r
-#define RELAY_ON() PIO_OUTPUT_DATA_SET = (1<<GPIO_RELAY)\r
-#define RELAY_OFF() PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_RELAY)\r
-#define BUTTON_PRESS() !(PIO_PIN_DATA_STATUS & (1<<GPIO_BUTTON))\r
+#define USB_D_PLUS_PULLUP_OFF() AT91C_BASE_PIOA->PIO_ODR = GPIO_USB_PU\r
+\r
+#define LED_A_ON() HIGH(GPIO_LED_A)\r
+#define LED_A_OFF() LOW(GPIO_LED_A)\r
+#define LED_B_ON() HIGH(GPIO_LED_B)\r
+#define LED_B_OFF() LOW(GPIO_LED_B)\r
+#define LED_C_ON() HIGH(GPIO_LED_C)\r
+#define LED_C_OFF() LOW(GPIO_LED_C)\r
+#define LED_D_ON() HIGH(GPIO_LED_D)\r
+#define LED_D_OFF() LOW(GPIO_LED_D)\r
+#define RELAY_ON() HIGH(GPIO_RELAY)\r
+#define RELAY_OFF() LOW(GPIO_RELAY)\r
+#define BUTTON_PRESS() !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_BUTTON)\r
//--------------------------------\r
// USB declarations\r
\r
\r
#define VERSION_INFORMATION_MAGIC 0x56334d50\r
struct version_information {\r
- int magic; /* Magic sequence to identify this as a correct version information structure. Must be VERSION_INFORMATION_MAGIC */ \r
+ int magic; /* Magic sequence to identify this as a correct version information structure. Must be VERSION_INFORMATION_MAGIC */\r
char versionversion; /* Must be 1 */\r
char present; /* 1 if the version information could be created at compile time, otherwise 0 and the remaining fields (except for magic) are empty */\r
char clean; /* 1: Tree was clean, no local changes. 0: Tree was unclean. 2: Couldn't be determined */\r
projects / proxmark3-svn / commitdiff