fix: (issue #72) LF simulation didn't work with lo_edge_detect.v

diff --git a/fpga/fpga_lf.bit b/fpga/fpga_lf.bit
index 51b0681cd6a082550a19dccd794ff40439e393f9..bd4d821bbd7db5d6ff01190fc2204e259e467c50 100644 (file)
Binary files a/fpga/fpga_lf.bit and b/fpga/fpga_lf.bit differ

diff --git a/fpga/lo_edge_detect.v b/fpga/lo_edge_detect.v
index dc97fc6f53ce419dd957536955bc0e0e2a5257a0..bb13015743b09e5c0cba5d4e69a309be2ab7fc34 100644 (file)
--- a/fpga/lo_edge_detect.v
+++ b/fpga/lo_edge_detect.v
@@ -35,10 +35,12 @@ wire tag_modulation = ssp_dout & !lf_field;
 wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
 
 // No logic, straight through.
 wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
 
 // No logic, straight through.

-assign pwr_oe1 = 1'b0; // not used in LF mode
+assign pwr_oe1 = 1'b0;                                                 // not used in LF mode 
+assign pwr_oe3 = 1'b0;                                                 // base antenna load = 33 Ohms
+// when modulating, add another 33 Ohms and 10k Ohms in parallel:

 assign pwr_oe2 = tag_modulation;
 assign pwr_oe2 = tag_modulation;

-assign pwr_oe3 = tag_modulation;
-assign pwr_oe4 = tag_modulation;
+assign pwr_oe4 = tag_modulation; 
+

 assign ssp_clk = cross_lo;
 assign pwr_lo = reader_modulation;
 assign pwr_hi = 1'b0;
 assign ssp_clk = cross_lo;
 assign pwr_lo = reader_modulation;
 assign pwr_hi = 1'b0;