corrected Eagle files

check change_log.txt

diff --git a/pcb/proxmark3_fix/BOT_layer_preview.png b/pcb/proxmark3_fix/BOT_layer_preview.png
new file mode 100644 (file)
index 0000000..a124ccf
Binary files /dev/null and b/pcb/proxmark3_fix/BOT_layer_preview.png differ

diff --git a/pcb/proxmark3_fix/CAD/change_log.txt b/pcb/proxmark3_fix/CAD/change_log.txt
new file mode 100644 (file)
index 0000000..6ee7a49
--- /dev/null
+++ b/pcb/proxmark3_fix/CAD/change_log.txt
@@ -0,0 +1,14 @@
+13/11/2015 Change list from original PCB:
+
+Main problem: more then 800 DRC errors when runing that in Eagle. Check out the following changes to make a more reliable PCB. Those are minor cosmetic changes, but ease your life to avoid short circuit.
+
+1. Eagle Layout / DRC rules / Masks / Limit: from 0mil to 16mil, thus ordinary GND and signal vias which smaller then 16mil wont be open at solder stop mask layer.
+
+2. Eagle Layout / DRC rules / Masks / Stop MAX: from 2mil to 0, this way the solder stop mask wont overlap silkscreen drawings. Also as per PCB assembly houses, it's recommended, they set their own scaling for production.
+
+3. Exporting all the parts in the proxmark3 Eagle Layout into a library for minor silkscreen edition: proxmark3_components  merged.lbr
+       - Editing components footprint as was overlapping with top stop mask
+
+4. Adding top, bottom, in1, in2 layer markings in PCB layout for better manufacturing identification   
+
+5. Generating 4 layer CAM files

diff --git a/pcb/proxmark3_fix/CAD/proxmark3.brd b/pcb/proxmark3_fix/CAD/proxmark3.brd
new file mode 100644 (file)
index 0000000..d7634eb
--- /dev/null
+++ b/pcb/proxmark3_fix/CAD/proxmark3.brd
@@ -0,0 +1,4640 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="6.4">
+<drawing>
+<settings>
+<setting alwaysvectorfont="yes"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="100" unitdist="mil" unit="mil" style="lines" multiple="1" display="no" altdistance="1" altunitdist="mil" altunit="mil"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="2" name="Route2" color="3" fill="6" visible="yes" active="yes"/>
+<layer number="3" name="Route3" color="4" fill="3" visible="no" active="yes"/>
+<layer number="4" name="Route4" color="1" fill="4" visible="no" active="yes"/>
+<layer number="5" name="Route5" color="4" fill="4" visible="no" active="yes"/>
+<layer number="6" name="Route6" color="1" fill="8" visible="no" active="yes"/>
+<layer number="7" name="Route7" color="4" fill="8" visible="no" active="yes"/>
+<layer number="8" name="Route8" color="1" fill="2" visible="no" active="yes"/>
+<layer number="9" name="Route9" color="4" fill="2" visible="no" active="yes"/>
+<layer number="10" name="Route10" color="1" fill="7" visible="no" active="yes"/>
+<layer number="11" name="Route11" color="4" fill="7" visible="no" active="yes"/>
+<layer number="12" name="Route12" color="1" fill="5" visible="no" active="yes"/>
+<layer number="13" name="Route13" color="4" fill="5" visible="no" active="yes"/>
+<layer number="14" name="Route14" color="1" fill="6" visible="no" active="yes"/>
+<layer number="15" name="Route15" color="5" fill="3" visible="yes" active="yes"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="yes"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="yes"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="no" active="yes"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="no" active="yes"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="no" active="yes"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
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+<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="yes"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="yes"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="yes"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="yes"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
+<layer number="48" name="Document" color="7" fill="1" visible="no" active="yes"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="no" active="yes"/>
+<layer number="51" name="tDocu" color="8" fill="1" visible="no" active="yes"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="yes"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="no" active="no"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="no" active="no"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="no"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="no" active="no"/>
+<layer number="95" name="Names" color="7" fill="1" visible="no" active="no"/>
+<layer number="96" name="Values" color="7" fill="1" visible="no" active="no"/>
+<layer number="97" name="Info" color="7" fill="1" visible="no" active="no"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="no" active="no"/>
+<layer number="101" name="LcdOutline" color="7" fill="1" visible="no" active="yes"/>
+<layer number="250" name="Descript" color="7" fill="1" visible="no" active="yes"/>
+<layer number="251" name="SMDround" color="7" fill="1" visible="no" active="yes"/>
+</layers>
+<board>
+<plain>
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+<text x="79.502" y="1.651" size="1.27" layer="16" ratio="17" rot="MR0">proxmark3</text>
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+<text x="12.7" y="48.641" size="1.27" layer="30" ratio="17" rot="MR0">J. Westhues</text>
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+<text x="88.9" y="53.34" size="1.778" layer="15" font="vector" ratio="15">IN2</text>
+</plain>
+<libraries>
+<library name="  merged">
+<packages>
+<package name="VQFP-100">
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+<wire x1="-1.3398" y1="0.4776" x2="-1.3398" y2="-0.4224" width="0.127" layer="21"/>
+<smd name="1" x="-0.9398" y="-1.4224" dx="0.4" dy="1.5" layer="1"/>
+<smd name="2" x="0.0102" y="-1.4224" dx="0.4" dy="1.5" layer="1"/>
+<smd name="3" x="0.9602" y="-1.4224" dx="0.4" dy="1.5" layer="1"/>
+<smd name="4" x="0.9602" y="1.4276" dx="0.4" dy="1.5" layer="1"/>
+<smd name="5" x="-0.9398" y="1.4276" dx="0.4" dy="1.5" layer="1"/>
+<text x="1.4602" y="2.1776" size="1.27" layer="21" font="vector" rot="R270">&gt;NAME</text>
+</package>
+<package name="--MERGED_HEADER-MALE-6X1-0.100-UNKEYED">
+<wire x1="-1.17" y1="7.62" x2="1.17" y2="7.62" width="0.254" layer="21"/>
+<wire x1="1.17" y1="7.62" x2="1.17" y2="-7.62" width="0.254" layer="21"/>
+<wire x1="1.17" y1="-7.62" x2="-1.17" y2="-7.62" width="0.254" layer="21"/>
+<wire x1="-1.17" y1="-7.62" x2="-1.17" y2="7.62" width="0.254" layer="21"/>
+<pad name="1" x="0" y="6.35" drill="1.143" shape="square"/>
+<pad name="2" x="0" y="3.81" drill="1.143"/>
+<pad name="3" x="0" y="1.27" drill="1.143"/>
+<pad name="4" x="0" y="-1.27" drill="1.143"/>
+<pad name="5" x="0" y="-3.81" drill="1.143"/>
+<pad name="6" x="0" y="-6.35" drill="1.143"/>
+<text x="1.905" y="6.985" size="1.27" layer="21" ratio="22" rot="R270">&gt;NAME</text>
+</package>
+<package name="--MERGED_RLC_0603">
+<wire x1="-1.4732" y1="0.6858" x2="1.4732" y2="0.6858" width="0.15" layer="21"/>
+<wire x1="1.4732" y1="0.6858" x2="1.4732" y2="-0.6858" width="0.15" layer="21"/>
+<wire x1="1.4732" y1="-0.6858" x2="-1.4732" y2="-0.6858" width="0.15" layer="21"/>
+<wire x1="-1.4732" y1="-0.6858" x2="-1.4732" y2="0.6858" width="0.15" layer="21"/>
+<smd name="1" x="-0.85" y="0" dx="1" dy="1.1" layer="1"/>
+<smd name="2" x="0.85" y="0" dx="1" dy="1.1" layer="1"/>
+<text x="-1.1938" y="-0.4064" size="0.762" layer="51">&gt;NAME</text>
+</package>
+</packages>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<designrules name="default *">
+<description language="en">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+The default Design Rules have been set to cover
+a wide range of applications. Your particular design
+may have different requirements, so please make the
+necessary adjustments and save your customized
+design rules under a new name.</description>
+<param name="layerSetup" value="(1*2*15*16)"/>
+<param name="mtCopper" value="1mil 1mil 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 1mil 1mil"/>
+<param name="mtIsolate" value="20mil 20mil 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 20mil"/>
+<param name="mdWireWire" value="8mil"/>
+<param name="mdWirePad" value="8mil"/>
+<param name="mdWireVia" value="8mil"/>
+<param name="mdPadPad" value="8mil"/>
+<param name="mdPadVia" value="8mil"/>
+<param name="mdViaVia" value="8mil"/>
+<param name="mdSmdPad" value="0mil"/>
+<param name="mdSmdVia" value="0mil"/>
+<param name="mdSmdSmd" value="0mil"/>
+<param name="mdViaViaSameLayer" value="8mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="10mil"/>
+<param name="mdDrill" value="8mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="8mil"/>
+<param name="msDrill" value="0.4mm"/>
+<param name="msMicroVia" value="9.99mm"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="10mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="10mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="10mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="8mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="8mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0.8"/>
+<param name="mlMinStopFrame" value="2mil"/>
+<param name="mlMaxStopFrame" value="0mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="2mil"/>
+<param name="mlViaStopLimit" value="16mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="10mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="1"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="50"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="50mil"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="|"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="-"/>
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+</autorouter>
+<elements>
+<element name="IC3" library="proxmark3" package="--MERGED_SOT-23-5" value="--MERGED_PQ1X331M2ZP-3V3-LDO-SOT-23-5" x="18.923" y="43.561" smashed="yes" rot="R270">
+<attribute name="NAME" x="19.4694" y="42.4248" size="1.016" layer="21" font="vector" ratio="20" rot="R90"/>
+</element>
+<element name="SV1" library="  merged" package="USB-MINIB-SMD" value="USB-MINIB" x="6.223" y="44.958" smashed="yes">
+<attribute name="NAME" x="2.069" y="40.804" size="1.27" layer="21" ratio="17" rot="R90"/>
+</element>
+<element name="C1" library="  merged" package="RLC_0603" value="33n" x="12.065" y="47.752" rot="R90"/>
+<element name="IC1" library="  merged" package="VQFP-100" value="SPARTAN-II-XC2S30-100-VQFP" x="45.72" y="11.811" smashed="yes" rot="R90">
+<attribute name="NAME" x="47.561" y="18.954" size="1.9304" layer="21" ratio="14" rot="R270"/>
+</element>
+<element name="XT1" library="  merged" package="XTAL-SMD-CITIZEN-CS10" value="XTAL-SMD-CITIZEN-CS10" x="75.946" y="6.985" smashed="yes" rot="R180">
+<attribute name="NAME" x="73.103" y="8.679" size="1.016" layer="21" rot="R270"/>
+</element>
+<element name="IC4" library="  merged" package="SMV-5" value="HCU-INVERTER" x="76.073" y="2.032" smashed="yes" rot="R180">
+<attribute name="NAME" x="77.343" y="0.673" size="1.016" layer="21" ratio="18"/>
+</element>
+<element name="IC2" library="  merged" package="LQFP-64" value="AT91SAM7S64" x="68.961" y="22.225" smashed="yes" rot="R180">
+<attribute name="NAME" x="67.448" y="19.0331" size="1.27" layer="21" rot="R270"/>
+</element>
+<element name="SV2" library="  merged" package="HIROSE-MQ172-4POS" value="HIROSE-MQ172-4POS" x="0.127" y="23.749" rot="R270"/>
+<element name="IC6" library="  merged" package="TSSOP-14" value="MCP6294" x="25.527" y="8.763" rot="R90"/>
+<element name="R1" library="  merged" package="RLC_0603" value="1meg" x="78.486" y="6.858" rot="R90"/>
+<element name="C2" library="  merged" package="RLC_0603" value="22p" x="78.486" y="3.429" rot="R90"/>
+<element name="C3" library="  merged" package="RLC_0603" value="22p" x="71.12" y="2.413"/>
+<element name="R2" library="  merged" package="RLC_0603" value="100" x="71.12" y="4.191" rot="R180"/>
+<element name="R3" library="  merged" package="RLC_0603" value="330" x="73.025" y="23.114" rot="R270"/>
+<element name="C4" library="  merged" package="RLC_0603" value="33n" x="73.025" y="26.416" rot="R270"/>
+<element name="C5" library="  merged" package="RLC_0603" value="2n" x="71.374" y="26.416" rot="R270"/>
+<element name="XT2" library="  merged" package="XTAL-SMD-CITIZEN-CS10" value="XTAL-SMD-CITIZEN-CS10" x="76.073" y="21.463" rot="R270"/>
+<element name="C6" library="proxmark3" package="--MERGED_RLC_0603" value="22p" x="79.375" y="17.526" rot="R270"/>
+<element name="C7" library="proxmark3" package="--MERGED_RLC_0603" value="22p" x="79.375" y="20.447" rot="R90"/>
+<element name="R4" library="  merged" package="RLC_0603" value="27" x="75.692" y="11.049" rot="R180"/>
+<element name="R5" library="  merged" package="RLC_0603" value="27" x="75.692" y="12.7" rot="R180"/>
+<element name="R6" library="  merged" package="RLC_0603" value="1k5" x="75.692" y="14.351"/>
+<element name="C8" library="  merged" package="RLC_0603" value="1n" x="65.532" y="26.797" rot="R90"/>
+<element name="C9" library="  merged" package="RLC_1210" value="2u2" x="62.865" y="27.94" rot="R90"/>
+<element name="SV3" library="  merged" package="HEADER-MALE-10X2-0.100-SHROUDED" value="" x="63.5" y="45.339" rot="R270"/>
+<element name="R7" library="  merged" package="RLC_0603" value="10k" x="64.008" y="39.37" rot="R180"/>
+<element name="R8" library="  merged" package="RLC_0603" value="10k" x="63.627" y="6.731"/>
+<element name="R9" library="  merged" package="RLC_0603" value="100k" x="29.337" y="5.334" rot="R270"/>
+<element name="R10" library="  merged" package="RLC_0603" value="100k" x="30.861" y="2.667" rot="R90"/>
+<element name="C10" library="  merged" package="RLC_0603" value="100n" x="27.686" y="4.445" rot="R270"/>
+<element name="D1" library="proxmark3" package="--MERGED_SOT23-3LEAD" value="--MERGED_DIODE-SMD-SOT23" x="21.336" y="10.922" smashed="yes" rot="R180">
+<attribute name="NAME" x="20.8514" y="12.3179" size="1.016" layer="25" font="vector" ratio="18" rot="R90"/>
+</element>
+<element name="R11" library="  merged" package="RLC_0603" value="510k" x="22.098" y="5.207"/>
+<element name="C11" library="  merged" package="RLC_0603" value="1n" x="22.098" y="6.858" rot="R180"/>
+<element name="C12" library="  merged" package="RLC_0603" value="1n" x="23.495" y="3.556" rot="R180"/>
+<element name="R12" library="  merged" package="RLC_0603" value="100k" x="23.495" y="1.905" rot="R180"/>
+<element name="R13" library="  merged" package="RLC_0603" value="10k" x="32.512" y="2.667" rot="R90"/>
+<element name="R14" library="  merged" package="RLC_0603" value="10k" x="34.163" y="2.667" rot="R270"/>
+<element name="C13" library="  merged" package="RLC_0603" value="dnp" x="35.814" y="2.667" rot="R270"/>
+<element name="D2" library="proxmark3" package="--MERGED_SOT23-3LEAD" value="--MERGED_DIODE-SMD-SOT23" x="13.462" y="17.145" smashed="yes" rot="R270">
+<attribute name="NAME" x="15.2411" y="16.0216" size="1.016" layer="25" font="vector" ratio="18" rot="R180"/>
+</element>
+<element name="C14" library="  merged" package="RLC_0603" value="22p" x="5.842" y="15.875" rot="R90"/>
+<element name="D3" library="proxmark3" package="--MERGED_SOT23-3LEAD" value="--MERGED_DIODE-SMD-SOT23" x="10.16" y="16.51" smashed="yes">
+<attribute name="NAME" x="8.9096" y="16.5089" size="1.016" layer="25" font="vector" ratio="18" rot="R90"/>
+</element>
+<element name="C15" library="  merged" package="RLC_0603" value="130p" x="16.637" y="17.272" rot="R270"/>
+<element name="R15" library="  merged" package="RLC_0603" value="10k" x="18.288" y="17.272" rot="R90"/>
+<element name="R16" library="  merged" package="RLC_0603" value="zerohm" x="19.939" y="17.272" rot="R270"/>
+<element name="C16" library="  merged" package="RLC_0603" value="1n" x="21.59" y="17.272" rot="R90"/>
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+<element name="C17" library="  merged" package="RLC_0603" value="dnp" x="32.512" y="13.335" rot="R90"/>
+<element name="R19" library="  merged" package="RLC_0603" value="10k" x="30.988" y="10.033" rot="R90"/>
+<element name="R20" library="  merged" package="RLC_0603" value="240k" x="14.859" y="19.685"/>
+<element name="IC8" library="  merged" package="TSSOP-24" value="TLC5540" x="46.99" y="27.432"/>
+<element name="C18" library="  merged" package="RLC_0603" value="33n" x="45.593" y="32.639" rot="R180"/>
+<element name="C19" library="  merged" package="RLC_0603" value="33n" x="48.768" y="32.639" rot="R180"/>
+<element name="IC9" library="  merged" package="TSSOP-20" value="74XX244-OCTAL-TRISTATE-BUFFERS" x="12.192" y="34.544" smashed="yes" rot="R90">
+<attribute name="NAME" x="12.992" y="35.655" size="1.27" layer="21" ratio="17"/>
+</element>
+<element name="IC10" library="  merged" package="TSSOP-20" value="74XX244-OCTAL-TRISTATE-BUFFERS" x="19.05" y="34.544" smashed="yes" rot="R90">
+<attribute name="NAME" x="19.85" y="35.655" size="1.27" layer="21" ratio="17"/>
+</element>
+<element name="SV5" library="proxmark3" package="--MERGED_HEADER-MALE-6X1-0.100-UNKEYED" value="--MERGED_HEADER-MALE-6X1" x="36.703" y="47.879" rot="R270"/>
+<element name="U1" library="  merged" package="RLC_0805" value="FERRITE0805" x="12.827" y="44.577"/>
+<element name="R22" library="  merged" package="RLC_0603" value="33" x="5.461" y="33.782" rot="R270"/>
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+<element name="C25" library="  merged" package="RLC_0603" value="33n" x="67.437" y="6.731"/>
+<element name="C26" library="  merged" package="RLC_0603" value="33n" x="67.31" y="26.797" rot="R90"/>
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+<element name="C30" library="  merged" package="RLC_0603" value="33n" x="45.339" y="1.651" rot="R180"/>
+<element name="C31" library="  merged" package="RLC_0603" value="33n" x="56.007" y="10.16" rot="R90"/>
+<element name="IC11" library="  merged" package="TSSOP-14" value="CD4066" x="30.099" y="18.034" smashed="yes" rot="R90">
+<attribute name="NAME" x="30.115" y="20.769" size="1.27" layer="21" ratio="15" rot="R180"/>
+</element>
+<element name="IC5" library="  merged" package="SOT-23-8-OR-MSOP-8" value="TLV3502" x="17.399" y="23.114"/>
+<element name="R21" library="  merged" package="RLC_0603" value="24k" x="18.288" y="19.685" rot="R180"/>
+<element name="IC12" library="  merged" package="SOIC-8" value="LP2989AIM-2.5" x="29.337" y="35.179" smashed="yes">
+<attribute name="NAME" x="28.321" y="38.1205" size="1.27" layer="25" ratio="17" rot="R90"/>
+</element>
+<element name="R23" library="  merged" package="RLC_0603" value="1k" x="39.751" y="33.909"/>
+<element name="C33" library="  merged" package="RLC_1210" value="4u7" x="43.942" y="39.243" rot="R270"/>
+<element name="IC13" library="proxmark3" package="--MERGED_SOT-23-5" value="--MERGED_PQ1X331M2ZP-3V3-LDO-SOT-23-5" x="37.846" y="28.448" smashed="yes" rot="R90">
+<attribute name="NAME" x="35.6684" y="29.9082" size="1.27" layer="21" font="vector" ratio="18"/>
+</element>
+<element name="C27" library="  merged" package="RLC_1210" value="4u7" x="23.114" y="45.339" rot="R270"/>
+<element name="C28" library="  merged" package="RLC_0603" value="33n" x="38.608" y="1.905"/>
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+<element name="C34" library="  merged" package="RLC_1210" value="4u7" x="37.973" y="25.019"/>
+<element name="D4" library="  merged" package="LED_0603" value="LED" x="56.261" y="29.337" rot="R90"/>
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diff --git a/pcb/proxmark3_fix/CAD/proxmark3.sch b/pcb/proxmark3_fix/CAD/proxmark3.sch
new file mode 100644 (file)
index 0000000..5d7ca62
--- /dev/null
+++ b/pcb/proxmark3_fix/CAD/proxmark3.sch
@@ -0,0 +1,5875 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="6.4">
+<drawing>
+<settings>
+<setting alwaysvectorfont="yes"/>
+<setting verticaltext="up"/>
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+<text x="230.505" y="5.08" size="2.54" layer="94" font="vector">&gt;SHEET</text>
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+<devicesets>
+<deviceset name="A4L-LOC" prefix="FRAME" uservalue="yes">
+<description>&lt;b&gt;FRAME&lt;/b&gt;&lt;p&gt;
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+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
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+<connect gate="G$1" pin="GND3" pad="60"/>
+<connect gate="G$1" pin="JTAGSEL" pad="50"/>
+<connect gate="G$1" pin="NRST" pad="39"/>
+<connect gate="G$1" pin="PA0" pad="48"/>
+<connect gate="G$1" pin="PA1" pad="47"/>
+<connect gate="G$1" pin="PA10" pad="29"/>
+<connect gate="G$1" pin="PA11" pad="28"/>
+<connect gate="G$1" pin="PA12" pad="27"/>
+<connect gate="G$1" pin="PA13" pad="22"/>
+<connect gate="G$1" pin="PA14" pad="21"/>
+<connect gate="G$1" pin="PA15" pad="20"/>
+<connect gate="G$1" pin="PA16" pad="19"/>
+<connect gate="G$1" pin="PA17/AD0" pad="9"/>
+<connect gate="G$1" pin="PA18/AD1" pad="10"/>
+<connect gate="G$1" pin="PA19/AD2" pad="13"/>
+<connect gate="G$1" pin="PA2" pad="44"/>
+<connect gate="G$1" pin="PA20/AD3" pad="16"/>
+<connect gate="G$1" pin="PA21" pad="11"/>
+<connect gate="G$1" pin="PA22" pad="14"/>
+<connect gate="G$1" pin="PA23" pad="15"/>
+<connect gate="G$1" pin="PA24" pad="23"/>
+<connect gate="G$1" pin="PA25" pad="25"/>
+<connect gate="G$1" pin="PA26" pad="26"/>
+<connect gate="G$1" pin="PA27" pad="37"/>
+<connect gate="G$1" pin="PA28" pad="38"/>
+<connect gate="G$1" pin="PA29" pad="41"/>
+<connect gate="G$1" pin="PA3" pad="43"/>
+<connect gate="G$1" pin="PA30" pad="42"/>
+<connect gate="G$1" pin="PA31" pad="52"/>
+<connect gate="G$1" pin="PA4" pad="36"/>
+<connect gate="G$1" pin="PA5" pad="35"/>
+<connect gate="G$1" pin="PA6" pad="34"/>
+<connect gate="G$1" pin="PA7" pad="32"/>
+<connect gate="G$1" pin="PA8" pad="31"/>
+<connect gate="G$1" pin="PA9" pad="30"/>
+<connect gate="G$1" pin="PLLRC" pad="63"/>
+<connect gate="G$1" pin="TCK" pad="53"/>
+<connect gate="G$1" pin="TDI" pad="33"/>
+<connect gate="G$1" pin="TDO" pad="49"/>
+<connect gate="G$1" pin="TMS" pad="51"/>
+<connect gate="G$1" pin="TST" pad="40"/>
+<connect gate="G$1" pin="VDDCORE0" pad="12"/>
+<connect gate="G$1" pin="VDDCORE1" pad="24"/>
+<connect gate="G$1" pin="VDDCORE2" pad="54"/>
+<connect gate="G$1" pin="VDDFLASH" pad="59"/>
+<connect gate="G$1" pin="VDDIN" pad="7"/>
+<connect gate="G$1" pin="VDDIO0" pad="18"/>
+<connect gate="G$1" pin="VDDIO1" pad="45"/>
+<connect gate="G$1" pin="VDDIO2" pad="58"/>
+<connect gate="G$1" pin="VDDOUT" pad="8"/>
+<connect gate="G$1" pin="VDDPLL" pad="64"/>
+<connect gate="G$1" pin="XIN/PGMCK" pad="62"/>
+<connect gate="G$1" pin="XOUT" pad="61"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="SUPPLY_2V5" prefix="V">
+<gates>
+<gate name="G$1" symbol="SUPPLY_+2V5" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="XTAL-SMD-CITIZEN-CS10" prefix="XT">
+<gates>
+<gate name="G$1" symbol="CRYSTAL" x="-10.16" y="2.54"/>
+</gates>
+<devices>
+<device name="" package="XTAL-SMD-CITIZEN-CS10">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="B" pad="B"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="HIROSE-MQ172-4POS" prefix="SV">
+<gates>
+<gate name="G$1" symbol="4TERMSTRIP" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="HIROSE-MQ172-4POS">
+<connects>
+<connect gate="G$1" pin="PIN1" pad="1"/>
+<connect gate="G$1" pin="PIN2" pad="2"/>
+<connect gate="G$1" pin="PIN3" pad="3"/>
+<connect gate="G$1" pin="PIN4" pad="4"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="HEADER-MALE-10X2" prefix="SV" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="HEADER-MALE-10X2" x="2.54" y="-2.54"/>
+</gates>
+<devices>
+<device name="" package="HEADER-MALE-10X2-0.100-SHROUDED">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="11" pad="11"/>
+<connect gate="G$1" pin="12" pad="12"/>
+<connect gate="G$1" pin="13" pad="13"/>
+<connect gate="G$1" pin="14" pad="14"/>
+<connect gate="G$1" pin="15" pad="15"/>
+<connect gate="G$1" pin="16" pad="16"/>
+<connect gate="G$1" pin="17" pad="17"/>
+<connect gate="G$1" pin="18" pad="18"/>
+<connect gate="G$1" pin="19" pad="19"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="20" pad="20"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="SUPPLY_VMID" prefix="V">
+<gates>
+<gate name="G$1" symbol="SUPPLY_VMID" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="TLC5540" prefix="IC">
+<gates>
+<gate name="G$1" symbol="TLC5540" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="TSSOP-24">
+<connects>
+<connect gate="G$1" pin="AGND0" pad="20"/>
+<connect gate="G$1" pin="AGND1" pad="21"/>
+<connect gate="G$1" pin="ANALOGIN" pad="19"/>
+<connect gate="G$1" pin="CLK" pad="12"/>
+<connect gate="G$1" pin="D1" pad="3"/>
+<connect gate="G$1" pin="D2" pad="4"/>
+<connect gate="G$1" pin="D3" pad="5"/>
+<connect gate="G$1" pin="D4" pad="6"/>
+<connect gate="G$1" pin="D5" pad="7"/>
+<connect gate="G$1" pin="D6" pad="8"/>
+<connect gate="G$1" pin="D7" pad="9"/>
+<connect gate="G$1" pin="DGND0" pad="2"/>
+<connect gate="G$1" pin="DGND1" pad="24"/>
+<connect gate="G$1" pin="MSB-D8" pad="10"/>
+<connect gate="G$1" pin="NOE" pad="1"/>
+<connect gate="G$1" pin="REFB" pad="23"/>
+<connect gate="G$1" pin="REFBS" pad="22"/>
+<connect gate="G$1" pin="REFT" pad="17"/>
+<connect gate="G$1" pin="REFTS" pad="16"/>
+<connect gate="G$1" pin="VDDA0" pad="14"/>
+<connect gate="G$1" pin="VDDA1" pad="15"/>
+<connect gate="G$1" pin="VDDA2" pad="18"/>
+<connect gate="G$1" pin="VDDD0" pad="11"/>
+<connect gate="G$1" pin="VDDD1" pad="13"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="SPARTAN-II-XC2S30-100-VQFP" prefix="IC">
+<gates>
+<gate name="G$1" symbol="SPARTAN-II-XC2S30-100-VQFP" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="VQFP-100">
+<connects>
+<connect gate="G$1" pin="/PROGRAM" pad="51"/>
+<connect gate="G$1" pin="CCLK" pad="75"/>
+<connect gate="G$1" pin="DIN" pad="73"/>
+<connect gate="G$1" pin="DONE" pad="49"/>
+<connect gate="G$1" pin="DOUT" pad="74"/>
+<connect gate="G$1" pin="GND1" pad="1"/>
+<connect gate="G$1" pin="GND2" pad="11"/>
+<connect gate="G$1" pin="GND3" pad="38"/>
+<connect gate="G$1" pin="GND4" pad="78"/>
+<connect gate="G$1" pin="GND5" pad="89"/>
+<connect gate="G$1" pin="GND6" pad="48"/>
+<connect gate="G$1" pin="GND7" pad="64"/>
+<connect gate="G$1" pin="GND8" pad="24"/>
+<connect gate="G$1" pin="M0" pad="25"/>
+<connect gate="G$1" pin="M1" pad="23"/>
+<connect gate="G$1" pin="M2" pad="27"/>
+<connect gate="G$1" pin="NC0" pad="28"/>
+<connect gate="G$1" pin="NC1" pad="29"/>
+<connect gate="G$1" pin="P10_IO7" pad="10"/>
+<connect gate="G$1" pin="P13_IO6" pad="13"/>
+<connect gate="G$1" pin="P15_IO6" pad="15"/>
+<connect gate="G$1" pin="P16_IOV6" pad="16"/>
+<connect gate="G$1" pin="P17_IO6" pad="17"/>
+<connect gate="G$1" pin="P18_IO6" pad="18"/>
+<connect gate="G$1" pin="P19_IO6" pad="19"/>
+<connect gate="G$1" pin="P20_IOV6" pad="20"/>
+<connect gate="G$1" pin="P21_IO6" pad="21"/>
+<connect gate="G$1" pin="P22_IO6" pad="22"/>
+<connect gate="G$1" pin="P30_IOV5" pad="30"/>
+<connect gate="G$1" pin="P31_IO5" pad="31"/>
+<connect gate="G$1" pin="P32_IO5" pad="32"/>
+<connect gate="G$1" pin="P34_IOV5" pad="34"/>
+<connect gate="G$1" pin="P36_IGCK5" pad="36"/>
+<connect gate="G$1" pin="P39_IGCK4" pad="39"/>
+<connect gate="G$1" pin="P3_IO7" pad="3"/>
+<connect gate="G$1" pin="P40_IO4" pad="40"/>
+<connect gate="G$1" pin="P41_IOV4" pad="41"/>
+<connect gate="G$1" pin="P43_IO4" pad="43"/>
+<connect gate="G$1" pin="P44_IO4" pad="44"/>
+<connect gate="G$1" pin="P45_IOV4" pad="45"/>
+<connect gate="G$1" pin="P46_IO4" pad="46"/>
+<connect gate="G$1" pin="P47_IO4" pad="47"/>
+<connect gate="G$1" pin="P4_IOV7" pad="4"/>
+<connect gate="G$1" pin="P52_IO3" pad="52"/>
+<connect gate="G$1" pin="P53_IO3" pad="53"/>
+<connect gate="G$1" pin="P54_IOV3" pad="54"/>
+<connect gate="G$1" pin="P55_IO3" pad="55"/>
+<connect gate="G$1" pin="P56_IO3" pad="56"/>
+<connect gate="G$1" pin="P57_IO3" pad="57"/>
+<connect gate="G$1" pin="P58_IO3" pad="58"/>
+<connect gate="G$1" pin="P59_IOV3" pad="59"/>
+<connect gate="G$1" pin="P5_IO7" pad="5"/>
+<connect gate="G$1" pin="P60_IO3" pad="60"/>
+<connect gate="G$1" pin="P62_IO3" pad="62"/>
+<connect gate="G$1" pin="P65_IO2" pad="65"/>
+<connect gate="G$1" pin="P66_IO2" pad="66"/>
+<connect gate="G$1" pin="P67_IOV2" pad="67"/>
+<connect gate="G$1" pin="P68_IO2" pad="68"/>
+<connect gate="G$1" pin="P69_IO2" pad="69"/>
+<connect gate="G$1" pin="P6_IO7" pad="6"/>
+<connect gate="G$1" pin="P70_IO2" pad="70"/>
+<connect gate="G$1" pin="P71_IO2" pad="71"/>
+<connect gate="G$1" pin="P72_IOV2" pad="72"/>
+<connect gate="G$1" pin="P7_IO7" pad="7"/>
+<connect gate="G$1" pin="P80_IO1" pad="80"/>
+<connect gate="G$1" pin="P81_IO1" pad="81"/>
+<connect gate="G$1" pin="P82_IOV1" pad="82"/>
+<connect gate="G$1" pin="P83_IO1" pad="83"/>
+<connect gate="G$1" pin="P84_IO1" pad="84"/>
+<connect gate="G$1" pin="P86_IOV1" pad="86"/>
+<connect gate="G$1" pin="P87_IO1" pad="87"/>
+<connect gate="G$1" pin="P88_IGCK1" pad="88"/>
+<connect gate="G$1" pin="P8_IOV7" pad="8"/>
+<connect gate="G$1" pin="P91_IGCK0" pad="91"/>
+<connect gate="G$1" pin="P93_IOV0" pad="93"/>
+<connect gate="G$1" pin="P95_IO0" pad="95"/>
+<connect gate="G$1" pin="P96_IO0" pad="96"/>
+<connect gate="G$1" pin="P97_IOV0" pad="97"/>
+<connect gate="G$1" pin="P98_IO0" pad="98"/>
+<connect gate="G$1" pin="P9_IO7" pad="9"/>
+<connect gate="G$1" pin="TCK" pad="99"/>
+<connect gate="G$1" pin="TDI" pad="79"/>
+<connect gate="G$1" pin="TDO" pad="77"/>
+<connect gate="G$1" pin="TMS" pad="2"/>
+<connect gate="G$1" pin="VCCINT1" pad="61"/>
+<connect gate="G$1" pin="VCCINT2" pad="92"/>
+<connect gate="G$1" pin="VCCINT3" pad="85"/>
+<connect gate="G$1" pin="VCCINT4" pad="94"/>
+<connect gate="G$1" pin="VCCINT5" pad="14"/>
+<connect gate="G$1" pin="VCCINT6" pad="33"/>
+<connect gate="G$1" pin="VCCINT7" pad="35"/>
+<connect gate="G$1" pin="VCCINT8" pad="42"/>
+<connect gate="G$1" pin="VCCO_B07" pad="100"/>
+<connect gate="G$1" pin="VCCO_B10" pad="90"/>
+<connect gate="G$1" pin="VCCO_B21" pad="76"/>
+<connect gate="G$1" pin="VCCO_B32" pad="63"/>
+<connect gate="G$1" pin="VCCO_B43" pad="50"/>
+<connect gate="G$1" pin="VCCO_B54" pad="37"/>
+<connect gate="G$1" pin="VCCO_B65" pad="26"/>
+<connect gate="G$1" pin="VCCO_B76" pad="12"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="RESISTOR" prefix="R" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="RESISTOR" x="-5.08" y="0"/>
+</gates>
+<devices>
+<device name="2512" package="2512">
+<connects>
+<connect gate="G$1" pin="1" pad="P$1"/>
+<connect gate="G$1" pin="2" pad="P$2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0603" package="RLC_0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0805" package="RLC_0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="1210" package="RLC_1210">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="FERRITE" prefix="U">
+<gates>
+<gate name="G$1" symbol="FERRITE" x="-7.62" y="0"/>
+</gates>
+<devices>
+<device name="0603" package="RLC_0603">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="B" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0805" package="RLC_0805">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="B" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="1210" package="RLC_1210">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="B" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CAPACITOR" prefix="C" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="CAPACITOR" x="2.54" y="0"/>
+</gates>
+<devices>
+<device name="0603" package="RLC_0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0805" package="RLC_0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="1210" package="RLC_1210">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="OPAMP-AD8052" prefix="IC">
+<gates>
+<gate name="A" symbol="OPAMP" x="0" y="0"/>
+<gate name="B" symbol="OPAMP" x="0" y="-12.7"/>
+<gate name="P" symbol="POWER-PINS" x="-20.32" y="2.54"/>
+</gates>
+<devices>
+<device name="" package="MSOP8">
+<connects>
+<connect gate="A" pin="+IN" pad="3"/>
+<connect gate="A" pin="-IN" pad="2"/>
+<connect gate="A" pin="OUT" pad="1"/>
+<connect gate="B" pin="+IN" pad="5"/>
+<connect gate="B" pin="-IN" pad="6"/>
+<connect gate="B" pin="OUT" pad="7"/>
+<connect gate="P" pin="V+" pad="8"/>
+<connect gate="P" pin="V-" pad="4"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CAPACITOR-POLARIZED" prefix="C" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="CAPACITOR-POLARIZED" x="0" y="0"/>
+</gates>
+<devices>
+<device name="ALCHIP-MZA-F80" package="CAPCAITOR-ELECTROLYTIC-ALCHIP-MZA-F80">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="LED" prefix="D">
+<gates>
+<gate name="G$1" symbol="LED" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="LED_0603">
+<connects>
+<connect gate="G$1" pin="A" pad="+"/>
+<connect gate="G$1" pin="C" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="TESTPAD" prefix="TP">
+<gates>
+<gate name="G$1" symbol="TESTPAD" x="0" y="2.54"/>
+</gates>
+<devices>
+<device name="0.7MM-ROUND-DRILLED" package="TESTPAD-PTH-0.7MM">
+<connects>
+<connect gate="G$1" pin="P$1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0.200&quot;-SQUARE" package="SQUARE-PAD-0.200-INCH">
+<connects>
+<connect gate="G$1" pin="P$1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="KEYSTONE-SMD" package="KEYSTONE-SMD-TESTPOINT-5015">
+<connects>
+<connect gate="G$1" pin="P$1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="KEYSTONE-PTH" package="KEYSTONE-PTH-TESTPOINT-5011">
+<connects>
+<connect gate="G$1" pin="P$1" pad="A"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="TACTSWITCH" prefix="SW">
+<gates>
+<gate name="G$1" symbol="TACTSWITCH" x="-10.16" y="5.08"/>
+</gates>
+<devices>
+<device name="THROUGHHOLE" package="TACTSWITCH">
+<connects>
+<connect gate="G$1" pin="P$1" pad="P$1"/>
+<connect gate="G$1" pin="P$2" pad="P$2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="" package="TACTSWITCH-SMD-EVQQ1">
+<connects>
+<connect gate="G$1" pin="P$1" pad="A"/>
+<connect gate="G$1" pin="P$2" pad="B"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="COMP-TLV3502" prefix="IC">
+<gates>
+<gate name="A" symbol="OPAMP" x="0" y="12.7"/>
+<gate name="B" symbol="OPAMP" x="0" y="0"/>
+<gate name="P" symbol="POWER-PINS" x="-15.24" y="12.7"/>
+</gates>
+<devices>
+<device name="SOT-23-8" package="SOT-23-8">
+<connects>
+<connect gate="A" pin="+IN" pad="1"/>
+<connect gate="A" pin="-IN" pad="2"/>
+<connect gate="A" pin="OUT" pad="7"/>
+<connect gate="B" pin="+IN" pad="3"/>
+<connect gate="B" pin="-IN" pad="4"/>
+<connect gate="B" pin="OUT" pad="6"/>
+<connect gate="P" pin="V+" pad="8"/>
+<connect gate="P" pin="V-" pad="5"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOT-23-8-OR-MSOP-8" package="SOT-23-8-OR-MSOP-8">
+<connects>
+<connect gate="A" pin="+IN" pad="1"/>
+<connect gate="A" pin="-IN" pad="2"/>
+<connect gate="A" pin="OUT" pad="7"/>
+<connect gate="B" pin="+IN" pad="3"/>
+<connect gate="B" pin="-IN" pad="4"/>
+<connect gate="B" pin="OUT" pad="6"/>
+<connect gate="P" pin="V+" pad="8"/>
+<connect gate="P" pin="V-" pad="5"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="IRF7307" prefix="Q">
+<gates>
+<gate name="N" symbol="NFET" x="0" y="2.54"/>
+<gate name="P" symbol="PFET" x="10.16" y="0"/>
+</gates>
+<devices>
+<device name="" package="SOIC-8">
+<connects>
+<connect gate="N" pin="D" pad="8"/>
+<connect gate="N" pin="G" pad="2"/>
+<connect gate="N" pin="S" pad="1"/>
+<connect gate="P" pin="D" pad="6"/>
+<connect gate="P" pin="G" pad="4"/>
+<connect gate="P" pin="S" pad="3"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="LP2989-LDO" prefix="IC" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="LP2989-LDO" x="0" y="-2.54"/>
+</gates>
+<devices>
+<device name="SOIC" package="SOIC-8">
+<connects>
+<connect gate="G$1" pin="/ERROR" pad="7"/>
+<connect gate="G$1" pin="/SHDN" pad="8"/>
+<connect gate="G$1" pin="BYP" pad="1"/>
+<connect gate="G$1" pin="GND" pad="3"/>
+<connect gate="G$1" pin="IN" pad="4"/>
+<connect gate="G$1" pin="OUT" pad="5"/>
+<connect gate="G$1" pin="SENSE" pad="6"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CD4066" prefix="IC">
+<gates>
+<gate name="G$1" symbol="CD4066-ANALOG-SWITCH" x="-15.24" y="0"/>
+</gates>
+<devices>
+<device name="" package="TSSOP-14">
+<connects>
+<connect gate="G$1" pin="A1" pad="1"/>
+<connect gate="G$1" pin="A2" pad="4"/>
+<connect gate="G$1" pin="A3" pad="8"/>
+<connect gate="G$1" pin="A4" pad="11"/>
+<connect gate="G$1" pin="B1" pad="2"/>
+<connect gate="G$1" pin="B2" pad="3"/>
+<connect gate="G$1" pin="B3" pad="9"/>
+<connect gate="G$1" pin="B4" pad="10"/>
+<connect gate="G$1" pin="C1" pad="13"/>
+<connect gate="G$1" pin="C2" pad="5"/>
+<connect gate="G$1" pin="C3" pad="6"/>
+<connect gate="G$1" pin="C4" pad="12"/>
+<connect gate="G$1" pin="VDD" pad="14"/>
+<connect gate="G$1" pin="VSS" pad="7"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="OPAMP-TLC2274" prefix="IC">
+<gates>
+<gate name="A" symbol="OPAMP" x="0" y="0"/>
+<gate name="B" symbol="OPAMP" x="0" y="-12.7"/>
+<gate name="C" symbol="OPAMP" x="0" y="-25.4"/>
+<gate name="D" symbol="OPAMP" x="0" y="-38.1"/>
+<gate name="P" symbol="POWER-PINS" x="-30.48" y="-2.54"/>
+</gates>
+<devices>
+<device name="" package="TSSOP-14">
+<connects>
+<connect gate="A" pin="+IN" pad="3"/>
+<connect gate="A" pin="-IN" pad="2"/>
+<connect gate="A" pin="OUT" pad="1"/>
+<connect gate="B" pin="+IN" pad="5"/>
+<connect gate="B" pin="-IN" pad="6"/>
+<connect gate="B" pin="OUT" pad="7"/>
+<connect gate="C" pin="+IN" pad="10"/>
+<connect gate="C" pin="-IN" pad="9"/>
+<connect gate="C" pin="OUT" pad="8"/>
+<connect gate="D" pin="+IN" pad="12"/>
+<connect gate="D" pin="-IN" pad="13"/>
+<connect gate="D" pin="OUT" pad="14"/>
+<connect gate="P" pin="V+" pad="4"/>
+<connect gate="P" pin="V-" pad="11"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="74XX244-OCTAL-TRISTATE-BUFFERS" prefix="IC">
+<gates>
+<gate name="G$1" symbol="74XX244-OCTAL-TRISTATE-BUFFERS" x="-10.16" y="-10.16"/>
+</gates>
+<devices>
+<device name="" package="TSSOP-20">
+<connects>
+<connect gate="G$1" pin="1A1" pad="2"/>
+<connect gate="G$1" pin="1A2" pad="4"/>
+<connect gate="G$1" pin="1A3" pad="6"/>
+<connect gate="G$1" pin="1A4" pad="8"/>
+<connect gate="G$1" pin="1NOE" pad="1"/>
+<connect gate="G$1" pin="1Y1" pad="18"/>
+<connect gate="G$1" pin="1Y2" pad="16"/>
+<connect gate="G$1" pin="1Y3" pad="14"/>
+<connect gate="G$1" pin="1Y4" pad="12"/>
+<connect gate="G$1" pin="2A1" pad="11"/>
+<connect gate="G$1" pin="2A2" pad="13"/>
+<connect gate="G$1" pin="2A3" pad="15"/>
+<connect gate="G$1" pin="2A4" pad="17"/>
+<connect gate="G$1" pin="2NOE" pad="19"/>
+<connect gate="G$1" pin="2Y1" pad="9"/>
+<connect gate="G$1" pin="2Y2" pad="7"/>
+<connect gate="G$1" pin="2Y3" pad="5"/>
+<connect gate="G$1" pin="2Y4" pad="3"/>
+<connect gate="G$1" pin="VDD" pad="20"/>
+<connect gate="G$1" pin="VSS" pad="10"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="HCU-INVERTER" prefix="IC">
+<gates>
+<gate name="G$1" symbol="INVERTER" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="SMV-5">
+<connects>
+<connect gate="G$1" pin="A" pad="2"/>
+<connect gate="G$1" pin="VDD" pad="5"/>
+<connect gate="G$1" pin="VSS" pad="3"/>
+<connect gate="G$1" pin="Y" pad="4"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="USB-MINIB" prefix="SV">
+<gates>
+<gate name="G$1" symbol="USB-MINIB" x="0" y="-2.54"/>
+</gates>
+<devices>
+<device name="" package="USB-MINIB-SMD">
+<connects>
+<connect gate="G$1" pin="D+/3" pad="3"/>
+<connect gate="G$1" pin="D-/2" pad="2"/>
+<connect gate="G$1" pin="GND/5" pad="5"/>
+<connect gate="G$1" pin="ID/4" pad="4"/>
+<connect gate="G$1" pin="SHLD0" pad="TAB0"/>
+<connect gate="G$1" pin="SHLD1" pad="TAB1"/>
+<connect gate="G$1" pin="SHLD2" pad="TAB2"/>
+<connect gate="G$1" pin="SHLD3" pad="TAB3"/>
+<connect gate="G$1" pin="VBUS/1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="supply2">
+<packages>
+</packages>
+<symbols>
+<symbol name="GND">
+<wire x1="-1.27" y1="0" x2="1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="1.27" y1="0" x2="0" y2="-1.27" width="0.254" layer="94"/>
+<wire x1="0" y1="-1.27" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<text x="-1.905" y="-3.175" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="GND" prefix="SUPPLY">
+<description>&lt;b&gt;SUPPLY SYMBOL&lt;/b&gt;</description>
+<gates>
+<gate name="GND" symbol="GND" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="supply1">
+<packages>
+</packages>
+<symbols>
+<symbol name="+3V3">
+<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/>
+<text x="-2.54" y="-5.08" size="1.778" layer="96" rot="R90">&gt;VALUE</text>
+<pin name="+3V3" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+<symbol name="VDD">
+<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/>
+<wire x1="0" y1="1.27" x2="-1.27" y2="-1.905" width="0.254" layer="94"/>
+<wire x1="1.27" y1="-1.905" x2="0" y2="1.27" width="0.254" layer="94"/>
+<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">&gt;VALUE</text>
+<pin name="VDD" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="+3V3" prefix="+3V3">
+<description>&lt;b&gt;SUPPLY SYMBOL&lt;/b&gt;</description>
+<gates>
+<gate name="G$1" symbol="+3V3" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="VDD" prefix="VDD">
+<description>&lt;b&gt;SUPPLY SYMBOL&lt;/b&gt;</description>
+<gates>
+<gate name="G$1" symbol="VDD" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="proxmark3">
+<description>Generated from &lt;b&gt;proxmark3.sch&lt;/b&gt;&lt;p&gt;
+by exp-lbrs.ulp</description>
+<packages>
+<package name="--MERGED_TQ-SMD-RELAY">
+<wire x1="-7" y1="-6.6" x2="7" y2="-6.6" width="0.254" layer="21"/>
+<wire x1="-7" y1="6.6" x2="7" y2="6.6" width="0.254" layer="21"/>
+<wire x1="-7" y1="6.6" x2="-7" y2="-6.6" width="0.254" layer="21"/>
+<wire x1="7" y1="6.6" x2="7" y2="-6.6" width="0.254" layer="21"/>
+<wire x1="-4" y1="2" x2="-6" y2="2" width="0.254" layer="21"/>
+<wire x1="-6" y1="2" x2="-6" y2="-2" width="0.254" layer="21"/>
+<wire x1="-6" y1="-2" x2="-4" y2="-2" width="0.254" layer="21"/>
+<wire x1="-4" y1="-2" x2="-4" y2="2" width="0.254" layer="21"/>
+<smd name="1" x="-5.08" y="-4.78" dx="1" dy="3" layer="1" rot="R180"/>
+<smd name="2" x="-2.54" y="-4.78" dx="1" dy="3" layer="1" rot="R180"/>
+<smd name="3" x="0" y="-4.78" dx="1" dy="3" layer="1" rot="R180"/>
+<smd name="4" x="2.54" y="-4.78" dx="1" dy="3" layer="1" rot="R180"/>
+<smd name="5" x="5.08" y="-4.78" dx="1" dy="3" layer="1" rot="R180"/>
+<smd name="6" x="5.08" y="4.78" dx="1" dy="3" layer="1" rot="R180"/>
+<smd name="7" x="2.54" y="4.78" dx="1" dy="3" layer="1" rot="R180"/>
+<smd name="8" x="0" y="4.78" dx="1" dy="3" layer="1" rot="R180"/>
+<smd name="9" x="-2.54" y="4.78" dx="1" dy="3" layer="1" rot="R180"/>
+<smd name="10" x="-5.08" y="4.78" dx="1" dy="3" layer="1" rot="R180"/>
+<text x="6.35" y="-2.54" size="1.27" layer="21" ratio="17" rot="R90">&gt;NAME</text>
+</package>
+<package name="--MERGED_SOT23-3LEAD">
+<wire x1="-1" y1="1" x2="-1" y2="-0.1" width="0.127" layer="21"/>
+<wire x1="-0.3" y1="-0.7" x2="0.3" y2="-0.7" width="0.127" layer="21"/>
+<wire x1="1" y1="-0.1" x2="1" y2="1" width="0.127" layer="21"/>
+<wire x1="1" y1="1" x2="0.6" y2="1" width="0.127" layer="21"/>
+<wire x1="-1" y1="1" x2="-0.6" y2="1" width="0.127" layer="21"/>
+<smd name="1" x="-0.9398" y="-0.762" dx="1.016" dy="1.016" layer="1"/>
+<smd name="2" x="0.9652" y="-0.762" dx="1.016" dy="1.016" layer="1"/>
+<smd name="3" x="0.0127" y="1.143" dx="1.016" dy="1.778" layer="1"/>
+<text x="2.4326" y="-0.1281" size="1.016" layer="25" font="vector" ratio="18" rot="R90">&gt;NAME</text>
+</package>
+<package name="--MERGED_SOT-23-5">
+<wire x1="-1.3398" y1="-0.4224" x2="1.2602" y2="-0.4224" width="0.127" layer="21"/>
+<wire x1="1.2602" y1="-0.4224" x2="1.2602" y2="0.4776" width="0.127" layer="21"/>
+<wire x1="1.2602" y1="0.4776" x2="-1.3398" y2="0.4776" width="0.127" layer="21"/>
+<wire x1="-1.3398" y1="0.4776" x2="-1.3398" y2="-0.4224" width="0.127" layer="21"/>
+<smd name="1" x="-0.9398" y="-1.4224" dx="0.4" dy="1.5" layer="1"/>
+<smd name="2" x="0.0102" y="-1.4224" dx="0.4" dy="1.5" layer="1"/>
+<smd name="3" x="0.9602" y="-1.4224" dx="0.4" dy="1.5" layer="1"/>
+<smd name="4" x="0.9602" y="1.4276" dx="0.4" dy="1.5" layer="1"/>
+<smd name="5" x="-0.9398" y="1.4276" dx="0.4" dy="1.5" layer="1"/>
+<text x="1.4602" y="2.1776" size="1.27" layer="21" font="vector" rot="R270">&gt;NAME</text>
+</package>
+<package name="--MERGED_HEADER-MALE-6X1-0.100-UNKEYED">
+<wire x1="-1.17" y1="7.62" x2="1.17" y2="7.62" width="0.254" layer="21"/>
+<wire x1="1.17" y1="7.62" x2="1.17" y2="-7.62" width="0.254" layer="21"/>
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+<wire x1="-1.17" y1="-7.62" x2="-1.17" y2="7.62" width="0.254" layer="21"/>
+<pad name="1" x="0" y="6.35" drill="1.143" shape="square"/>
+<pad name="2" x="0" y="3.81" drill="1.143"/>
+<pad name="3" x="0" y="1.27" drill="1.143"/>
+<pad name="4" x="0" y="-1.27" drill="1.143"/>
+<pad name="5" x="0" y="-3.81" drill="1.143"/>
+<pad name="6" x="0" y="-6.35" drill="1.143"/>
+<text x="1.905" y="6.985" size="1.27" layer="21" ratio="22" rot="R270">&gt;NAME</text>
+</package>
+<package name="--MERGED_RLC_0603">
+<wire x1="-1.4732" y1="0.6858" x2="1.4732" y2="0.6858" width="0.15" layer="21"/>
+<wire x1="1.4732" y1="0.6858" x2="1.4732" y2="-0.6858" width="0.15" layer="21"/>
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+<smd name="1" x="-0.85" y="0" dx="1" dy="1.1" layer="1"/>
+<smd name="2" x="0.85" y="0" dx="1" dy="1.1" layer="1"/>
+<text x="-1.1938" y="-0.4064" size="0.762" layer="51">&gt;NAME</text>
+</package>
+<package name="--MERGED_RLC_0805">
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+<smd name="1" x="-0.85" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.85" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="-1.4732" y="-0.635" size="1.27" layer="51">&gt;NAME</text>
+</package>
+<package name="--MERGED_RLC_1210">
+<wire x1="-2.4638" y1="1.6764" x2="2.4638" y2="1.6764" width="0.3048" layer="21"/>
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+<smd name="1" x="-1.5" y="0" dx="1.5" dy="2.9" layer="1"/>
+<smd name="2" x="1.5" y="0" dx="1.5" dy="2.9" layer="1"/>
+<text x="-2.2096" y="-0.736" size="1.524" layer="51">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="--MERGED_RELAY-COIL">
+<wire x1="0" y1="0" x2="1.27" y2="0" width="0.1524" layer="94"/>
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+<pin name="P$1" x="-2.54" y="0" visible="pad" length="short" direction="pas"/>
+<pin name="P$2" x="-2.54" y="-7.62" visible="pad" length="short" direction="pas"/>
+<text x="3.048" y="0" size="1.6764" layer="95" rot="R270">&gt;NAME</text>
+</symbol>
+<symbol name="--MERGED_RELAY-NO-NC">
+<wire x1="0" y1="0" x2="-0.635" y2="-1.27" width="0.1524" layer="94"/>
+<wire x1="0" y1="0" x2="0.635" y2="-1.27" width="0.1524" layer="94"/>
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+<pin name="COM" x="5.08" y="-5.08" visible="pad" length="middle" direction="pas" rot="R90"/>
+<pin name="NC" x="0" y="-5.08" visible="pad" length="middle" direction="pas" rot="R90"/>
+<pin name="NO" x="10.16" y="-5.08" visible="pad" length="middle" direction="pas" rot="R90"/>
+<text x="-0.508" y="1.27" size="1.6764" layer="95">&gt;NAME</text>
+</symbol>
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+<device name="" package="--MERGED_SOT-23-5">
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+<connect gate="G$1" pin="GND" pad="2"/>
+<connect gate="G$1" pin="NR" pad="4"/>
+<connect gate="G$1" pin="VC" pad="3"/>
+<connect gate="G$1" pin="VIN" pad="1"/>
+<connect gate="G$1" pin="VO" pad="5"/>
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+</device>
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+<devices>
+<device name="" package="--MERGED_HEADER-MALE-6X1-0.100-UNKEYED">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
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+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
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+</device>
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+<gates>
+<gate name="G$1" symbol="--MERGED_RESET-GENERATOR-3TERM" x="2.54" y="7.62"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_SOT23-3LEAD">
+<connects>
+<connect gate="G$1" pin="OUT" pad="1"/>
+<connect gate="G$1" pin="V+" pad="2"/>
+<connect gate="G$1" pin="V-" pad="3"/>
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+<technologies>
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+</device>
+</devices>
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+<gates>
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+<devices>
+<device name="" package="--MERGED_SOT23-3LEAD">
+<connects>
+<connect gate="G$1" pin="A" pad="3"/>
+<connect gate="G$1" pin="K1" pad="1"/>
+<connect gate="G$1" pin="K2" pad="2"/>
+</connects>
+<technologies>
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+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_CAPACITOR" prefix="C" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="--MERGED_CAPACITOR" x="2.54" y="0"/>
+</gates>
+<devices>
+<device name="0603" package="--MERGED_RLC_0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
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+<technologies>
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+</device>
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+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
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+</device>
+<device name="1210" package="--MERGED_RLC_1210">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
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+<technologies>
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+</device>
+</devices>
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+<part name="TP6" library="  merged" deviceset="TESTPAD" device="KEYSTONE-PTH"/>
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+<part name="FRAME2" library="frames" deviceset="A4L-LOC" device=""/>
+<part name="IC1" library="  merged" deviceset="SPARTAN-II-XC2S30-100-VQFP" device=""/>
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+<part name="C19" library="  merged" deviceset="CAPACITOR" device="0603" value="33n"/>
+<part name="SV5" library="proxmark3" deviceset="--MERGED_HEADER-MALE-6X1" device=""/>
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+<part name="C5" library="  merged" deviceset="CAPACITOR" device="0603" value="2n"/>
+<part name="V8" library="supply2" deviceset="GND" device=""/>
+<part name="XT2" library="  merged" deviceset="XTAL-SMD-CITIZEN-CS10" device=""/>
+<part name="C6" library="proxmark3" deviceset="--MERGED_CAPACITOR" device="0603" value="22p"/>
+<part name="C7" library="proxmark3" deviceset="--MERGED_CAPACITOR" device="0603" value="22p"/>
+<part name="V9" library="supply2" deviceset="GND" device=""/>
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+<part name="R5" library="  merged" deviceset="RESISTOR" device="0603" value="27"/>
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+<part name="SV3" library="  merged" deviceset="HEADER-MALE-10X2" device=""/>
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+<part name="V12" library="supply2" deviceset="GND" device=""/>
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+<part name="D4" library="  merged" deviceset="LED" device=""/>
+<part name="D5" library="  merged" deviceset="LED" device=""/>
+<part name="D6" library="  merged" deviceset="LED" device=""/>
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+<part name="SW1" library="  merged" deviceset="TACTSWITCH" device=""/>
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+<part name="FRAME4" library="frames" deviceset="A4L-LOC" device=""/>
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+<part name="V13" library="  merged" deviceset="SUPPLY_VMID" device=""/>
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+<part name="C13" library="  merged" deviceset="CAPACITOR" device="0603" value="dnp"/>
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+<part name="D3" library="proxmark3" deviceset="--MERGED_DIODE-SMD-SOT23" device=""/>
+<part name="V19" library="supply2" deviceset="GND" device=""/>
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+<part name="R16" library="  merged" deviceset="RESISTOR" device="0603" value="zerohm"/>
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+<part name="V20" library="  merged" deviceset="SUPPLY_VMID" device=""/>
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+<part name="V21" library="  merged" deviceset="SUPPLY_VMID" device=""/>
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+<part name="V23" library="supply2" deviceset="GND" device=""/>
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+<part name="VDD3" library="supply1" deviceset="VDD" device=""/>
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+<part name="IC5" library="  merged" deviceset="COMP-TLV3502" device="SOT-23-8-OR-MSOP-8" value="TLV3502"/>
+<part name="V34" library="supply2" deviceset="GND" device=""/>
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+<part name="V42" library="supply2" deviceset="GND" device=""/>
+<part name="V43" library="supply2" deviceset="GND" device=""/>
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+<part name="R38" library="  merged" deviceset="RESISTOR" device="0603" value="dnp"/>
+<part name="V46" library="  merged" deviceset="SUPPLY_VMID" device=""/>
+<part name="RLY1" library="proxmark3" deviceset="--MERGED_RELAY-DPDT" device=""/>
+<part name="Q1" library="proxmark3" deviceset="--MERGED_NPN-SOT23-2N3904" device=""/>
+<part name="D7" library="proxmark3" deviceset="--MERGED_DIODE-SMD-SOT23" device=""/>
+<part name="VDD9" library="supply1" deviceset="VDD" device=""/>
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+<part name="V53" library="  merged" deviceset="SUPPLY_VMID" device=""/>
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+<part name="D11" library="proxmark3" deviceset="--MERGED_DIODE-SMD-SOT23" device=""/>
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+<part name="IC9" library="  merged" deviceset="74XX244-OCTAL-TRISTATE-BUFFERS" device=""/>
+<part name="V26" library="supply2" deviceset="GND" device=""/>
+<part name="VDD5" library="supply1" deviceset="VDD" device=""/>
+<part name="IC10" library="  merged" deviceset="74XX244-OCTAL-TRISTATE-BUFFERS" device=""/>
+<part name="V27" library="supply2" deviceset="GND" device=""/>
+<part name="VDD6" library="supply1" deviceset="VDD" device=""/>
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+<part name="R27" library="  merged" deviceset="RESISTOR" device="0603" value="33"/>
+<part name="R28" library="  merged" deviceset="RESISTOR" device="0603" value="33"/>
+<part name="R29" library="  merged" deviceset="RESISTOR" device="0603" value="33"/>
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+<part name="V47" library="supply2" deviceset="GND" device=""/>
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+<part name="C36" library="  merged" deviceset="CAPACITOR" device="0603" value="dnp"/>
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+<part name="R46" library="  merged" deviceset="RESISTOR" device="0603" value="10k"/>
+<part name="TP2" library="  merged" deviceset="TESTPAD" device="KEYSTONE-SMD"/>
+<part name="TP3" library="  merged" deviceset="TESTPAD" device="KEYSTONE-SMD"/>
+<part name="TP4" library="  merged" deviceset="TESTPAD" device="KEYSTONE-SMD"/>
+<part name="TP5" library="  merged" deviceset="TESTPAD" device="KEYSTONE-SMD"/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+<text x="165.1" y="17.78" size="2.54" layer="95">power and bypass</text>
+</plain>
+<instances>
+<instance part="FRAME1" gate="G$1" x="0" y="0"/>
+<instance part="IC3" gate="G$1" x="162.56" y="111.76"/>
+<instance part="SV1" gate="G$1" x="43.18" y="111.76"/>
+<instance part="V1" gate="GND" x="50.8" y="83.82"/>
+<instance part="C1" gate="G$1" x="81.28" y="104.14"/>
+<instance part="V2" gate="GND" x="81.28" y="96.52"/>
+<instance part="V6" gate="GND" x="154.94" y="73.66" rot="MR0"/>
+<instance part="U$3" gate="G$1" x="200.66" y="121.92" rot="MR0"/>
+<instance part="VDD1" gate="G$1" x="147.32" y="93.98" rot="MR0"/>
+<instance part="U1" gate="G$1" x="88.9" y="111.76"/>
+<instance part="C21" gate="G$1" x="30.48" y="144.78"/>
+<instance part="C22" gate="G$1" x="40.64" y="144.78"/>
+<instance part="C23" gate="G$1" x="50.8" y="144.78"/>
+<instance part="C24" gate="G$1" x="60.96" y="144.78"/>
+<instance part="VDD7" gate="G$1" x="30.48" y="157.48"/>
+<instance part="V29" gate="GND" x="101.6" y="134.62"/>
+<instance part="C25" gate="G$1" x="116.84" y="144.78"/>
+<instance part="C26" gate="G$1" x="127" y="144.78"/>
+<instance part="U$8" gate="G$1" x="116.84" y="157.48"/>
+<instance part="V30" gate="GND" x="137.16" y="134.62"/>
+<instance part="V31" gate="G$1" x="198.12" y="157.48"/>
+<instance part="C29" gate="G$1" x="198.12" y="144.78"/>
+<instance part="C30" gate="G$1" x="208.28" y="144.78"/>
+<instance part="C31" gate="G$1" x="218.44" y="144.78"/>
+<instance part="V32" gate="GND" x="228.6" y="134.62"/>
+<instance part="IC12" gate="G$1" x="182.88" y="63.5"/>
+<instance part="V35" gate="GND" x="152.4" y="45.72" rot="MR0"/>
+<instance part="R23" gate="G$1" x="137.16" y="50.8" rot="R90"/>
+<instance part="V36" gate="GND" x="137.16" y="40.64" rot="MR0"/>
+<instance part="V37" gate="G$1" x="195.58" y="68.58" rot="MR0"/>
+<instance part="C33" gate="G$1" x="228.6" y="144.78"/>
+<instance part="IC13" gate="G$1" x="162.56" y="83.82"/>
+<instance part="C27" gate="G$1" x="137.16" y="144.78"/>
+<instance part="C28" gate="G$1" x="152.4" y="144.78"/>
+<instance part="C32" gate="G$1" x="162.56" y="144.78"/>
+<instance part="V38" gate="GND" x="182.88" y="134.62"/>
+<instance part="C34" gate="G$1" x="182.88" y="144.78"/>
+<instance part="V39" gate="GND" x="154.94" y="101.6" rot="MR0"/>
+<instance part="C37" gate="G$1" x="91.44" y="147.32"/>
+<instance part="C38" gate="G$1" x="101.6" y="147.32"/>
+<instance part="TP6" gate="G$1" x="55.88" y="63.5"/>
+<instance part="V51" gate="GND" x="55.88" y="53.34"/>
+<instance part="C44" gate="G$1" x="71.12" y="144.78"/>
+<instance part="D8" gate="G$1" x="60.96" y="93.98"/>
+<instance part="V54" gate="GND" x="60.96" y="88.9"/>
+<instance part="C46" gate="G$1" x="81.28" y="144.78"/>
+<instance part="C47" gate="G$1" x="172.72" y="144.78"/>
+<instance part="Q2" gate="N" x="73.66" y="63.5"/>
+<instance part="Q2" gate="P" x="129.54" y="93.98" rot="R180"/>
+<instance part="V25" gate="GND" x="76.2" y="53.34"/>
+<instance part="R56" gate="G$1" x="119.38" y="101.6" rot="R90"/>
+<instance part="R57" gate="G$1" x="111.76" y="93.98"/>
+<instance part="R58" gate="G$1" x="137.16" y="93.98" rot="R90"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="GND" class="0">
+<segment>
+<wire x1="48.26" y1="101.6" x2="50.8" y2="101.6" width="0.1524" layer="91"/>
+<wire x1="50.8" y1="101.6" x2="50.8" y2="96.52" width="0.1524" layer="91"/>
+<wire x1="50.8" y1="96.52" x2="50.8" y2="93.98" width="0.1524" layer="91"/>
+<wire x1="50.8" y1="93.98" x2="50.8" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="50.8" y1="91.44" x2="50.8" y2="88.9" width="0.1524" layer="91"/>
+<wire x1="50.8" y1="88.9" x2="50.8" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="96.52" x2="50.8" y2="96.52" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="93.98" x2="50.8" y2="93.98" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="91.44" x2="50.8" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="88.9" x2="50.8" y2="88.9" width="0.1524" layer="91"/>
+<junction x="50.8" y="96.52"/>
+<junction x="50.8" y="93.98"/>
+<junction x="50.8" y="91.44"/>
+<junction x="50.8" y="88.9"/>
+<pinref part="SV1" gate="G$1" pin="GND/5"/>
+<pinref part="V1" gate="GND" pin="GND"/>
+<pinref part="SV1" gate="G$1" pin="SHLD0"/>
+<pinref part="SV1" gate="G$1" pin="SHLD1"/>
+<pinref part="SV1" gate="G$1" pin="SHLD2"/>
+<pinref part="SV1" gate="G$1" pin="SHLD3"/>
+</segment>
+<segment>
+<wire x1="81.28" y1="101.6" x2="81.28" y2="99.06" width="0.1524" layer="91"/>
+<pinref part="C1" gate="G$1" pin="2"/>
+<pinref part="V2" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="137.16" y1="142.24" x2="137.16" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="137.16" y1="139.7" x2="137.16" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="137.16" y1="139.7" x2="127" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="127" y1="139.7" x2="127" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="127" y1="139.7" x2="116.84" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="139.7" x2="116.84" y2="142.24" width="0.1524" layer="91"/>
+<junction x="137.16" y="139.7"/>
+<junction x="127" y="139.7"/>
+<pinref part="V30" gate="GND" pin="GND"/>
+<pinref part="C26" gate="G$1" pin="2"/>
+<pinref part="C25" gate="G$1" pin="2"/>
+<pinref part="C27" gate="G$1" pin="2"/>
+</segment>
+<segment>
+<wire x1="228.6" y1="137.16" x2="228.6" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="228.6" y1="139.7" x2="228.6" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="228.6" y1="139.7" x2="218.44" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="218.44" y1="139.7" x2="218.44" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="218.44" y1="139.7" x2="208.28" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="139.7" x2="208.28" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="139.7" x2="198.12" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="198.12" y1="139.7" x2="198.12" y2="142.24" width="0.1524" layer="91"/>
+<junction x="228.6" y="139.7"/>
+<junction x="218.44" y="139.7"/>
+<junction x="208.28" y="139.7"/>
+<pinref part="V32" gate="GND" pin="GND"/>
+<pinref part="C31" gate="G$1" pin="2"/>
+<pinref part="C30" gate="G$1" pin="2"/>
+<pinref part="C29" gate="G$1" pin="2"/>
+<pinref part="C33" gate="G$1" pin="2"/>
+</segment>
+<segment>
+<wire x1="154.94" y1="50.8" x2="152.4" y2="50.8" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="50.8" x2="152.4" y2="48.26" width="0.1524" layer="91"/>
+<pinref part="IC12" gate="G$1" pin="GND"/>
+<pinref part="V35" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="137.16" y1="43.18" x2="137.16" y2="45.72" width="0.1524" layer="91"/>
+<pinref part="V36" gate="GND" pin="GND"/>
+<pinref part="R23" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<wire x1="182.88" y1="142.24" x2="182.88" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="182.88" y1="139.7" x2="182.88" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="182.88" y1="139.7" x2="172.72" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="172.72" y1="139.7" x2="162.56" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="162.56" y1="139.7" x2="162.56" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="162.56" y1="139.7" x2="152.4" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="139.7" x2="152.4" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="172.72" y1="142.24" x2="172.72" y2="139.7" width="0.1524" layer="91"/>
+<junction x="182.88" y="139.7"/>
+<junction x="162.56" y="139.7"/>
+<junction x="172.72" y="139.7"/>
+<pinref part="V38" gate="GND" pin="GND"/>
+<pinref part="C32" gate="G$1" pin="2"/>
+<pinref part="C28" gate="G$1" pin="2"/>
+<pinref part="C34" gate="G$1" pin="2"/>
+<pinref part="C47" gate="G$1" pin="2"/>
+</segment>
+<segment>
+<wire x1="157.48" y1="81.28" x2="154.94" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="81.28" x2="154.94" y2="76.2" width="0.1524" layer="91"/>
+<pinref part="IC13" gate="G$1" pin="GND"/>
+<pinref part="V6" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="157.48" y1="109.22" x2="154.94" y2="109.22" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="109.22" x2="154.94" y2="104.14" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="GND"/>
+<pinref part="V39" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="101.6" y1="142.24" x2="101.6" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="101.6" y1="139.7" x2="101.6" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="139.7" x2="60.96" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="139.7" x2="50.8" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="50.8" y1="139.7" x2="40.64" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="40.64" y1="139.7" x2="30.48" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="139.7" x2="30.48" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="40.64" y1="142.24" x2="40.64" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="50.8" y1="142.24" x2="50.8" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="101.6" y1="139.7" x2="91.44" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="91.44" y1="139.7" x2="81.28" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="139.7" x2="71.12" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="139.7" x2="60.96" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="91.44" y1="142.24" x2="91.44" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="142.24" x2="71.12" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="142.24" x2="81.28" y2="139.7" width="0.1524" layer="91"/>
+<junction x="40.64" y="139.7"/>
+<junction x="50.8" y="139.7"/>
+<junction x="101.6" y="139.7"/>
+<junction x="60.96" y="139.7"/>
+<junction x="91.44" y="139.7"/>
+<junction x="71.12" y="139.7"/>
+<junction x="81.28" y="139.7"/>
+<pinref part="C38" gate="G$1" pin="-"/>
+<pinref part="V29" gate="GND" pin="GND"/>
+<pinref part="C24" gate="G$1" pin="2"/>
+<pinref part="C21" gate="G$1" pin="2"/>
+<pinref part="C22" gate="G$1" pin="2"/>
+<pinref part="C23" gate="G$1" pin="2"/>
+<pinref part="C37" gate="G$1" pin="-"/>
+<pinref part="C44" gate="G$1" pin="2"/>
+<pinref part="C46" gate="G$1" pin="2"/>
+</segment>
+<segment>
+<wire x1="55.88" y1="60.96" x2="55.88" y2="55.88" width="0.1524" layer="91"/>
+<pinref part="TP6" gate="G$1" pin="P$1"/>
+<pinref part="V51" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="60.96" y1="93.98" x2="60.96" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="D8" gate="G$1" pin="A"/>
+<pinref part="V54" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="68.58" y1="60.96" x2="66.04" y2="60.96" width="0.1524" layer="91"/>
+<wire x1="66.04" y1="60.96" x2="66.04" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="73.66" y1="63.5" x2="76.2" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="63.5" x2="76.2" y2="60.96" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="60.96" x2="76.2" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="58.42" x2="76.2" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="73.66" y1="60.96" x2="76.2" y2="60.96" width="0.1524" layer="91"/>
+<wire x1="66.04" y1="58.42" x2="76.2" y2="58.42" width="0.1524" layer="91"/>
+<junction x="76.2" y="60.96"/>
+<junction x="76.2" y="58.42"/>
+<pinref part="Q2" gate="N" pin="G"/>
+<pinref part="Q2" gate="N" pin="D"/>
+<pinref part="V25" gate="GND" pin="GND"/>
+<pinref part="Q2" gate="N" pin="S"/>
+</segment>
+</net>
+<net name="N$1" class="0">
+<segment>
+<wire x1="48.26" y1="111.76" x2="81.28" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="111.76" x2="86.36" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="109.22" x2="81.28" y2="111.76" width="0.1524" layer="91"/>
+<junction x="81.28" y="111.76"/>
+<pinref part="SV1" gate="G$1" pin="VBUS/1"/>
+<pinref part="C1" gate="G$1" pin="1"/>
+<pinref part="U1" gate="G$1" pin="A"/>
+</segment>
+</net>
+<net name="USB_D-" class="0">
+<segment>
+<wire x1="66.04" y1="109.22" x2="63.5" y2="109.22" width="0.1524" layer="91"/>
+<wire x1="63.5" y1="109.22" x2="48.26" y2="109.22" width="0.1524" layer="91"/>
+<wire x1="63.5" y1="109.22" x2="63.5" y2="101.6" width="0.1524" layer="91"/>
+<junction x="63.5" y="109.22"/>
+<label x="66.04" y="109.22" size="1.778" layer="95"/>
+<pinref part="SV1" gate="G$1" pin="D-/2"/>
+<pinref part="D8" gate="G$1" pin="K2"/>
+</segment>
+</net>
+<net name="USB_D+" class="0">
+<segment>
+<wire x1="66.04" y1="106.68" x2="58.42" y2="106.68" width="0.1524" layer="91"/>
+<wire x1="58.42" y1="106.68" x2="48.26" y2="106.68" width="0.1524" layer="91"/>
+<wire x1="58.42" y1="106.68" x2="58.42" y2="101.6" width="0.1524" layer="91"/>
+<junction x="58.42" y="106.68"/>
+<label x="66.04" y="106.68" size="1.778" layer="95"/>
+<pinref part="SV1" gate="G$1" pin="D+/3"/>
+<pinref part="D8" gate="G$1" pin="K1"/>
+</segment>
+</net>
+<net name="+3V3" class="0">
+<segment>
+<wire x1="185.42" y1="111.76" x2="200.66" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="200.66" y1="111.76" x2="200.66" y2="119.38" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="VO"/>
+<pinref part="U$3" gate="G$1" pin="+3V3"/>
+</segment>
+<segment>
+<wire x1="116.84" y1="149.86" x2="116.84" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="152.4" x2="116.84" y2="154.94" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="152.4" x2="127" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="127" y1="152.4" x2="127" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="127" y1="152.4" x2="137.16" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="137.16" y1="152.4" x2="137.16" y2="149.86" width="0.1524" layer="91"/>
+<junction x="116.84" y="152.4"/>
+<junction x="127" y="152.4"/>
+<pinref part="C25" gate="G$1" pin="1"/>
+<pinref part="U$8" gate="G$1" pin="+3V3"/>
+<pinref part="C26" gate="G$1" pin="1"/>
+<pinref part="C27" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="VDD" class="0">
+<segment>
+<wire x1="30.48" y1="154.94" x2="30.48" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="152.4" x2="30.48" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="152.4" x2="40.64" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="40.64" y1="152.4" x2="50.8" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="50.8" y1="152.4" x2="60.96" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="152.4" x2="60.96" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="50.8" y1="152.4" x2="50.8" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="40.64" y1="149.86" x2="40.64" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="152.4" x2="71.12" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="152.4" x2="81.28" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="152.4" x2="91.44" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="91.44" y1="152.4" x2="101.6" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="101.6" y1="152.4" x2="101.6" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="91.44" y1="149.86" x2="91.44" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="149.86" x2="71.12" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="149.86" x2="81.28" y2="152.4" width="0.1524" layer="91"/>
+<junction x="30.48" y="152.4"/>
+<junction x="50.8" y="152.4"/>
+<junction x="40.64" y="152.4"/>
+<junction x="60.96" y="152.4"/>
+<junction x="91.44" y="152.4"/>
+<junction x="71.12" y="152.4"/>
+<junction x="81.28" y="152.4"/>
+<pinref part="VDD7" gate="G$1" pin="VDD"/>
+<pinref part="C21" gate="G$1" pin="1"/>
+<pinref part="C24" gate="G$1" pin="1"/>
+<pinref part="C23" gate="G$1" pin="1"/>
+<pinref part="C22" gate="G$1" pin="1"/>
+<pinref part="C38" gate="G$1" pin="+"/>
+<pinref part="C37" gate="G$1" pin="+"/>
+<pinref part="C44" gate="G$1" pin="1"/>
+<pinref part="C46" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<wire x1="132.08" y1="91.44" x2="132.08" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="147.32" y1="83.82" x2="147.32" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="147.32" y1="86.36" x2="147.32" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="157.48" y1="83.82" x2="147.32" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="63.5" x2="147.32" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="147.32" y1="63.5" x2="147.32" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="132.08" y1="86.36" x2="137.16" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="137.16" y1="86.36" x2="147.32" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="127" y1="91.44" x2="132.08" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="137.16" y1="88.9" x2="137.16" y2="86.36" width="0.1524" layer="91"/>
+<junction x="147.32" y="83.82"/>
+<junction x="147.32" y="86.36"/>
+<junction x="137.16" y="86.36"/>
+<pinref part="VDD1" gate="G$1" pin="VDD"/>
+<pinref part="IC13" gate="G$1" pin="VIN"/>
+<pinref part="IC12" gate="G$1" pin="IN"/>
+<pinref part="Q2" gate="P" pin="D"/>
+<pinref part="R58" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="+2V5" class="0">
+<segment>
+<wire x1="198.12" y1="154.94" x2="198.12" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="198.12" y1="152.4" x2="198.12" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="198.12" y1="152.4" x2="208.28" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="152.4" x2="208.28" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="152.4" x2="218.44" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="218.44" y1="152.4" x2="218.44" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="218.44" y1="152.4" x2="228.6" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="228.6" y1="152.4" x2="228.6" y2="149.86" width="0.1524" layer="91"/>
+<junction x="198.12" y="152.4"/>
+<junction x="208.28" y="152.4"/>
+<junction x="218.44" y="152.4"/>
+<pinref part="V31" gate="G$1" pin="+2V5"/>
+<pinref part="C29" gate="G$1" pin="1"/>
+<pinref part="C30" gate="G$1" pin="1"/>
+<pinref part="C31" gate="G$1" pin="1"/>
+<pinref part="C33" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<wire x1="187.96" y1="60.96" x2="195.58" y2="60.96" width="0.1524" layer="91"/>
+<wire x1="195.58" y1="60.96" x2="195.58" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="195.58" y1="63.5" x2="195.58" y2="66.04" width="0.1524" layer="91"/>
+<wire x1="187.96" y1="63.5" x2="195.58" y2="63.5" width="0.1524" layer="91"/>
+<junction x="195.58" y="63.5"/>
+<pinref part="IC12" gate="G$1" pin="SENSE"/>
+<pinref part="V37" gate="G$1" pin="+2V5"/>
+<pinref part="IC12" gate="G$1" pin="OUT"/>
+</segment>
+</net>
+<net name="FPGA_ON" class="0">
+<segment>
+<wire x1="157.48" y1="78.74" x2="139.7" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="137.16" y1="55.88" x2="137.16" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="137.16" y1="58.42" x2="139.7" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="139.7" y1="58.42" x2="154.94" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="129.54" y1="58.42" x2="137.16" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="139.7" y1="78.74" x2="139.7" y2="58.42" width="0.1524" layer="91"/>
+<junction x="137.16" y="58.42"/>
+<junction x="139.7" y="58.42"/>
+<label x="129.54" y="58.42" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC13" gate="G$1" pin="VC"/>
+<pinref part="R23" gate="G$1" pin="2"/>
+<pinref part="IC12" gate="G$1" pin="/SHDN"/>
+</segment>
+</net>
+<net name="+3V3-FPGA" class="0">
+<segment>
+<wire x1="185.42" y1="83.82" x2="200.66" y2="83.82" width="0.1524" layer="91"/>
+<label x="200.66" y="83.82" size="1.778" layer="95"/>
+<pinref part="IC13" gate="G$1" pin="VO"/>
+</segment>
+<segment>
+<wire x1="152.4" y1="149.86" x2="152.4" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="152.4" x2="162.56" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="162.56" y1="152.4" x2="162.56" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="162.56" y1="152.4" x2="172.72" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="172.72" y1="152.4" x2="182.88" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="182.88" y1="152.4" x2="182.88" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="152.4" x2="152.4" y2="157.48" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="157.48" x2="154.94" y2="157.48" width="0.1524" layer="91"/>
+<wire x1="172.72" y1="149.86" x2="172.72" y2="152.4" width="0.1524" layer="91"/>
+<junction x="152.4" y="152.4"/>
+<junction x="162.56" y="152.4"/>
+<junction x="172.72" y="152.4"/>
+<label x="154.94" y="157.48" size="1.778" layer="95"/>
+<pinref part="C28" gate="G$1" pin="1"/>
+<pinref part="C32" gate="G$1" pin="1"/>
+<pinref part="C34" gate="G$1" pin="1"/>
+<pinref part="C47" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="PFETGATE" class="0">
+<segment>
+<wire x1="121.92" y1="93.98" x2="119.38" y2="93.98" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="93.98" x2="119.38" y2="96.52" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="93.98" x2="119.38" y2="93.98" width="0.1524" layer="91"/>
+<junction x="119.38" y="93.98"/>
+<pinref part="Q2" gate="P" pin="G"/>
+<pinref part="R56" gate="G$1" pin="1"/>
+<pinref part="R57" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="NVDD_ON" class="0">
+<segment>
+<wire x1="104.14" y1="93.98" x2="106.68" y2="93.98" width="0.1524" layer="91"/>
+<label x="104.14" y="93.98" size="1.778" layer="95" rot="MR0"/>
+<pinref part="R57" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$49" class="0">
+<segment>
+<wire x1="137.16" y1="99.06" x2="137.16" y2="101.6" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="111.76" x2="157.48" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="157.48" y1="106.68" x2="152.4" y2="106.68" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="106.68" x2="152.4" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="99.06" y1="111.76" x2="119.38" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="111.76" x2="132.08" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="132.08" y1="111.76" x2="152.4" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="132.08" y1="93.98" x2="132.08" y2="101.6" width="0.1524" layer="91"/>
+<wire x1="132.08" y1="101.6" x2="132.08" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="132.08" y1="93.98" x2="127" y2="93.98" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="106.68" x2="119.38" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="137.16" y1="101.6" x2="132.08" y2="101.6" width="0.1524" layer="91"/>
+<junction x="152.4" y="111.76"/>
+<junction x="132.08" y="111.76"/>
+<junction x="119.38" y="111.76"/>
+<junction x="132.08" y="101.6"/>
+<pinref part="R58" gate="G$1" pin="2"/>
+<pinref part="IC3" gate="G$1" pin="VIN"/>
+<pinref part="IC3" gate="G$1" pin="VC"/>
+<pinref part="U1" gate="G$1" pin="B"/>
+<pinref part="Q2" gate="P" pin="S"/>
+<pinref part="R56" gate="G$1" pin="2"/>
+</segment>
+</net>
+</nets>
+</sheet>
+<sheet>
+<plain>
+<text x="165.1" y="17.78" size="2.54" layer="95">FPGA and ADC</text>
+<text x="50.8" y="123.19" size="1.778" layer="95">M2:0=111 means slave</text>
+<text x="50.8" y="120.65" size="1.778" layer="95">serial (with pull-ups)</text>
+</plain>
+<instances>
+<instance part="FRAME2" gate="G$1" x="0" y="0"/>
+<instance part="IC1" gate="G$1" x="88.9" y="154.94"/>
+<instance part="V3" gate="GND" x="93.98" y="22.86" rot="MR0"/>
+<instance part="V4" gate="G$1" x="134.62" y="167.64" rot="MR0"/>
+<instance part="XT1" gate="G$1" x="38.1" y="66.04"/>
+<instance part="IC4" gate="G$1" x="27.94" y="55.88"/>
+<instance part="R1" gate="G$1" x="43.18" y="73.66"/>
+<instance part="C2" gate="G$1" x="20.32" y="45.72" rot="MR0"/>
+<instance part="C3" gate="G$1" x="53.34" y="45.72" rot="MR0"/>
+<instance part="R2" gate="G$1" x="43.18" y="55.88"/>
+<instance part="V7" gate="GND" x="53.34" y="35.56"/>
+<instance part="IC8" gate="G$1" x="187.96" y="154.94" rot="MR0"/>
+<instance part="VDD4" gate="G$1" x="213.36" y="167.64" rot="MR0"/>
+<instance part="V24" gate="GND" x="190.5" y="96.52" rot="MR0"/>
+<instance part="C18" gate="G$1" x="223.52" y="99.06"/>
+<instance part="C19" gate="G$1" x="233.68" y="99.06"/>
+<instance part="SV5" gate="G$1" x="210.82" y="53.34" rot="MR0"/>
+<instance part="V28" gate="GND" x="223.52" y="45.72" rot="MR0"/>
+<instance part="U$5" gate="G$1" x="220.98" y="76.2"/>
+<instance part="R39" gate="G$1" x="55.88" y="93.98"/>
+<instance part="R44" gate="G$1" x="55.88" y="86.36"/>
+<instance part="R47" gate="G$1" x="180.34" y="114.3" rot="R90"/>
+<instance part="VDD10" gate="G$1" x="170.18" y="111.76"/>
+<instance part="TP7" gate="G$1" x="149.86" y="109.22"/>
+<instance part="R52" gate="G$1" x="243.84" y="137.16" rot="R90"/>
+<instance part="VDD11" gate="G$1" x="243.84" y="147.32" rot="MR0"/>
+<instance part="R53" gate="G$1" x="243.84" y="121.92" rot="R90"/>
+<instance part="R54" gate="G$1" x="243.84" y="93.98" rot="R90"/>
+<instance part="V55" gate="GND" x="243.84" y="81.28"/>
+<instance part="R59" gate="G$1" x="170.18" y="50.8"/>
+</instances>
+<busses>
+<bus name="NCS,SPCK,MISO,MOSI">
+<segment>
+<wire x1="157.48" y1="81.28" x2="157.48" y2="71.12" width="0.762" layer="92"/>
+<wire x1="157.48" y1="71.12" x2="160.02" y2="68.58" width="0.762" layer="92"/>
+<label x="160.02" y="68.58" size="1.778" layer="95"/>
+</segment>
+</bus>
+<bus name="ADC[1..8]">
+<segment>
+<wire x1="170.18" y1="132.08" x2="170.18" y2="149.86" width="0.762" layer="92"/>
+<wire x1="170.18" y1="149.86" x2="167.64" y2="152.4" width="0.762" layer="92"/>
+<wire x1="157.48" y1="33.02" x2="154.94" y2="35.56" width="0.762" layer="92"/>
+<wire x1="154.94" y1="35.56" x2="154.94" y2="55.88" width="0.762" layer="92"/>
+<label x="167.64" y="152.4" size="1.778" layer="95" rot="MR0"/>
+<label x="157.48" y="33.02" size="1.778" layer="95"/>
+</segment>
+</bus>
+</busses>
+<nets>
+<net name="GND" class="0">
+<segment>
+<wire x1="53.34" y1="43.18" x2="53.34" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="53.34" y1="40.64" x2="53.34" y2="38.1" width="0.1524" layer="91"/>
+<wire x1="53.34" y1="40.64" x2="30.48" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="40.64" x2="30.48" y2="50.8" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="40.64" x2="20.32" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="40.64" x2="20.32" y2="43.18" width="0.1524" layer="91"/>
+<junction x="53.34" y="40.64"/>
+<junction x="30.48" y="40.64"/>
+<pinref part="C3" gate="G$1" pin="2"/>
+<pinref part="V7" gate="GND" pin="GND"/>
+<pinref part="IC4" gate="G$1" pin="VSS"/>
+<pinref part="C2" gate="G$1" pin="2"/>
+</segment>
+<segment>
+<wire x1="200.66" y1="104.14" x2="200.66" y2="101.6" width="0.1524" layer="91"/>
+<wire x1="200.66" y1="101.6" x2="198.12" y2="101.6" width="0.1524" layer="91"/>
+<wire x1="198.12" y1="101.6" x2="198.12" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="198.12" y1="101.6" x2="193.04" y2="101.6" width="0.1524" layer="91"/>
+<wire x1="193.04" y1="101.6" x2="193.04" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="193.04" y1="101.6" x2="190.5" y2="101.6" width="0.1524" layer="91"/>
+<wire x1="190.5" y1="101.6" x2="190.5" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="190.5" y1="99.06" x2="190.5" y2="101.6" width="0.1524" layer="91"/>
+<junction x="198.12" y="101.6"/>
+<junction x="193.04" y="101.6"/>
+<junction x="190.5" y="101.6"/>
+<pinref part="IC8" gate="G$1" pin="AGND1"/>
+<pinref part="IC8" gate="G$1" pin="AGND0"/>
+<pinref part="IC8" gate="G$1" pin="DGND1"/>
+<pinref part="IC8" gate="G$1" pin="DGND0"/>
+<pinref part="V24" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="119.38" y1="30.48" x2="119.38" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="27.94" x2="116.84" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="27.94" x2="111.76" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="111.76" y1="27.94" x2="109.22" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="109.22" y1="27.94" x2="106.68" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="106.68" y1="27.94" x2="104.14" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="104.14" y1="27.94" x2="101.6" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="101.6" y1="27.94" x2="99.06" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="99.06" y1="27.94" x2="96.52" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="96.52" y1="27.94" x2="93.98" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="93.98" y1="27.94" x2="93.98" y2="30.48" width="0.1524" layer="91"/>
+<wire x1="96.52" y1="30.48" x2="96.52" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="99.06" y1="30.48" x2="99.06" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="101.6" y1="30.48" x2="101.6" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="104.14" y1="30.48" x2="104.14" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="106.68" y1="30.48" x2="106.68" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="109.22" y1="30.48" x2="109.22" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="111.76" y1="30.48" x2="111.76" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="30.48" x2="116.84" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="93.98" y1="25.4" x2="93.98" y2="27.94" width="0.1524" layer="91"/>
+<junction x="96.52" y="27.94"/>
+<junction x="99.06" y="27.94"/>
+<junction x="101.6" y="27.94"/>
+<junction x="104.14" y="27.94"/>
+<junction x="106.68" y="27.94"/>
+<junction x="109.22" y="27.94"/>
+<junction x="111.76" y="27.94"/>
+<junction x="116.84" y="27.94"/>
+<junction x="93.98" y="27.94"/>
+<pinref part="IC1" gate="G$1" pin="NC1"/>
+<pinref part="IC1" gate="G$1" pin="GND1"/>
+<pinref part="IC1" gate="G$1" pin="GND2"/>
+<pinref part="IC1" gate="G$1" pin="GND3"/>
+<pinref part="IC1" gate="G$1" pin="GND4"/>
+<pinref part="IC1" gate="G$1" pin="GND5"/>
+<pinref part="IC1" gate="G$1" pin="GND6"/>
+<pinref part="IC1" gate="G$1" pin="GND7"/>
+<pinref part="IC1" gate="G$1" pin="GND8"/>
+<pinref part="IC1" gate="G$1" pin="NC0"/>
+<pinref part="V3" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="218.44" y1="53.34" x2="223.52" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="223.52" y1="53.34" x2="223.52" y2="48.26" width="0.1524" layer="91"/>
+<pinref part="SV5" gate="G$1" pin="5"/>
+<pinref part="V28" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="243.84" y1="88.9" x2="243.84" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="243.84" y1="86.36" x2="243.84" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="233.68" y1="96.52" x2="233.68" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="233.68" y1="86.36" x2="223.52" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="223.52" y1="86.36" x2="223.52" y2="96.52" width="0.1524" layer="91"/>
+<wire x1="243.84" y1="86.36" x2="233.68" y2="86.36" width="0.1524" layer="91"/>
+<junction x="243.84" y="86.36"/>
+<junction x="233.68" y="86.36"/>
+<pinref part="R54" gate="G$1" pin="1"/>
+<pinref part="V55" gate="GND" pin="GND"/>
+<pinref part="C19" gate="G$1" pin="2"/>
+<pinref part="C18" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="+3V3" class="0">
+<segment>
+<wire x1="218.44" y1="50.8" x2="220.98" y2="50.8" width="0.1524" layer="91"/>
+<wire x1="220.98" y1="50.8" x2="220.98" y2="73.66" width="0.1524" layer="91"/>
+<pinref part="SV5" gate="G$1" pin="6"/>
+<pinref part="U$5" gate="G$1" pin="+3V3"/>
+</segment>
+</net>
+<net name="N$4" class="0">
+<segment>
+<wire x1="25.4" y1="55.88" x2="20.32" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="55.88" x2="20.32" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="63.5" x2="38.1" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="38.1" y1="73.66" x2="20.32" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="73.66" x2="20.32" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="55.88" x2="20.32" y2="50.8" width="0.1524" layer="91"/>
+<junction x="20.32" y="63.5"/>
+<junction x="20.32" y="55.88"/>
+<pinref part="IC4" gate="G$1" pin="A"/>
+<pinref part="XT1" gate="G$1" pin="A"/>
+<pinref part="R1" gate="G$1" pin="1"/>
+<pinref part="C2" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$5" class="0">
+<segment>
+<wire x1="48.26" y1="63.5" x2="53.34" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="53.34" y1="63.5" x2="53.34" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="53.34" y1="55.88" x2="53.34" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="83.82" y1="53.34" x2="76.2" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="53.34" x2="53.34" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="73.66" x2="53.34" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="53.34" y1="73.66" x2="53.34" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="53.34" y1="50.8" x2="53.34" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="55.88" x2="53.34" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="83.82" y1="50.8" x2="76.2" y2="50.8" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="50.8" x2="76.2" y2="53.34" width="0.1524" layer="91"/>
+<junction x="53.34" y="63.5"/>
+<junction x="53.34" y="53.34"/>
+<junction x="53.34" y="55.88"/>
+<junction x="76.2" y="53.34"/>
+<pinref part="XT1" gate="G$1" pin="B"/>
+<pinref part="IC1" gate="G$1" pin="P91_IGCK0"/>
+<pinref part="R1" gate="G$1" pin="2"/>
+<pinref part="C3" gate="G$1" pin="1"/>
+<pinref part="R2" gate="G$1" pin="2"/>
+<pinref part="IC1" gate="G$1" pin="P93_IOV0"/>
+</segment>
+</net>
+<net name="N$3" class="0">
+<segment>
+<wire x1="38.1" y1="55.88" x2="35.56" y2="55.88" width="0.1524" layer="91"/>
+<pinref part="R2" gate="G$1" pin="1"/>
+<pinref part="IC4" gate="G$1" pin="Y"/>
+</segment>
+</net>
+<net name="SPCK" class="0">
+<segment>
+<wire x1="157.48" y1="81.28" x2="154.94" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="83.82" x2="142.24" y2="83.82" width="0.1524" layer="91"/>
+<label x="144.78" y="83.82" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P39_IGCK4"/>
+</segment>
+</net>
+<net name="MISO" class="0">
+<segment>
+<wire x1="157.48" y1="78.74" x2="154.94" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="81.28" x2="142.24" y2="81.28" width="0.1524" layer="91"/>
+<label x="144.78" y="81.28" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P40_IO4"/>
+</segment>
+</net>
+<net name="MOSI" class="0">
+<segment>
+<wire x1="157.48" y1="73.66" x2="154.94" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="76.2" x2="142.24" y2="76.2" width="0.1524" layer="91"/>
+<label x="144.78" y="76.2" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P43_IO4"/>
+</segment>
+</net>
+<net name="NCS" class="0">
+<segment>
+<wire x1="157.48" y1="71.12" x2="154.94" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="73.66" x2="142.24" y2="73.66" width="0.1524" layer="91"/>
+<label x="144.78" y="73.66" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P44_IO4"/>
+</segment>
+</net>
+<net name="VDD" class="0">
+<segment>
+<wire x1="203.2" y1="160.02" x2="203.2" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="200.66" y1="162.56" x2="200.66" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="203.2" y1="162.56" x2="200.66" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="203.2" y1="162.56" x2="208.28" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="162.56" x2="208.28" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="162.56" x2="210.82" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="210.82" y1="162.56" x2="210.82" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="210.82" y1="162.56" x2="213.36" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="213.36" y1="162.56" x2="213.36" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="213.36" y1="165.1" x2="213.36" y2="162.56" width="0.1524" layer="91"/>
+<junction x="203.2" y="162.56"/>
+<junction x="208.28" y="162.56"/>
+<junction x="210.82" y="162.56"/>
+<junction x="213.36" y="162.56"/>
+<pinref part="IC8" gate="G$1" pin="VDDD0"/>
+<pinref part="IC8" gate="G$1" pin="VDDD1"/>
+<pinref part="IC8" gate="G$1" pin="VDDA2"/>
+<pinref part="IC8" gate="G$1" pin="VDDA1"/>
+<pinref part="IC8" gate="G$1" pin="VDDA0"/>
+<pinref part="VDD4" gate="G$1" pin="VDD"/>
+</segment>
+<segment>
+<wire x1="180.34" y1="109.22" x2="180.34" y2="106.68" width="0.1524" layer="91"/>
+<wire x1="180.34" y1="106.68" x2="170.18" y2="106.68" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="106.68" x2="170.18" y2="109.22" width="0.1524" layer="91"/>
+<pinref part="R47" gate="G$1" pin="1"/>
+<pinref part="VDD10" gate="G$1" pin="VDD"/>
+</segment>
+<segment>
+<wire x1="243.84" y1="144.78" x2="243.84" y2="142.24" width="0.1524" layer="91"/>
+<pinref part="VDD11" gate="G$1" pin="VDD"/>
+<pinref part="R52" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$24" class="0">
+<segment>
+<wire x1="220.98" y1="124.46" x2="223.52" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="223.52" y1="124.46" x2="223.52" y2="114.3" width="0.1524" layer="91"/>
+<wire x1="223.52" y1="114.3" x2="223.52" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="243.84" y1="116.84" x2="243.84" y2="114.3" width="0.1524" layer="91"/>
+<wire x1="243.84" y1="114.3" x2="243.84" y2="99.06" width="0.1524" layer="91"/>
+<wire x1="223.52" y1="114.3" x2="243.84" y2="114.3" width="0.1524" layer="91"/>
+<junction x="223.52" y="114.3"/>
+<junction x="243.84" y="114.3"/>
+<pinref part="IC8" gate="G$1" pin="REFB"/>
+<pinref part="C18" gate="G$1" pin="1"/>
+<pinref part="R53" gate="G$1" pin="1"/>
+<pinref part="R54" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="+2V5" class="0">
+<segment>
+<wire x1="116.84" y1="162.56" x2="116.84" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="162.56" x2="119.38" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="162.56" x2="119.38" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="162.56" x2="121.92" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="121.92" y1="162.56" x2="121.92" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="121.92" y1="162.56" x2="124.46" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="162.56" x2="124.46" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="162.56" x2="127" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="127" y1="162.56" x2="127" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="127" y1="162.56" x2="129.54" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="129.54" y1="162.56" x2="129.54" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="129.54" y1="162.56" x2="132.08" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="132.08" y1="162.56" x2="132.08" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="132.08" y1="162.56" x2="134.62" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="134.62" y1="162.56" x2="134.62" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="134.62" y1="162.56" x2="134.62" y2="165.1" width="0.1524" layer="91"/>
+<junction x="119.38" y="162.56"/>
+<junction x="121.92" y="162.56"/>
+<junction x="124.46" y="162.56"/>
+<junction x="127" y="162.56"/>
+<junction x="129.54" y="162.56"/>
+<junction x="132.08" y="162.56"/>
+<junction x="134.62" y="162.56"/>
+<pinref part="IC1" gate="G$1" pin="VCCINT1"/>
+<pinref part="IC1" gate="G$1" pin="VCCINT2"/>
+<pinref part="IC1" gate="G$1" pin="VCCINT3"/>
+<pinref part="IC1" gate="G$1" pin="VCCINT4"/>
+<pinref part="IC1" gate="G$1" pin="VCCINT5"/>
+<pinref part="IC1" gate="G$1" pin="VCCINT6"/>
+<pinref part="IC1" gate="G$1" pin="VCCINT7"/>
+<pinref part="IC1" gate="G$1" pin="VCCINT8"/>
+<pinref part="V4" gate="G$1" pin="+2V5"/>
+</segment>
+</net>
+<net name="FPGA_TDI" class="0">
+<segment>
+<wire x1="78.74" y1="137.16" x2="83.82" y2="137.16" width="0.1524" layer="91"/>
+<label x="78.74" y="137.16" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="TDI"/>
+</segment>
+<segment>
+<wire x1="226.06" y1="60.96" x2="218.44" y2="60.96" width="0.1524" layer="91"/>
+<label x="226.06" y="60.96" size="1.778" layer="95"/>
+<pinref part="SV5" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="FPGA_TDO" class="0">
+<segment>
+<wire x1="78.74" y1="134.62" x2="83.82" y2="134.62" width="0.1524" layer="91"/>
+<label x="78.74" y="134.62" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="TDO"/>
+</segment>
+<segment>
+<wire x1="226.06" y1="58.42" x2="218.44" y2="58.42" width="0.1524" layer="91"/>
+<label x="226.06" y="58.42" size="1.778" layer="95"/>
+<pinref part="SV5" gate="G$1" pin="3"/>
+</segment>
+</net>
+<net name="FPGA_TMS" class="0">
+<segment>
+<wire x1="78.74" y1="132.08" x2="83.82" y2="132.08" width="0.1524" layer="91"/>
+<label x="78.74" y="132.08" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="TMS"/>
+</segment>
+<segment>
+<wire x1="226.06" y1="63.5" x2="218.44" y2="63.5" width="0.1524" layer="91"/>
+<label x="226.06" y="63.5" size="1.778" layer="95"/>
+<pinref part="SV5" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="FPGA_TCK" class="0">
+<segment>
+<wire x1="78.74" y1="129.54" x2="83.82" y2="129.54" width="0.1524" layer="91"/>
+<label x="78.74" y="129.54" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="TCK"/>
+</segment>
+<segment>
+<wire x1="226.06" y1="55.88" x2="218.44" y2="55.88" width="0.1524" layer="91"/>
+<label x="226.06" y="55.88" size="1.778" layer="95"/>
+<pinref part="SV5" gate="G$1" pin="4"/>
+</segment>
+</net>
+<net name="FPGA_DONE" class="0">
+<segment>
+<wire x1="78.74" y1="114.3" x2="83.82" y2="114.3" width="0.1524" layer="91"/>
+<label x="78.74" y="114.3" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="DONE"/>
+</segment>
+</net>
+<net name="FPGA_NPROGRAM" class="0">
+<segment>
+<wire x1="78.74" y1="111.76" x2="83.82" y2="111.76" width="0.1524" layer="91"/>
+<label x="78.74" y="111.76" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="/PROGRAM"/>
+</segment>
+</net>
+<net name="FPGA_CCLK" class="0">
+<segment>
+<wire x1="78.74" y1="109.22" x2="83.82" y2="109.22" width="0.1524" layer="91"/>
+<label x="78.74" y="109.22" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="CCLK"/>
+</segment>
+</net>
+<net name="FPGA_DIN" class="0">
+<segment>
+<wire x1="78.74" y1="106.68" x2="83.82" y2="106.68" width="0.1524" layer="91"/>
+<label x="78.74" y="106.68" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="DIN"/>
+</segment>
+</net>
+<net name="FPGA_DOUT" class="0">
+<segment>
+<wire x1="78.74" y1="104.14" x2="83.82" y2="104.14" width="0.1524" layer="91"/>
+<label x="78.74" y="104.14" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="DOUT"/>
+</segment>
+</net>
+<net name="+3V3-FPGA" class="0">
+<segment>
+<wire x1="30.48" y1="60.96" x2="30.48" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="81.28" x2="27.94" y2="81.28" width="0.1524" layer="91"/>
+<label x="27.94" y="81.28" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC4" gate="G$1" pin="VDD"/>
+</segment>
+<segment>
+<wire x1="93.98" y1="162.56" x2="93.98" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="93.98" y1="162.56" x2="96.52" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="96.52" y1="162.56" x2="96.52" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="96.52" y1="162.56" x2="99.06" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="99.06" y1="162.56" x2="99.06" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="99.06" y1="162.56" x2="101.6" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="101.6" y1="162.56" x2="101.6" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="101.6" y1="162.56" x2="104.14" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="104.14" y1="162.56" x2="104.14" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="104.14" y1="162.56" x2="106.68" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="106.68" y1="162.56" x2="106.68" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="106.68" y1="162.56" x2="109.22" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="109.22" y1="162.56" x2="109.22" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="109.22" y1="162.56" x2="111.76" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="111.76" y1="162.56" x2="111.76" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="111.76" y1="162.56" x2="111.76" y2="167.64" width="0.1524" layer="91"/>
+<wire x1="111.76" y1="167.64" x2="109.22" y2="167.64" width="0.1524" layer="91"/>
+<wire x1="177.8" y1="50.8" x2="175.26" y2="50.8" width="0.1524" layer="91"/>
+<wire x1="177.8" y1="50.8" x2="177.8" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="177.8" y1="53.34" x2="180.34" y2="53.34" width="0.1524" layer="91"/>
+<junction x="96.52" y="162.56"/>
+<junction x="99.06" y="162.56"/>
+<junction x="101.6" y="162.56"/>
+<junction x="104.14" y="162.56"/>
+<junction x="106.68" y="162.56"/>
+<junction x="109.22" y="162.56"/>
+<junction x="111.76" y="162.56"/>
+<label x="109.22" y="167.64" size="1.778" layer="95" rot="MR0"/>
+<label x="180.34" y="53.34" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="VCCO_B76"/>
+<pinref part="IC1" gate="G$1" pin="VCCO_B65"/>
+<pinref part="IC1" gate="G$1" pin="VCCO_B54"/>
+<pinref part="IC1" gate="G$1" pin="VCCO_B43"/>
+<pinref part="IC1" gate="G$1" pin="VCCO_B32"/>
+<pinref part="IC1" gate="G$1" pin="VCCO_B21"/>
+<pinref part="IC1" gate="G$1" pin="VCCO_B10"/>
+<pinref part="IC1" gate="G$1" pin="VCCO_B07"/>
+<pinref part="R59" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="ADC1" class="0">
+<segment>
+<wire x1="170.18" y1="149.86" x2="172.72" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="172.72" y1="152.4" x2="182.88" y2="152.4" width="0.1524" layer="91"/>
+<label x="175.26" y="152.4" size="1.778" layer="95"/>
+<pinref part="IC8" gate="G$1" pin="D1"/>
+</segment>
+<segment>
+<wire x1="154.94" y1="35.56" x2="152.4" y2="38.1" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="38.1" x2="142.24" y2="38.1" width="0.1524" layer="91"/>
+<label x="144.78" y="38.1" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P62_IO3"/>
+</segment>
+</net>
+<net name="ADC2" class="0">
+<segment>
+<wire x1="170.18" y1="147.32" x2="172.72" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="172.72" y1="149.86" x2="182.88" y2="149.86" width="0.1524" layer="91"/>
+<label x="175.26" y="149.86" size="1.778" layer="95"/>
+<pinref part="IC8" gate="G$1" pin="D2"/>
+</segment>
+<segment>
+<wire x1="154.94" y1="38.1" x2="152.4" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="40.64" x2="142.24" y2="40.64" width="0.1524" layer="91"/>
+<label x="144.78" y="40.64" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P60_IO3"/>
+</segment>
+</net>
+<net name="ADC3" class="0">
+<segment>
+<wire x1="170.18" y1="144.78" x2="172.72" y2="147.32" width="0.1524" layer="91"/>
+<wire x1="172.72" y1="147.32" x2="182.88" y2="147.32" width="0.1524" layer="91"/>
+<label x="175.26" y="147.32" size="1.778" layer="95"/>
+<pinref part="IC8" gate="G$1" pin="D3"/>
+</segment>
+<segment>
+<wire x1="154.94" y1="43.18" x2="152.4" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="45.72" x2="142.24" y2="45.72" width="0.1524" layer="91"/>
+<label x="144.78" y="45.72" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P58_IO3"/>
+</segment>
+</net>
+<net name="ADC4" class="0">
+<segment>
+<wire x1="170.18" y1="142.24" x2="172.72" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="172.72" y1="144.78" x2="182.88" y2="144.78" width="0.1524" layer="91"/>
+<label x="175.26" y="144.78" size="1.778" layer="95"/>
+<pinref part="IC8" gate="G$1" pin="D4"/>
+</segment>
+<segment>
+<wire x1="154.94" y1="45.72" x2="152.4" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="48.26" x2="142.24" y2="48.26" width="0.1524" layer="91"/>
+<label x="144.78" y="48.26" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P57_IO3"/>
+</segment>
+</net>
+<net name="ADC5" class="0">
+<segment>
+<wire x1="170.18" y1="139.7" x2="172.72" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="172.72" y1="142.24" x2="182.88" y2="142.24" width="0.1524" layer="91"/>
+<label x="175.26" y="142.24" size="1.778" layer="95"/>
+<pinref part="IC8" gate="G$1" pin="D5"/>
+</segment>
+<segment>
+<wire x1="154.94" y1="48.26" x2="152.4" y2="50.8" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="50.8" x2="142.24" y2="50.8" width="0.1524" layer="91"/>
+<label x="144.78" y="50.8" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P56_IO3"/>
+</segment>
+</net>
+<net name="ADC6" class="0">
+<segment>
+<wire x1="170.18" y1="137.16" x2="172.72" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="172.72" y1="139.7" x2="182.88" y2="139.7" width="0.1524" layer="91"/>
+<label x="175.26" y="139.7" size="1.778" layer="95"/>
+<pinref part="IC8" gate="G$1" pin="D6"/>
+</segment>
+<segment>
+<wire x1="154.94" y1="50.8" x2="152.4" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="53.34" x2="142.24" y2="53.34" width="0.1524" layer="91"/>
+<label x="144.78" y="53.34" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P55_IO3"/>
+</segment>
+</net>
+<net name="ADC7" class="0">
+<segment>
+<wire x1="170.18" y1="134.62" x2="172.72" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="172.72" y1="137.16" x2="182.88" y2="137.16" width="0.1524" layer="91"/>
+<label x="175.26" y="137.16" size="1.778" layer="95"/>
+<pinref part="IC8" gate="G$1" pin="D7"/>
+</segment>
+<segment>
+<wire x1="154.94" y1="53.34" x2="152.4" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="55.88" x2="142.24" y2="55.88" width="0.1524" layer="91"/>
+<label x="144.78" y="55.88" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P54_IOV3"/>
+</segment>
+</net>
+<net name="ADC8" class="0">
+<segment>
+<wire x1="170.18" y1="132.08" x2="172.72" y2="134.62" width="0.1524" layer="91"/>
+<wire x1="172.72" y1="134.62" x2="182.88" y2="134.62" width="0.1524" layer="91"/>
+<label x="175.26" y="134.62" size="1.778" layer="95"/>
+<pinref part="IC8" gate="G$1" pin="MSB-D8"/>
+</segment>
+<segment>
+<wire x1="154.94" y1="55.88" x2="152.4" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="58.42" x2="142.24" y2="58.42" width="0.1524" layer="91"/>
+<label x="144.78" y="58.42" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P53_IO3"/>
+</segment>
+</net>
+<net name="ADC_NOE" class="0">
+<segment>
+<wire x1="175.26" y1="129.54" x2="180.34" y2="129.54" width="0.1524" layer="91"/>
+<wire x1="180.34" y1="129.54" x2="182.88" y2="129.54" width="0.1524" layer="91"/>
+<wire x1="180.34" y1="129.54" x2="180.34" y2="119.38" width="0.1524" layer="91"/>
+<junction x="180.34" y="129.54"/>
+<label x="175.26" y="129.54" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC8" gate="G$1" pin="NOE"/>
+<pinref part="R47" gate="G$1" pin="2"/>
+</segment>
+<segment>
+<wire x1="144.78" y1="66.04" x2="142.24" y2="66.04" width="0.1524" layer="91"/>
+<label x="144.78" y="66.04" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P47_IO4"/>
+</segment>
+</net>
+<net name="ADC_CLK" class="0">
+<segment>
+<wire x1="175.26" y1="124.46" x2="182.88" y2="124.46" width="0.1524" layer="91"/>
+<label x="175.26" y="124.46" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC8" gate="G$1" pin="CLK"/>
+</segment>
+<segment>
+<wire x1="144.78" y1="68.58" x2="142.24" y2="68.58" width="0.1524" layer="91"/>
+<label x="144.78" y="68.58" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P46_IO4"/>
+</segment>
+</net>
+<net name="SSP_DIN" class="0">
+<segment>
+<wire x1="144.78" y1="93.98" x2="142.24" y2="93.98" width="0.1524" layer="91"/>
+<label x="144.78" y="93.98" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P32_IO5"/>
+</segment>
+</net>
+<net name="SSP_DOUT" class="0">
+<segment>
+<wire x1="144.78" y1="91.44" x2="142.24" y2="91.44" width="0.1524" layer="91"/>
+<label x="144.78" y="91.44" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P34_IOV5"/>
+</segment>
+</net>
+<net name="ADC_IN" class="0">
+<segment>
+<wire x1="223.52" y1="139.7" x2="220.98" y2="139.7" width="0.1524" layer="91"/>
+<label x="223.52" y="139.7" size="1.778" layer="95"/>
+<pinref part="IC8" gate="G$1" pin="ANALOGIN"/>
+</segment>
+</net>
+<net name="PWR_HI" class="0">
+<segment>
+<wire x1="81.28" y1="76.2" x2="83.82" y2="76.2" width="0.1524" layer="91"/>
+<label x="81.28" y="76.2" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="P80_IO1"/>
+</segment>
+</net>
+<net name="PWR_LO" class="0">
+<segment>
+<wire x1="81.28" y1="73.66" x2="83.82" y2="73.66" width="0.1524" layer="91"/>
+<label x="81.28" y="73.66" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="P81_IO1"/>
+</segment>
+</net>
+<net name="PWR_OE1" class="0">
+<segment>
+<wire x1="81.28" y1="71.12" x2="83.82" y2="71.12" width="0.1524" layer="91"/>
+<label x="81.28" y="71.12" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="P82_IOV1"/>
+</segment>
+</net>
+<net name="PWR_OE2" class="0">
+<segment>
+<wire x1="81.28" y1="68.58" x2="83.82" y2="68.58" width="0.1524" layer="91"/>
+<label x="81.28" y="68.58" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="P83_IO1"/>
+</segment>
+</net>
+<net name="SSP_FRAME" class="0">
+<segment>
+<wire x1="144.78" y1="96.52" x2="142.24" y2="96.52" width="0.1524" layer="91"/>
+<label x="144.78" y="96.52" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P31_IO5"/>
+</segment>
+</net>
+<net name="N$27" class="0">
+<segment>
+<wire x1="60.96" y1="93.98" x2="66.04" y2="93.98" width="0.1524" layer="91"/>
+<wire x1="66.04" y1="93.98" x2="66.04" y2="60.96" width="0.1524" layer="91"/>
+<wire x1="66.04" y1="60.96" x2="83.82" y2="60.96" width="0.1524" layer="91"/>
+<pinref part="R39" gate="G$1" pin="2"/>
+<pinref part="IC1" gate="G$1" pin="P87_IO1"/>
+</segment>
+</net>
+<net name="N$40" class="0">
+<segment>
+<wire x1="60.96" y1="86.36" x2="63.5" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="63.5" y1="86.36" x2="63.5" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="63.5" y1="58.42" x2="83.82" y2="58.42" width="0.1524" layer="91"/>
+<pinref part="R44" gate="G$1" pin="2"/>
+<pinref part="IC1" gate="G$1" pin="P88_IGCK1"/>
+</segment>
+</net>
+<net name="CROSS_LO" class="0">
+<segment>
+<wire x1="48.26" y1="93.98" x2="50.8" y2="93.98" width="0.1524" layer="91"/>
+<label x="48.26" y="93.98" size="1.778" layer="95" rot="MR0"/>
+<pinref part="R39" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="CROSS_HI" class="0">
+<segment>
+<wire x1="48.26" y1="86.36" x2="50.8" y2="86.36" width="0.1524" layer="91"/>
+<label x="48.26" y="86.36" size="1.778" layer="95" rot="MR0"/>
+<pinref part="R44" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="PWR_OE3" class="0">
+<segment>
+<wire x1="81.28" y1="66.04" x2="83.82" y2="66.04" width="0.1524" layer="91"/>
+<label x="81.28" y="66.04" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="P84_IO1"/>
+</segment>
+</net>
+<net name="PWR_OE4" class="0">
+<segment>
+<wire x1="81.28" y1="63.5" x2="83.82" y2="63.5" width="0.1524" layer="91"/>
+<label x="81.28" y="63.5" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="P86_IOV1"/>
+</segment>
+</net>
+<net name="N$55" class="0">
+<segment>
+<wire x1="142.24" y1="104.14" x2="149.86" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="149.86" y1="104.14" x2="149.86" y2="106.68" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="G$1" pin="P22_IO6"/>
+<pinref part="TP7" gate="G$1" pin="P$1"/>
+</segment>
+</net>
+<net name="N$48" class="0">
+<segment>
+<wire x1="243.84" y1="132.08" x2="243.84" y2="129.54" width="0.1524" layer="91"/>
+<wire x1="243.84" y1="129.54" x2="243.84" y2="127" width="0.1524" layer="91"/>
+<wire x1="233.68" y1="129.54" x2="220.98" y2="129.54" width="0.1524" layer="91"/>
+<wire x1="233.68" y1="129.54" x2="233.68" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="243.84" y1="129.54" x2="233.68" y2="129.54" width="0.1524" layer="91"/>
+<junction x="243.84" y="129.54"/>
+<junction x="233.68" y="129.54"/>
+<pinref part="R52" gate="G$1" pin="1"/>
+<pinref part="R53" gate="G$1" pin="2"/>
+<pinref part="IC8" gate="G$1" pin="REFT"/>
+<pinref part="C19" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="SSP_CLK" class="0">
+<segment>
+<wire x1="81.28" y1="83.82" x2="83.82" y2="83.82" width="0.1524" layer="91"/>
+<label x="81.28" y="83.82" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC1" gate="G$1" pin="P71_IO2"/>
+</segment>
+</net>
+<net name="PCK0" class="0">
+<segment>
+<wire x1="144.78" y1="88.9" x2="142.24" y2="88.9" width="0.1524" layer="91"/>
+<label x="144.78" y="88.9" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P36_IGCK5"/>
+</segment>
+</net>
+<net name="FPGA_NINIT" class="0">
+<segment>
+<wire x1="167.64" y1="60.96" x2="160.02" y2="60.96" width="0.1524" layer="91"/>
+<wire x1="160.02" y1="60.96" x2="142.24" y2="60.96" width="0.1524" layer="91"/>
+<wire x1="165.1" y1="50.8" x2="160.02" y2="50.8" width="0.1524" layer="91"/>
+<wire x1="160.02" y1="50.8" x2="160.02" y2="60.96" width="0.1524" layer="91"/>
+<junction x="160.02" y="60.96"/>
+<label x="167.64" y="60.96" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="P52_IO3"/>
+<pinref part="R59" gate="G$1" pin="1"/>
+</segment>
+</net>
+</nets>
+</sheet>
+<sheet>
+<plain>
+<text x="165.1" y="17.78" size="2.54" layer="95">ARM micro and support</text>
+</plain>
+<instances>
+<instance part="FRAME3" gate="G$1" x="0" y="0"/>
+<instance part="IC2" gate="G$1" x="144.78" y="132.08"/>
+<instance part="V5" gate="GND" x="124.46" y="38.1"/>
+<instance part="U$2" gate="G$1" x="104.14" y="147.32"/>
+<instance part="R3" gate="G$1" x="71.12" y="127"/>
+<instance part="C4" gate="G$1" x="58.42" y="127" rot="R90"/>
+<instance part="C5" gate="G$1" x="58.42" y="137.16" rot="R90"/>
+<instance part="V8" gate="GND" x="48.26" y="121.92" rot="MR0"/>
+<instance part="XT2" gate="G$1" x="76.2" y="81.28" smashed="yes" rot="R90">
+<attribute name="NAME" x="75.0156" y="84.0901" size="1.778" layer="95" rot="R90"/>
+</instance>
+<instance part="C6" gate="G$1" x="66.04" y="91.44" rot="R90"/>
+<instance part="C7" gate="G$1" x="66.04" y="81.28" rot="R90"/>
+<instance part="V9" gate="GND" x="55.88" y="76.2" rot="MR0"/>
+<instance part="R4" gate="G$1" x="38.1" y="66.04"/>
+<instance part="R5" gate="G$1" x="38.1" y="58.42"/>
+<instance part="R6" gate="G$1" x="45.72" y="73.66" rot="R90"/>
+<instance part="C8" gate="G$1" x="144.78" y="149.86" rot="MR0"/>
+<instance part="C9" gate="G$1" x="154.94" y="149.86" rot="MR0"/>
+<instance part="V10" gate="GND" x="154.94" y="139.7"/>
+<instance part="SV3" gate="G$1" x="215.9" y="137.16" rot="R180"/>
+<instance part="V11" gate="GND" x="228.6" y="119.38"/>
+<instance part="U$6" gate="G$1" x="203.2" y="162.56"/>
+<instance part="R7" gate="G$1" x="203.2" y="149.86" rot="R90"/>
+<instance part="V12" gate="GND" x="27.94" y="96.52" rot="MR0"/>
+<instance part="R8" gate="G$1" x="58.42" y="114.3"/>
+<instance part="U$7" gate="G$1" x="27.94" y="132.08"/>
+<instance part="D4" gate="G$1" x="210.82" y="63.5" rot="R90"/>
+<instance part="D5" gate="G$1" x="210.82" y="55.88" rot="R90"/>
+<instance part="D6" gate="G$1" x="210.82" y="48.26" rot="R90"/>
+<instance part="R24" gate="G$1" x="198.12" y="63.5"/>
+<instance part="R25" gate="G$1" x="198.12" y="55.88"/>
+<instance part="R26" gate="G$1" x="198.12" y="48.26"/>
+<instance part="V40" gate="GND" x="218.44" y="33.02"/>
+<instance part="R43" gate="G$1" x="236.22" y="81.28" rot="R90"/>
+<instance part="U$9" gate="G$1" x="236.22" y="91.44" rot="MR0"/>
+<instance part="SW1" gate="G$1" x="236.22" y="60.96" rot="R90"/>
+<instance part="V50" gate="GND" x="236.22" y="50.8"/>
+<instance part="D9" gate="G$1" x="210.82" y="40.64" rot="R90"/>
+<instance part="R55" gate="G$1" x="198.12" y="40.64"/>
+<instance part="TP8" gate="G$1" x="185.42" y="35.56" rot="R90"/>
+<instance part="IC7" gate="G$1" x="38.1" y="121.92"/>
+</instances>
+<busses>
+<bus name="NCS,SPCK,MISO,MOSI">
+<segment>
+<wire x1="172.72" y1="101.6" x2="172.72" y2="93.98" width="0.762" layer="92"/>
+<wire x1="172.72" y1="93.98" x2="175.26" y2="91.44" width="0.762" layer="92"/>
+<label x="175.26" y="91.44" size="1.778" layer="95"/>
+</segment>
+</bus>
+</busses>
+<nets>
+<net name="GND" class="0">
+<segment>
+<wire x1="124.46" y1="45.72" x2="124.46" y2="43.18" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="43.18" x2="124.46" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="43.18" x2="121.92" y2="43.18" width="0.1524" layer="91"/>
+<wire x1="121.92" y1="43.18" x2="121.92" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="121.92" y1="43.18" x2="119.38" y2="43.18" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="43.18" x2="119.38" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="43.18" x2="116.84" y2="43.18" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="43.18" x2="116.84" y2="45.72" width="0.1524" layer="91"/>
+<junction x="124.46" y="43.18"/>
+<junction x="121.92" y="43.18"/>
+<junction x="119.38" y="43.18"/>
+<pinref part="IC2" gate="G$1" pin="GND0"/>
+<pinref part="V5" gate="GND" pin="GND"/>
+<pinref part="IC2" gate="G$1" pin="GND1"/>
+<pinref part="IC2" gate="G$1" pin="GND2"/>
+<pinref part="IC2" gate="G$1" pin="GND3"/>
+</segment>
+<segment>
+<wire x1="53.34" y1="127" x2="48.26" y2="127" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="127" x2="48.26" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="53.34" y1="137.16" x2="48.26" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="137.16" x2="48.26" y2="127" width="0.1524" layer="91"/>
+<junction x="48.26" y="127"/>
+<pinref part="C4" gate="G$1" pin="1"/>
+<pinref part="V8" gate="GND" pin="GND"/>
+<pinref part="C5" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<wire x1="60.96" y1="91.44" x2="55.88" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="55.88" y1="91.44" x2="55.88" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="55.88" y1="81.28" x2="55.88" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="81.28" x2="55.88" y2="81.28" width="0.1524" layer="91"/>
+<junction x="55.88" y="81.28"/>
+<pinref part="C6" gate="G$1" pin="1"/>
+<pinref part="V9" gate="GND" pin="GND"/>
+<pinref part="C7" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<wire x1="154.94" y1="147.32" x2="154.94" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="144.78" x2="154.94" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="144.78" x2="144.78" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="144.78" y1="144.78" x2="144.78" y2="147.32" width="0.1524" layer="91"/>
+<junction x="154.94" y="144.78"/>
+<pinref part="C9" gate="G$1" pin="2"/>
+<pinref part="V10" gate="GND" pin="GND"/>
+<pinref part="C8" gate="G$1" pin="2"/>
+</segment>
+<segment>
+<wire x1="226.06" y1="144.78" x2="228.6" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="228.6" y1="144.78" x2="228.6" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="228.6" y1="142.24" x2="228.6" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="228.6" y1="139.7" x2="228.6" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="228.6" y1="137.16" x2="228.6" y2="134.62" width="0.1524" layer="91"/>
+<wire x1="228.6" y1="134.62" x2="228.6" y2="132.08" width="0.1524" layer="91"/>
+<wire x1="228.6" y1="132.08" x2="228.6" y2="129.54" width="0.1524" layer="91"/>
+<wire x1="228.6" y1="129.54" x2="228.6" y2="127" width="0.1524" layer="91"/>
+<wire x1="228.6" y1="127" x2="228.6" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="228.6" y1="124.46" x2="228.6" y2="121.92" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="124.46" x2="228.6" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="127" x2="228.6" y2="127" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="129.54" x2="228.6" y2="129.54" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="132.08" x2="228.6" y2="132.08" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="134.62" x2="228.6" y2="134.62" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="137.16" x2="228.6" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="139.7" x2="228.6" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="142.24" x2="228.6" y2="142.24" width="0.1524" layer="91"/>
+<junction x="228.6" y="124.46"/>
+<junction x="228.6" y="127"/>
+<junction x="228.6" y="129.54"/>
+<junction x="228.6" y="132.08"/>
+<junction x="228.6" y="134.62"/>
+<junction x="228.6" y="137.16"/>
+<junction x="228.6" y="139.7"/>
+<junction x="228.6" y="142.24"/>
+<pinref part="SV3" gate="G$1" pin="4"/>
+<pinref part="V11" gate="GND" pin="GND"/>
+<pinref part="SV3" gate="G$1" pin="20"/>
+<pinref part="SV3" gate="G$1" pin="18"/>
+<pinref part="SV3" gate="G$1" pin="16"/>
+<pinref part="SV3" gate="G$1" pin="14"/>
+<pinref part="SV3" gate="G$1" pin="12"/>
+<pinref part="SV3" gate="G$1" pin="10"/>
+<pinref part="SV3" gate="G$1" pin="8"/>
+<pinref part="SV3" gate="G$1" pin="6"/>
+</segment>
+<segment>
+<wire x1="27.94" y1="101.6" x2="27.94" y2="99.06" width="0.1524" layer="91"/>
+<pinref part="V12" gate="GND" pin="GND"/>
+<pinref part="IC7" gate="G$1" pin="V-"/>
+</segment>
+<segment>
+<wire x1="213.36" y1="63.5" x2="218.44" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="218.44" y1="63.5" x2="218.44" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="218.44" y1="55.88" x2="218.44" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="218.44" y1="48.26" x2="218.44" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="218.44" y1="40.64" x2="218.44" y2="35.56" width="0.1524" layer="91"/>
+<wire x1="213.36" y1="55.88" x2="218.44" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="213.36" y1="48.26" x2="218.44" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="213.36" y1="40.64" x2="218.44" y2="40.64" width="0.1524" layer="91"/>
+<junction x="218.44" y="55.88"/>
+<junction x="218.44" y="48.26"/>
+<junction x="218.44" y="40.64"/>
+<pinref part="D4" gate="G$1" pin="C"/>
+<pinref part="V40" gate="GND" pin="GND"/>
+<pinref part="D5" gate="G$1" pin="C"/>
+<pinref part="D6" gate="G$1" pin="C"/>
+<pinref part="D9" gate="G$1" pin="C"/>
+</segment>
+<segment>
+<wire x1="236.22" y1="55.88" x2="236.22" y2="53.34" width="0.1524" layer="91"/>
+<pinref part="SW1" gate="G$1" pin="P$1"/>
+<pinref part="V50" gate="GND" pin="GND"/>
+</segment>
+</net>
+<net name="+3V3" class="0">
+<segment>
+<wire x1="104.14" y1="144.78" x2="104.14" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="104.14" y1="142.24" x2="104.14" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="104.14" y1="142.24" x2="106.68" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="106.68" y1="142.24" x2="106.68" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="106.68" y1="142.24" x2="109.22" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="109.22" y1="142.24" x2="109.22" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="109.22" y1="142.24" x2="111.76" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="111.76" y1="142.24" x2="111.76" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="111.76" y1="142.24" x2="114.3" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="114.3" y1="142.24" x2="114.3" y2="139.7" width="0.1524" layer="91"/>
+<junction x="104.14" y="142.24"/>
+<junction x="106.68" y="142.24"/>
+<junction x="109.22" y="142.24"/>
+<junction x="111.76" y="142.24"/>
+<pinref part="U$2" gate="G$1" pin="+3V3"/>
+<pinref part="IC2" gate="G$1" pin="VDDIO0"/>
+<pinref part="IC2" gate="G$1" pin="VDDIO1"/>
+<pinref part="IC2" gate="G$1" pin="VDDIO2"/>
+<pinref part="IC2" gate="G$1" pin="VDDFLASH"/>
+<pinref part="IC2" gate="G$1" pin="VDDIN"/>
+</segment>
+<segment>
+<wire x1="81.28" y1="68.58" x2="83.82" y2="68.58" width="0.1524" layer="91"/>
+<label x="81.28" y="68.58" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC2" gate="G$1" pin="ADVREF"/>
+</segment>
+<segment>
+<wire x1="210.82" y1="147.32" x2="208.28" y2="147.32" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="147.32" x2="208.28" y2="157.48" width="0.1524" layer="91"/>
+<wire x1="203.2" y1="160.02" x2="203.2" y2="157.48" width="0.1524" layer="91"/>
+<wire x1="203.2" y1="157.48" x2="203.2" y2="154.94" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="157.48" x2="203.2" y2="157.48" width="0.1524" layer="91"/>
+<junction x="203.2" y="157.48"/>
+<pinref part="SV3" gate="G$1" pin="1"/>
+<pinref part="U$6" gate="G$1" pin="+3V3"/>
+<pinref part="R7" gate="G$1" pin="2"/>
+</segment>
+<segment>
+<wire x1="27.94" y1="129.54" x2="27.94" y2="127" width="0.1524" layer="91"/>
+<pinref part="U$7" gate="G$1" pin="+3V3"/>
+<pinref part="IC7" gate="G$1" pin="V+"/>
+</segment>
+<segment>
+<wire x1="236.22" y1="88.9" x2="236.22" y2="86.36" width="0.1524" layer="91"/>
+<pinref part="U$9" gate="G$1" pin="+3V3"/>
+<pinref part="R43" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$2" class="0">
+<segment>
+<wire x1="60.96" y1="137.16" x2="78.74" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="78.74" y1="137.16" x2="78.74" y2="127" width="0.1524" layer="91"/>
+<wire x1="78.74" y1="127" x2="83.82" y2="127" width="0.1524" layer="91"/>
+<wire x1="78.74" y1="127" x2="76.2" y2="127" width="0.1524" layer="91"/>
+<junction x="78.74" y="127"/>
+<pinref part="C5" gate="G$1" pin="2"/>
+<pinref part="IC2" gate="G$1" pin="PLLRC"/>
+<pinref part="R3" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$6" class="0">
+<segment>
+<wire x1="66.04" y1="127" x2="60.96" y2="127" width="0.1524" layer="91"/>
+<pinref part="R3" gate="G$1" pin="1"/>
+<pinref part="C4" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$7" class="0">
+<segment>
+<wire x1="83.82" y1="91.44" x2="78.74" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="78.74" y1="91.44" x2="68.58" y2="91.44" width="0.1524" layer="91"/>
+<junction x="78.74" y="91.44"/>
+<pinref part="IC2" gate="G$1" pin="XOUT"/>
+<pinref part="XT2" gate="G$1" pin="B"/>
+<pinref part="C6" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$8" class="0">
+<segment>
+<wire x1="68.58" y1="81.28" x2="78.74" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="78.74" y1="81.28" x2="83.82" y2="81.28" width="0.1524" layer="91"/>
+<junction x="78.74" y="81.28"/>
+<pinref part="C7" gate="G$1" pin="2"/>
+<pinref part="XT2" gate="G$1" pin="A"/>
+<pinref part="IC2" gate="G$1" pin="XIN/PGMCK"/>
+</segment>
+</net>
+<net name="N$11" class="0">
+<segment>
+<wire x1="43.18" y1="66.04" x2="63.5" y2="66.04" width="0.1524" layer="91"/>
+<wire x1="63.5" y1="66.04" x2="63.5" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="63.5" y1="76.2" x2="83.82" y2="76.2" width="0.1524" layer="91"/>
+<pinref part="R4" gate="G$1" pin="2"/>
+<pinref part="IC2" gate="G$1" pin="DDM"/>
+</segment>
+</net>
+<net name="N$12" class="0">
+<segment>
+<wire x1="83.82" y1="73.66" x2="66.04" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="66.04" y1="73.66" x2="66.04" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="66.04" y1="58.42" x2="45.72" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="58.42" x2="43.18" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="68.58" x2="45.72" y2="58.42" width="0.1524" layer="91"/>
+<junction x="45.72" y="58.42"/>
+<pinref part="IC2" gate="G$1" pin="DDP"/>
+<pinref part="R5" gate="G$1" pin="2"/>
+<pinref part="R6" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="USB_PU" class="0">
+<segment>
+<wire x1="45.72" y1="78.74" x2="45.72" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="81.28" x2="43.18" y2="81.28" width="0.1524" layer="91"/>
+<label x="43.18" y="81.28" size="1.778" layer="95" rot="MR0"/>
+<pinref part="R6" gate="G$1" pin="2"/>
+</segment>
+<segment>
+<wire x1="152.4" y1="71.12" x2="149.86" y2="71.12" width="0.1524" layer="91"/>
+<label x="152.4" y="71.12" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA24"/>
+</segment>
+</net>
+<net name="USB_D-" class="0">
+<segment>
+<wire x1="30.48" y1="66.04" x2="33.02" y2="66.04" width="0.1524" layer="91"/>
+<label x="30.48" y="66.04" size="1.778" layer="95" rot="MR0"/>
+<pinref part="R4" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="USB_D+" class="0">
+<segment>
+<wire x1="30.48" y1="58.42" x2="33.02" y2="58.42" width="0.1524" layer="91"/>
+<label x="30.48" y="58.42" size="1.778" layer="95" rot="MR0"/>
+<pinref part="R5" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$10" class="0">
+<segment>
+<wire x1="132.08" y1="142.24" x2="132.08" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="129.54" y1="142.24" x2="132.08" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="129.54" y1="139.7" x2="129.54" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="127" y1="142.24" x2="129.54" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="127" y1="139.7" x2="127" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="142.24" x2="127" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="139.7" x2="124.46" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="121.92" y1="142.24" x2="124.46" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="121.92" y1="142.24" x2="121.92" y2="139.7" width="0.1524" layer="91"/>
+<wire x1="132.08" y1="142.24" x2="132.08" y2="157.48" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="154.94" x2="154.94" y2="157.48" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="157.48" x2="144.78" y2="157.48" width="0.1524" layer="91"/>
+<wire x1="144.78" y1="157.48" x2="144.78" y2="154.94" width="0.1524" layer="91"/>
+<wire x1="132.08" y1="157.48" x2="144.78" y2="157.48" width="0.1524" layer="91"/>
+<junction x="129.54" y="142.24"/>
+<junction x="127" y="142.24"/>
+<junction x="124.46" y="142.24"/>
+<junction x="132.08" y="142.24"/>
+<junction x="144.78" y="157.48"/>
+<pinref part="IC2" gate="G$1" pin="VDDOUT"/>
+<pinref part="IC2" gate="G$1" pin="VDDCORE2"/>
+<pinref part="IC2" gate="G$1" pin="VDDCORE1"/>
+<pinref part="IC2" gate="G$1" pin="VDDCORE0"/>
+<pinref part="IC2" gate="G$1" pin="VDDPLL"/>
+<pinref part="C8" gate="G$1" pin="1"/>
+<pinref part="C9" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="ARM_TMS" class="0">
+<segment>
+<wire x1="81.28" y1="111.76" x2="83.82" y2="111.76" width="0.1524" layer="91"/>
+<label x="81.28" y="111.76" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC2" gate="G$1" pin="TMS"/>
+</segment>
+<segment>
+<wire x1="198.12" y1="139.7" x2="210.82" y2="139.7" width="0.1524" layer="91"/>
+<label x="198.12" y="139.7" size="1.778" layer="95" rot="MR0"/>
+<pinref part="SV3" gate="G$1" pin="7"/>
+</segment>
+</net>
+<net name="ARM_TCK" class="0">
+<segment>
+<wire x1="81.28" y1="109.22" x2="83.82" y2="109.22" width="0.1524" layer="91"/>
+<label x="81.28" y="109.22" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC2" gate="G$1" pin="TCK"/>
+</segment>
+<segment>
+<wire x1="198.12" y1="137.16" x2="203.2" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="203.2" y1="137.16" x2="210.82" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="203.2" y1="144.78" x2="203.2" y2="137.16" width="0.1524" layer="91"/>
+<junction x="203.2" y="137.16"/>
+<label x="198.12" y="137.16" size="1.778" layer="95" rot="MR0"/>
+<pinref part="SV3" gate="G$1" pin="9"/>
+<pinref part="R7" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="ARM_TDO" class="0">
+<segment>
+<wire x1="81.28" y1="106.68" x2="83.82" y2="106.68" width="0.1524" layer="91"/>
+<label x="81.28" y="106.68" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC2" gate="G$1" pin="TDO"/>
+</segment>
+<segment>
+<wire x1="198.12" y1="132.08" x2="210.82" y2="132.08" width="0.1524" layer="91"/>
+<label x="198.12" y="132.08" size="1.778" layer="95" rot="MR0"/>
+<pinref part="SV3" gate="G$1" pin="13"/>
+</segment>
+</net>
+<net name="ARM_TDI" class="0">
+<segment>
+<wire x1="81.28" y1="104.14" x2="83.82" y2="104.14" width="0.1524" layer="91"/>
+<label x="81.28" y="104.14" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC2" gate="G$1" pin="TDI"/>
+</segment>
+<segment>
+<wire x1="198.12" y1="142.24" x2="210.82" y2="142.24" width="0.1524" layer="91"/>
+<label x="198.12" y="142.24" size="1.778" layer="95" rot="MR0"/>
+<pinref part="SV3" gate="G$1" pin="5"/>
+</segment>
+</net>
+<net name="N$9" class="0">
+<segment>
+<wire x1="63.5" y1="114.3" x2="83.82" y2="114.3" width="0.1524" layer="91"/>
+<pinref part="R8" gate="G$1" pin="2"/>
+<pinref part="IC2" gate="G$1" pin="NRST"/>
+</segment>
+</net>
+<net name="N$13" class="0">
+<segment>
+<wire x1="53.34" y1="114.3" x2="40.64" y2="114.3" width="0.1524" layer="91"/>
+<pinref part="R8" gate="G$1" pin="1"/>
+<pinref part="IC7" gate="G$1" pin="OUT"/>
+</segment>
+</net>
+<net name="NCS" class="0">
+<segment>
+<wire x1="172.72" y1="101.6" x2="170.18" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="104.14" x2="149.86" y2="104.14" width="0.1524" layer="91"/>
+<label x="152.4" y="104.14" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA11"/>
+</segment>
+</net>
+<net name="MISO" class="0">
+<segment>
+<wire x1="172.72" y1="99.06" x2="170.18" y2="101.6" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="101.6" x2="149.86" y2="101.6" width="0.1524" layer="91"/>
+<label x="152.4" y="101.6" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA12"/>
+</segment>
+</net>
+<net name="MOSI" class="0">
+<segment>
+<wire x1="172.72" y1="96.52" x2="170.18" y2="99.06" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="99.06" x2="149.86" y2="99.06" width="0.1524" layer="91"/>
+<label x="152.4" y="99.06" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA13"/>
+</segment>
+</net>
+<net name="SPCK" class="0">
+<segment>
+<wire x1="172.72" y1="93.98" x2="170.18" y2="96.52" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="96.52" x2="149.86" y2="96.52" width="0.1524" layer="91"/>
+<label x="152.4" y="96.52" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA14"/>
+</segment>
+</net>
+<net name="N$28" class="0">
+<segment>
+<wire x1="203.2" y1="48.26" x2="205.74" y2="48.26" width="0.1524" layer="91"/>
+<pinref part="R26" gate="G$1" pin="2"/>
+<pinref part="D6" gate="G$1" pin="A"/>
+</segment>
+</net>
+<net name="N$29" class="0">
+<segment>
+<wire x1="203.2" y1="55.88" x2="205.74" y2="55.88" width="0.1524" layer="91"/>
+<pinref part="R25" gate="G$1" pin="2"/>
+<pinref part="D5" gate="G$1" pin="A"/>
+</segment>
+</net>
+<net name="N$30" class="0">
+<segment>
+<wire x1="203.2" y1="63.5" x2="205.74" y2="63.5" width="0.1524" layer="91"/>
+<pinref part="R24" gate="G$1" pin="2"/>
+<pinref part="D4" gate="G$1" pin="A"/>
+</segment>
+</net>
+<net name="AMPL_LO" class="0">
+<segment>
+<wire x1="81.28" y1="66.04" x2="83.82" y2="66.04" width="0.1524" layer="91"/>
+<label x="81.28" y="66.04" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC2" gate="G$1" pin="AD4"/>
+</segment>
+</net>
+<net name="AMPL_HI" class="0">
+<segment>
+<wire x1="81.28" y1="63.5" x2="83.82" y2="63.5" width="0.1524" layer="91"/>
+<label x="81.28" y="63.5" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC2" gate="G$1" pin="AD5"/>
+</segment>
+</net>
+<net name="BUTTON_A" class="0">
+<segment>
+<wire x1="149.86" y1="73.66" x2="152.4" y2="73.66" width="0.1524" layer="91"/>
+<label x="152.4" y="73.66" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA23"/>
+</segment>
+<segment>
+<wire x1="236.22" y1="71.12" x2="236.22" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="236.22" y1="73.66" x2="236.22" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="236.22" y1="73.66" x2="228.6" y2="73.66" width="0.1524" layer="91"/>
+<junction x="236.22" y="73.66"/>
+<label x="228.6" y="73.66" size="1.778" layer="95" rot="MR0"/>
+<pinref part="SW1" gate="G$1" pin="P$2"/>
+<pinref part="R43" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="LED_A" class="0">
+<segment>
+<wire x1="152.4" y1="132.08" x2="149.86" y2="132.08" width="0.1524" layer="91"/>
+<label x="152.4" y="132.08" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA0"/>
+</segment>
+<segment>
+<wire x1="190.5" y1="63.5" x2="193.04" y2="63.5" width="0.1524" layer="91"/>
+<label x="190.5" y="63.5" size="1.778" layer="95" rot="MR0"/>
+<pinref part="R24" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="LED_B" class="0">
+<segment>
+<wire x1="152.4" y1="111.76" x2="149.86" y2="111.76" width="0.1524" layer="91"/>
+<label x="152.4" y="111.76" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA8"/>
+</segment>
+<segment>
+<wire x1="190.5" y1="55.88" x2="193.04" y2="55.88" width="0.1524" layer="91"/>
+<label x="190.5" y="55.88" size="1.778" layer="95" rot="MR0"/>
+<pinref part="R25" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="LED_C" class="0">
+<segment>
+<wire x1="152.4" y1="109.22" x2="149.86" y2="109.22" width="0.1524" layer="91"/>
+<label x="152.4" y="109.22" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA9"/>
+</segment>
+<segment>
+<wire x1="190.5" y1="48.26" x2="193.04" y2="48.26" width="0.1524" layer="91"/>
+<label x="190.5" y="48.26" size="1.778" layer="95" rot="MR0"/>
+<pinref part="R26" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="SSP_DIN" class="0">
+<segment>
+<wire x1="152.4" y1="86.36" x2="149.86" y2="86.36" width="0.1524" layer="91"/>
+<label x="152.4" y="86.36" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA18/AD1"/>
+</segment>
+</net>
+<net name="SSP_DOUT" class="0">
+<segment>
+<wire x1="152.4" y1="88.9" x2="149.86" y2="88.9" width="0.1524" layer="91"/>
+<label x="152.4" y="88.9" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA17/AD0"/>
+</segment>
+</net>
+<net name="FPGA_DONE" class="0">
+<segment>
+<wire x1="152.4" y1="63.5" x2="149.86" y2="63.5" width="0.1524" layer="91"/>
+<label x="152.4" y="63.5" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA27"/>
+</segment>
+</net>
+<net name="FPGA_NPROGRAM" class="0">
+<segment>
+<wire x1="152.4" y1="60.96" x2="149.86" y2="60.96" width="0.1524" layer="91"/>
+<label x="152.4" y="60.96" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA28"/>
+</segment>
+</net>
+<net name="FPGA_CCLK" class="0">
+<segment>
+<wire x1="152.4" y1="58.42" x2="149.86" y2="58.42" width="0.1524" layer="91"/>
+<label x="152.4" y="58.42" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA29"/>
+</segment>
+</net>
+<net name="FPGA_DIN" class="0">
+<segment>
+<wire x1="152.4" y1="55.88" x2="149.86" y2="55.88" width="0.1524" layer="91"/>
+<label x="152.4" y="55.88" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA30"/>
+</segment>
+</net>
+<net name="FPGA_DOUT" class="0">
+<segment>
+<wire x1="152.4" y1="53.34" x2="149.86" y2="53.34" width="0.1524" layer="91"/>
+<label x="152.4" y="53.34" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA31"/>
+</segment>
+</net>
+<net name="FPGA_ON" class="0">
+<segment>
+<wire x1="152.4" y1="66.04" x2="149.86" y2="66.04" width="0.1524" layer="91"/>
+<label x="152.4" y="66.04" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA26"/>
+</segment>
+</net>
+<net name="RELAY_ON" class="0">
+<segment>
+<wire x1="152.4" y1="68.58" x2="149.86" y2="68.58" width="0.1524" layer="91"/>
+<label x="152.4" y="68.58" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA25"/>
+</segment>
+</net>
+<net name="SSP_CLK" class="0">
+<segment>
+<wire x1="152.4" y1="91.44" x2="149.86" y2="91.44" width="0.1524" layer="91"/>
+<label x="152.4" y="91.44" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA16"/>
+</segment>
+</net>
+<net name="SSP_FRAME" class="0">
+<segment>
+<wire x1="152.4" y1="93.98" x2="149.86" y2="93.98" width="0.1524" layer="91"/>
+<label x="152.4" y="93.98" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA15"/>
+</segment>
+</net>
+<net name="MUXSEL_HIPKD" class="0">
+<segment>
+<wire x1="152.4" y1="83.82" x2="149.86" y2="83.82" width="0.1524" layer="91"/>
+<label x="152.4" y="83.82" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA19/AD2"/>
+</segment>
+</net>
+<net name="MUXSEL_LOPKD" class="0">
+<segment>
+<wire x1="152.4" y1="81.28" x2="149.86" y2="81.28" width="0.1524" layer="91"/>
+<label x="152.4" y="81.28" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA20/AD3"/>
+</segment>
+</net>
+<net name="MUXSEL_HIRAW" class="0">
+<segment>
+<wire x1="152.4" y1="78.74" x2="149.86" y2="78.74" width="0.1524" layer="91"/>
+<label x="152.4" y="78.74" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA21"/>
+</segment>
+</net>
+<net name="MUXSEL_LORAW" class="0">
+<segment>
+<wire x1="152.4" y1="76.2" x2="149.86" y2="76.2" width="0.1524" layer="91"/>
+<label x="152.4" y="76.2" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA22"/>
+</segment>
+</net>
+<net name="PCK0" class="0">
+<segment>
+<wire x1="152.4" y1="116.84" x2="149.86" y2="116.84" width="0.1524" layer="91"/>
+<label x="152.4" y="116.84" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA6"/>
+</segment>
+</net>
+<net name="LED_D" class="0">
+<segment>
+<wire x1="152.4" y1="127" x2="149.86" y2="127" width="0.1524" layer="91"/>
+<label x="152.4" y="127" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA2"/>
+</segment>
+<segment>
+<wire x1="187.96" y1="35.56" x2="190.5" y2="35.56" width="0.1524" layer="91"/>
+<wire x1="193.04" y1="40.64" x2="190.5" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="190.5" y1="40.64" x2="187.96" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="190.5" y1="35.56" x2="190.5" y2="40.64" width="0.1524" layer="91"/>
+<junction x="190.5" y="40.64"/>
+<label x="187.96" y="40.64" size="1.778" layer="95" rot="MR0"/>
+<pinref part="TP8" gate="G$1" pin="P$1"/>
+<pinref part="R55" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$25" class="0">
+<segment>
+<wire x1="203.2" y1="40.64" x2="205.74" y2="40.64" width="0.1524" layer="91"/>
+<pinref part="R55" gate="G$1" pin="2"/>
+<pinref part="D9" gate="G$1" pin="A"/>
+</segment>
+</net>
+<net name="NVDD_ON" class="0">
+<segment>
+<wire x1="152.4" y1="124.46" x2="149.86" y2="124.46" width="0.1524" layer="91"/>
+<label x="152.4" y="124.46" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA3"/>
+</segment>
+</net>
+<net name="FPGA_NINIT" class="0">
+<segment>
+<wire x1="152.4" y1="121.92" x2="149.86" y2="121.92" width="0.1524" layer="91"/>
+<label x="152.4" y="121.92" size="1.778" layer="95"/>
+<pinref part="IC2" gate="G$1" pin="PA4"/>
+</segment>
+</net>
+</nets>
+</sheet>
+<sheet>
+<plain>
+<text x="165.1" y="17.78" size="2.54" layer="95">analog rx path</text>
+<text x="35.56" y="33.02" size="1.778" layer="95" rot="R180">D2, D3 are BAR18</text>
+</plain>
+<instances>
+<instance part="FRAME4" gate="G$1" x="0" y="0"/>
+<instance part="IC6" gate="A" x="208.28" y="152.4" rot="MR180"/>
+<instance part="IC6" gate="B" x="101.6" y="129.54" rot="MR180"/>
+<instance part="IC6" gate="C" x="132.08" y="43.18" rot="MR180"/>
+<instance part="IC6" gate="D" x="177.8" y="43.18" rot="MR180"/>
+<instance part="IC6" gate="P" x="238.76" y="116.84"/>
+<instance part="R9" gate="G$1" x="195.58" y="157.48" rot="R90"/>
+<instance part="R10" gate="G$1" x="195.58" y="142.24" rot="R90"/>
+<instance part="V13" gate="G$1" x="238.76" y="157.48" rot="R270"/>
+<instance part="V14" gate="GND" x="195.58" y="132.08"/>
+<instance part="C10" gate="G$1" x="231.14" y="142.24"/>
+<instance part="V15" gate="GND" x="241.3" y="132.08"/>
+<instance part="D1" gate="G$1" x="38.1" y="127"/>
+<instance part="R11" gate="G$1" x="60.96" y="119.38" rot="R90"/>
+<instance part="C11" gate="G$1" x="48.26" y="119.38"/>
+<instance part="C12" gate="G$1" x="83.82" y="127" rot="R90"/>
+<instance part="R12" gate="G$1" x="88.9" y="119.38" rot="R90"/>
+<instance part="V16" gate="G$1" x="93.98" y="111.76" rot="MR90"/>
+<instance part="R13" gate="G$1" x="86.36" y="142.24"/>
+<instance part="V17" gate="G$1" x="76.2" y="142.24" rot="R90"/>
+<instance part="R14" gate="G$1" x="104.14" y="142.24"/>
+<instance part="C13" gate="G$1" x="109.22" y="149.86" rot="R90"/>
+<instance part="V18" gate="GND" x="60.96" y="106.68"/>
+<instance part="D2" gate="G$1" x="50.8" y="40.64"/>
+<instance part="C14" gate="G$1" x="38.1" y="40.64" rot="R90"/>
+<instance part="D3" gate="G$1" x="43.18" y="30.48" rot="R90"/>
+<instance part="V19" gate="GND" x="78.74" y="17.78"/>
+<instance part="C15" gate="G$1" x="66.04" y="30.48"/>
+<instance part="R15" gate="G$1" x="78.74" y="30.48" rot="R90"/>
+<instance part="R16" gate="G$1" x="88.9" y="40.64"/>
+<instance part="C16" gate="G$1" x="101.6" y="40.64" rot="R90"/>
+<instance part="R17" gate="G$1" x="119.38" y="30.48" rot="R90"/>
+<instance part="V20" gate="G$1" x="134.62" y="22.86" rot="MR90"/>
+<instance part="R18" gate="G$1" x="132.08" y="55.88"/>
+<instance part="C17" gate="G$1" x="137.16" y="63.5" rot="R90"/>
+<instance part="R19" gate="G$1" x="116.84" y="53.34"/>
+<instance part="V21" gate="G$1" x="106.68" y="53.34" rot="R90"/>
+<instance part="V22" gate="GND" x="68.58" y="152.4" rot="MR0"/>
+<instance part="R20" gate="G$1" x="60.96" y="162.56"/>
+<instance part="V23" gate="GND" x="238.76" y="91.44"/>
+<instance part="VDD2" gate="G$1" x="215.9" y="129.54"/>
+<instance part="VDD3" gate="G$1" x="195.58" y="167.64"/>
+<instance part="IC11" gate="G$1" x="203.2" y="81.28"/>
+<instance part="V33" gate="GND" x="215.9" y="43.18"/>
+<instance part="VDD8" gate="G$1" x="205.74" y="96.52"/>
+<instance part="IC5" gate="A" x="73.66" y="160.02"/>
+<instance part="IC5" gate="B" x="119.38" y="78.74"/>
+<instance part="IC5" gate="P" x="215.9" y="116.84"/>
+<instance part="V34" gate="GND" x="111.76" y="71.12" rot="MR0"/>
+<instance part="R21" gate="G$1" x="106.68" y="81.28"/>
+<instance part="R30" gate="G$1" x="45.72" y="142.24" rot="R90"/>
+<instance part="R31" gate="G$1" x="55.88" y="142.24" rot="R90"/>
+<instance part="V42" gate="GND" x="55.88" y="134.62"/>
+<instance part="V43" gate="GND" x="170.18" y="35.56" rot="MR0"/>
+<instance part="IC14" gate="A" x="71.12" y="76.2" rot="MR180"/>
+<instance part="IC14" gate="B" x="165.1" y="132.08" rot="MR180"/>
+<instance part="IC14" gate="P" x="226.06" y="116.84"/>
+<instance part="R33" gate="G$1" x="73.66" y="86.36"/>
+<instance part="C40" gate="G$1" x="73.66" y="93.98" rot="R90"/>
+<instance part="R34" gate="G$1" x="170.18" y="142.24"/>
+<instance part="C41" gate="G$1" x="170.18" y="149.86" rot="R90"/>
+<instance part="V45" gate="G$1" x="152.4" y="114.3" rot="R90"/>
+<instance part="C42" gate="G$1" x="35.56" y="83.82" rot="R90"/>
+<instance part="C43" gate="G$1" x="137.16" y="129.54" rot="R90"/>
+<instance part="R32" gate="G$1" x="147.32" y="129.54"/>
+<instance part="R35" gate="G$1" x="45.72" y="83.82"/>
+<instance part="R36" gate="G$1" x="127" y="30.48" rot="R90"/>
+<instance part="R37" gate="G$1" x="109.22" y="33.02" rot="R90"/>
+<instance part="R38" gate="G$1" x="109.22" y="20.32" rot="R90"/>
+<instance part="V46" gate="G$1" x="114.3" y="12.7" rot="MR90"/>
+<instance part="RLY1" gate="L" x="27.94" y="119.38"/>
+<instance part="RLY1" gate="A" x="15.24" y="48.26" rot="R90"/>
+<instance part="RLY1" gate="B" x="17.78" y="144.78" rot="R90"/>
+<instance part="Q1" gate="G$1" x="20.32" y="101.6"/>
+<instance part="D7" gate="G$1" x="15.24" y="116.84" rot="R90"/>
+<instance part="VDD9" gate="G$1" x="15.24" y="129.54"/>
+<instance part="V48" gate="GND" x="22.86" y="91.44"/>
+<instance part="R40" gate="G$1" x="12.7" y="93.98" rot="R90"/>
+<instance part="R41" gate="G$1" x="68.58" y="50.8" rot="R90"/>
+<instance part="R42" gate="G$1" x="78.74" y="58.42" rot="R180"/>
+<instance part="V49" gate="GND" x="86.36" y="53.34"/>
+<instance part="TP1" gate="G$1" x="231.14" y="78.74" rot="R270"/>
+<instance part="R48" gate="G$1" x="157.48" y="121.92" rot="R90"/>
+<instance part="R49" gate="G$1" x="53.34" y="76.2" rot="R90"/>
+<instance part="R50" gate="G$1" x="149.86" y="157.48"/>
+<instance part="V52" gate="G$1" x="139.7" y="157.48" rot="R90"/>
+<instance part="V44" gate="G$1" x="48.26" y="68.58" rot="R90"/>
+<instance part="R51" gate="G$1" x="58.42" y="93.98"/>
+<instance part="V53" gate="G$1" x="48.26" y="93.98" rot="R90"/>
+<instance part="C45" gate="G$1" x="241.3" y="142.24"/>
+<instance part="D10" gate="G$1" x="58.42" y="30.48" rot="R90"/>
+<instance part="D11" gate="G$1" x="73.66" y="116.84" rot="R90"/>
+<instance part="V56" gate="GND" x="73.66" y="106.68"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="N$14" class="0">
+<segment>
+<wire x1="205.74" y1="149.86" x2="195.58" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="195.58" y1="149.86" x2="195.58" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="195.58" y1="149.86" x2="195.58" y2="147.32" width="0.1524" layer="91"/>
+<junction x="195.58" y="149.86"/>
+<pinref part="IC6" gate="A" pin="+IN"/>
+<pinref part="R9" gate="G$1" pin="1"/>
+<pinref part="R10" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="GND" class="0">
+<segment>
+<wire x1="195.58" y1="137.16" x2="195.58" y2="134.62" width="0.1524" layer="91"/>
+<pinref part="R10" gate="G$1" pin="1"/>
+<pinref part="V14" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="48.26" y1="116.84" x2="48.26" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="114.3" x2="60.96" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="111.76" x2="60.96" y2="109.22" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="111.76" x2="60.96" y2="111.76" width="0.1524" layer="91"/>
+<junction x="60.96" y="111.76"/>
+<pinref part="C11" gate="G$1" pin="2"/>
+<pinref part="R11" gate="G$1" pin="1"/>
+<pinref part="V18" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="71.12" y1="157.48" x2="68.58" y2="157.48" width="0.1524" layer="91"/>
+<wire x1="68.58" y1="157.48" x2="68.58" y2="154.94" width="0.1524" layer="91"/>
+<pinref part="V22" gate="GND" pin="GND"/>
+<pinref part="IC5" gate="A" pin="-IN"/>
+</segment>
+<segment>
+<wire x1="238.76" y1="93.98" x2="238.76" y2="96.52" width="0.1524" layer="91"/>
+<wire x1="238.76" y1="96.52" x2="238.76" y2="99.06" width="0.1524" layer="91"/>
+<wire x1="238.76" y1="96.52" x2="226.06" y2="96.52" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="96.52" x2="215.9" y2="96.52" width="0.1524" layer="91"/>
+<wire x1="215.9" y1="96.52" x2="215.9" y2="99.06" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="99.06" x2="226.06" y2="96.52" width="0.1524" layer="91"/>
+<junction x="238.76" y="96.52"/>
+<junction x="226.06" y="96.52"/>
+<pinref part="V23" gate="GND" pin="GND"/>
+<pinref part="IC6" gate="P" pin="V-"/>
+<pinref part="IC5" gate="P" pin="V-"/>
+<pinref part="IC14" gate="P" pin="V-"/>
+</segment>
+<segment>
+<wire x1="66.04" y1="27.94" x2="66.04" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="78.74" y1="25.4" x2="78.74" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="78.74" y1="22.86" x2="78.74" y2="20.32" width="0.1524" layer="91"/>
+<wire x1="66.04" y1="22.86" x2="78.74" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="66.04" y1="22.86" x2="58.42" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="58.42" y1="22.86" x2="43.18" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="43.18" y1="22.86" x2="43.18" y2="27.94" width="0.1524" layer="91"/>
+<wire x1="58.42" y1="27.94" x2="58.42" y2="22.86" width="0.1524" layer="91"/>
+<junction x="78.74" y="22.86"/>
+<junction x="66.04" y="22.86"/>
+<junction x="58.42" y="22.86"/>
+<pinref part="C15" gate="G$1" pin="2"/>
+<pinref part="R15" gate="G$1" pin="1"/>
+<pinref part="V19" gate="GND" pin="GND"/>
+<pinref part="D3" gate="G$1" pin="A"/>
+<pinref part="D10" gate="G$1" pin="A"/>
+</segment>
+<segment>
+<wire x1="215.9" y1="48.26" x2="215.9" y2="45.72" width="0.1524" layer="91"/>
+<pinref part="IC11" gate="G$1" pin="VSS"/>
+<pinref part="V33" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="116.84" y1="76.2" x2="111.76" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="111.76" y1="76.2" x2="111.76" y2="73.66" width="0.1524" layer="91"/>
+<pinref part="IC5" gate="B" pin="-IN"/>
+<pinref part="V34" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<pinref part="R31" gate="G$1" pin="1"/>
+<pinref part="V42" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="175.26" y1="45.72" x2="170.18" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="45.72" x2="170.18" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="40.64" x2="170.18" y2="38.1" width="0.1524" layer="91"/>
+<wire x1="175.26" y1="40.64" x2="170.18" y2="40.64" width="0.1524" layer="91"/>
+<junction x="170.18" y="40.64"/>
+<pinref part="IC6" gate="D" pin="-IN"/>
+<pinref part="V43" gate="GND" pin="GND"/>
+<pinref part="IC6" gate="D" pin="+IN"/>
+</segment>
+<segment>
+<wire x1="22.86" y1="96.52" x2="22.86" y2="93.98" width="0.1524" layer="91"/>
+<pinref part="Q1" gate="G$1" pin="E"/>
+<pinref part="V48" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="83.82" y1="58.42" x2="86.36" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="86.36" y1="58.42" x2="86.36" y2="55.88" width="0.1524" layer="91"/>
+<pinref part="R42" gate="G$1" pin="1"/>
+<pinref part="V49" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="241.3" y1="139.7" x2="241.3" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="241.3" y1="137.16" x2="241.3" y2="134.62" width="0.1524" layer="91"/>
+<wire x1="241.3" y1="137.16" x2="231.14" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="137.16" x2="231.14" y2="139.7" width="0.1524" layer="91"/>
+<junction x="241.3" y="137.16"/>
+<pinref part="C45" gate="G$1" pin="2"/>
+<pinref part="V15" gate="GND" pin="GND"/>
+<pinref part="C10" gate="G$1" pin="2"/>
+</segment>
+<segment>
+<wire x1="73.66" y1="114.3" x2="73.66" y2="109.22" width="0.1524" layer="91"/>
+<pinref part="D11" gate="G$1" pin="A"/>
+<pinref part="V56" gate="GND" pin="GND"/>
+</segment>
+</net>
+<net name="VMID" class="0">
+<segment>
+<wire x1="205.74" y1="154.94" x2="203.2" y2="154.94" width="0.1524" layer="91"/>
+<wire x1="203.2" y1="154.94" x2="203.2" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="203.2" y1="162.56" x2="231.14" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="162.56" x2="231.14" y2="157.48" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="157.48" x2="231.14" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="152.4" x2="220.98" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="236.22" y1="157.48" x2="231.14" y2="157.48" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="147.32" x2="231.14" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="149.86" x2="231.14" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="149.86" x2="241.3" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="241.3" y1="149.86" x2="241.3" y2="147.32" width="0.1524" layer="91"/>
+<junction x="231.14" y="157.48"/>
+<junction x="231.14" y="152.4"/>
+<junction x="231.14" y="149.86"/>
+<pinref part="IC6" gate="A" pin="-IN"/>
+<pinref part="IC6" gate="A" pin="OUT"/>
+<pinref part="V13" gate="G$1" pin="VMID"/>
+<pinref part="C10" gate="G$1" pin="1"/>
+<pinref part="C45" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<wire x1="91.44" y1="111.76" x2="88.9" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="88.9" y1="111.76" x2="88.9" y2="114.3" width="0.1524" layer="91"/>
+<pinref part="V16" gate="G$1" pin="VMID"/>
+<pinref part="R12" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<wire x1="81.28" y1="142.24" x2="78.74" y2="142.24" width="0.1524" layer="91"/>
+<pinref part="R13" gate="G$1" pin="1"/>
+<pinref part="V17" gate="G$1" pin="VMID"/>
+</segment>
+<segment>
+<wire x1="132.08" y1="22.86" x2="127" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="127" y1="22.86" x2="119.38" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="22.86" x2="119.38" y2="25.4" width="0.1524" layer="91"/>
+<wire x1="127" y1="25.4" x2="127" y2="22.86" width="0.1524" layer="91"/>
+<junction x="127" y="22.86"/>
+<pinref part="V20" gate="G$1" pin="VMID"/>
+<pinref part="R17" gate="G$1" pin="1"/>
+<pinref part="R36" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<wire x1="111.76" y1="12.7" x2="109.22" y2="12.7" width="0.1524" layer="91"/>
+<wire x1="109.22" y1="12.7" x2="109.22" y2="15.24" width="0.1524" layer="91"/>
+<pinref part="V46" gate="G$1" pin="VMID"/>
+<pinref part="R38" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<wire x1="111.76" y1="53.34" x2="109.22" y2="53.34" width="0.1524" layer="91"/>
+<pinref part="R19" gate="G$1" pin="1"/>
+<pinref part="V21" gate="G$1" pin="VMID"/>
+</segment>
+<segment>
+<wire x1="154.94" y1="114.3" x2="157.48" y2="114.3" width="0.1524" layer="91"/>
+<wire x1="157.48" y1="114.3" x2="157.48" y2="116.84" width="0.1524" layer="91"/>
+<pinref part="V45" gate="G$1" pin="VMID"/>
+<pinref part="R48" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<wire x1="144.78" y1="157.48" x2="142.24" y2="157.48" width="0.1524" layer="91"/>
+<pinref part="R50" gate="G$1" pin="1"/>
+<pinref part="V52" gate="G$1" pin="VMID"/>
+</segment>
+<segment>
+<wire x1="50.8" y1="68.58" x2="53.34" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="53.34" y1="68.58" x2="53.34" y2="71.12" width="0.1524" layer="91"/>
+<pinref part="R49" gate="G$1" pin="1"/>
+<pinref part="V44" gate="G$1" pin="VMID"/>
+</segment>
+<segment>
+<wire x1="53.34" y1="93.98" x2="50.8" y2="93.98" width="0.1524" layer="91"/>
+<pinref part="R51" gate="G$1" pin="1"/>
+<pinref part="V53" gate="G$1" pin="VMID"/>
+</segment>
+</net>
+<net name="N$16" class="0">
+<segment>
+<wire x1="88.9" y1="124.46" x2="88.9" y2="127" width="0.1524" layer="91"/>
+<wire x1="88.9" y1="127" x2="86.36" y2="127" width="0.1524" layer="91"/>
+<wire x1="88.9" y1="127" x2="99.06" y2="127" width="0.1524" layer="91"/>
+<junction x="88.9" y="127"/>
+<pinref part="R12" gate="G$1" pin="2"/>
+<pinref part="C12" gate="G$1" pin="2"/>
+<pinref part="IC6" gate="B" pin="+IN"/>
+</segment>
+</net>
+<net name="N$17" class="0">
+<segment>
+<wire x1="99.06" y1="142.24" x2="96.52" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="96.52" y1="142.24" x2="93.98" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="93.98" y1="142.24" x2="91.44" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="99.06" y1="132.08" x2="93.98" y2="132.08" width="0.1524" layer="91"/>
+<wire x1="93.98" y1="132.08" x2="93.98" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="96.52" y1="149.86" x2="96.52" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="104.14" y1="149.86" x2="96.52" y2="149.86" width="0.1524" layer="91"/>
+<junction x="93.98" y="142.24"/>
+<junction x="96.52" y="142.24"/>
+<pinref part="R14" gate="G$1" pin="1"/>
+<pinref part="R13" gate="G$1" pin="2"/>
+<pinref part="IC6" gate="B" pin="-IN"/>
+<pinref part="C13" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$19" class="0">
+<segment>
+<wire x1="40.64" y1="127" x2="45.72" y2="127" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="127" x2="48.26" y2="127" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="127" x2="48.26" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="127" x2="60.96" y2="127" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="127" x2="60.96" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="127" x2="73.66" y2="127" width="0.1524" layer="91"/>
+<wire x1="73.66" y1="127" x2="78.74" y2="127" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="137.16" x2="45.72" y2="127" width="0.1524" layer="91"/>
+<wire x1="73.66" y1="119.38" x2="73.66" y2="127" width="0.1524" layer="91"/>
+<junction x="48.26" y="127"/>
+<junction x="60.96" y="127"/>
+<junction x="45.72" y="127"/>
+<junction x="73.66" y="127"/>
+<pinref part="D1" gate="G$1" pin="C"/>
+<pinref part="C11" gate="G$1" pin="1"/>
+<pinref part="R11" gate="G$1" pin="2"/>
+<pinref part="C12" gate="G$1" pin="1"/>
+<pinref part="R30" gate="G$1" pin="1"/>
+<pinref part="D11" gate="G$1" pin="C"/>
+</segment>
+</net>
+<net name="ADCDR_LO" class="0">
+<segment>
+<wire x1="109.22" y1="142.24" x2="124.46" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="142.24" x2="124.46" y2="129.54" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="129.54" x2="114.3" y2="129.54" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="149.86" x2="124.46" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="149.86" x2="111.76" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="129.54" x2="124.46" y2="106.68" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="106.68" x2="170.18" y2="106.68" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="106.68" x2="170.18" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="73.66" x2="198.12" y2="73.66" width="0.1524" layer="91"/>
+<junction x="124.46" y="142.24"/>
+<junction x="124.46" y="129.54"/>
+<pinref part="R14" gate="G$1" pin="2"/>
+<pinref part="IC6" gate="B" pin="OUT"/>
+<pinref part="C13" gate="G$1" pin="2"/>
+<pinref part="IC11" gate="G$1" pin="A2"/>
+</segment>
+</net>
+<net name="N$15" class="0">
+<segment>
+<wire x1="127" y1="55.88" x2="124.46" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="129.54" y1="45.72" x2="124.46" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="45.72" x2="124.46" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="53.34" x2="124.46" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="55.88" x2="124.46" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="63.5" x2="132.08" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="121.92" y1="53.34" x2="124.46" y2="53.34" width="0.1524" layer="91"/>
+<junction x="124.46" y="55.88"/>
+<junction x="124.46" y="53.34"/>
+<pinref part="R18" gate="G$1" pin="1"/>
+<pinref part="IC6" gate="C" pin="-IN"/>
+<pinref part="C17" gate="G$1" pin="1"/>
+<pinref part="R19" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$20" class="0">
+<segment>
+<wire x1="40.64" y1="40.64" x2="43.18" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="43.18" y1="40.64" x2="43.18" y2="33.02" width="0.1524" layer="91"/>
+<wire x1="43.18" y1="40.64" x2="48.26" y2="40.64" width="0.1524" layer="91"/>
+<junction x="43.18" y="40.64"/>
+<pinref part="C14" gate="G$1" pin="2"/>
+<pinref part="D3" gate="G$1" pin="C"/>
+<pinref part="D2" gate="G$1" pin="A"/>
+</segment>
+</net>
+<net name="N$18" class="0">
+<segment>
+<wire x1="93.98" y1="40.64" x2="96.52" y2="40.64" width="0.1524" layer="91"/>
+<pinref part="R16" gate="G$1" pin="2"/>
+<pinref part="C16" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$22" class="0">
+<segment>
+<wire x1="129.54" y1="40.64" x2="127" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="127" y1="40.64" x2="119.38" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="40.64" x2="109.22" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="109.22" y1="40.64" x2="104.14" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="35.56" x2="119.38" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="127" y1="35.56" x2="127" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="109.22" y1="38.1" x2="109.22" y2="40.64" width="0.1524" layer="91"/>
+<junction x="119.38" y="40.64"/>
+<junction x="127" y="40.64"/>
+<junction x="109.22" y="40.64"/>
+<pinref part="IC6" gate="C" pin="+IN"/>
+<pinref part="C16" gate="G$1" pin="2"/>
+<pinref part="R17" gate="G$1" pin="2"/>
+<pinref part="R36" gate="G$1" pin="2"/>
+<pinref part="R37" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$23" class="0">
+<segment>
+<wire x1="66.04" y1="162.56" x2="71.12" y2="162.56" width="0.1524" layer="91"/>
+<pinref part="R20" gate="G$1" pin="2"/>
+<pinref part="IC5" gate="A" pin="+IN"/>
+</segment>
+</net>
+<net name="CROSS_LO" class="0">
+<segment>
+<wire x1="86.36" y1="160.02" x2="99.06" y2="160.02" width="0.1524" layer="91"/>
+<label x="99.06" y="160.02" size="1.778" layer="95"/>
+<pinref part="IC5" gate="A" pin="OUT"/>
+</segment>
+</net>
+<net name="VDD" class="0">
+<segment>
+<wire x1="195.58" y1="165.1" x2="195.58" y2="162.56" width="0.1524" layer="91"/>
+<pinref part="VDD3" gate="G$1" pin="VDD"/>
+<pinref part="R9" gate="G$1" pin="2"/>
+</segment>
+<segment>
+<wire x1="215.9" y1="127" x2="215.9" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="215.9" y1="124.46" x2="215.9" y2="121.92" width="0.1524" layer="91"/>
+<wire x1="215.9" y1="124.46" x2="226.06" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="124.46" x2="238.76" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="238.76" y1="124.46" x2="238.76" y2="121.92" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="121.92" x2="226.06" y2="124.46" width="0.1524" layer="91"/>
+<junction x="215.9" y="124.46"/>
+<junction x="226.06" y="124.46"/>
+<pinref part="VDD2" gate="G$1" pin="VDD"/>
+<pinref part="IC6" gate="P" pin="V+"/>
+<pinref part="IC5" gate="P" pin="V+"/>
+<pinref part="IC14" gate="P" pin="V+"/>
+</segment>
+<segment>
+<wire x1="205.74" y1="93.98" x2="205.74" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="VDD8" gate="G$1" pin="VDD"/>
+<pinref part="IC11" gate="G$1" pin="VDD"/>
+</segment>
+<segment>
+<wire x1="25.4" y1="119.38" x2="22.86" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="119.38" x2="22.86" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="15.24" y1="119.38" x2="15.24" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="15.24" y1="124.46" x2="15.24" y2="127" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="124.46" x2="15.24" y2="124.46" width="0.1524" layer="91"/>
+<junction x="15.24" y="124.46"/>
+<pinref part="RLY1" gate="L" pin="P$1"/>
+<pinref part="D7" gate="G$1" pin="C"/>
+<pinref part="VDD9" gate="G$1" pin="VDD"/>
+</segment>
+</net>
+<net name="ADC_IN" class="0">
+<segment>
+<wire x1="223.52" y1="58.42" x2="226.06" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="223.52" y1="81.28" x2="226.06" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="81.28" x2="226.06" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="78.74" x2="226.06" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="73.66" x2="223.52" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="223.52" y1="66.04" x2="226.06" y2="66.04" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="66.04" x2="226.06" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="68.58" x2="226.06" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="58.42" x2="226.06" y2="66.04" width="0.1524" layer="91"/>
+<wire x1="233.68" y1="68.58" x2="226.06" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="228.6" y1="78.74" x2="226.06" y2="78.74" width="0.1524" layer="91"/>
+<junction x="226.06" y="73.66"/>
+<junction x="226.06" y="66.04"/>
+<junction x="226.06" y="68.58"/>
+<junction x="226.06" y="78.74"/>
+<label x="233.68" y="68.58" size="1.778" layer="95"/>
+<pinref part="IC11" gate="G$1" pin="B4"/>
+<pinref part="IC11" gate="G$1" pin="B1"/>
+<pinref part="IC11" gate="G$1" pin="B2"/>
+<pinref part="IC11" gate="G$1" pin="B3"/>
+<pinref part="TP1" gate="G$1" pin="P$1"/>
+</segment>
+</net>
+<net name="N$26" class="0">
+<segment>
+<wire x1="116.84" y1="81.28" x2="111.76" y2="81.28" width="0.1524" layer="91"/>
+<pinref part="IC5" gate="B" pin="+IN"/>
+<pinref part="R21" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="CROSS_HI" class="0">
+<segment>
+<wire x1="139.7" y1="78.74" x2="132.08" y2="78.74" width="0.1524" layer="91"/>
+<label x="139.7" y="78.74" size="1.778" layer="95"/>
+<pinref part="IC5" gate="B" pin="OUT"/>
+</segment>
+</net>
+<net name="ADCDR_HI" class="0">
+<segment>
+<wire x1="137.16" y1="55.88" x2="152.4" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="139.7" y1="63.5" x2="152.4" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="63.5" x2="152.4" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="58.42" x2="152.4" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="55.88" x2="152.4" y2="43.18" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="43.18" x2="144.78" y2="43.18" width="0.1524" layer="91"/>
+<wire x1="198.12" y1="58.42" x2="152.4" y2="58.42" width="0.1524" layer="91"/>
+<junction x="152.4" y="55.88"/>
+<junction x="152.4" y="58.42"/>
+<pinref part="R18" gate="G$1" pin="2"/>
+<pinref part="C17" gate="G$1" pin="2"/>
+<pinref part="IC6" gate="C" pin="OUT"/>
+<pinref part="IC11" gate="G$1" pin="A4"/>
+</segment>
+</net>
+<net name="AMPL_LO" class="0">
+<segment>
+<wire x1="45.72" y1="147.32" x2="45.72" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="149.86" x2="55.88" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="55.88" y1="149.86" x2="55.88" y2="147.32" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="149.86" x2="45.72" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="152.4" x2="48.26" y2="152.4" width="0.1524" layer="91"/>
+<junction x="45.72" y="149.86"/>
+<label x="48.26" y="152.4" size="1.778" layer="95"/>
+<pinref part="R30" gate="G$1" pin="2"/>
+<pinref part="R31" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$52" class="0">
+<segment>
+<wire x1="68.58" y1="93.98" x2="66.04" y2="93.98" width="0.1524" layer="91"/>
+<wire x1="68.58" y1="86.36" x2="66.04" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="68.58" y1="78.74" x2="66.04" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="66.04" y1="86.36" x2="66.04" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="66.04" y1="93.98" x2="66.04" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="63.5" y1="93.98" x2="66.04" y2="93.98" width="0.1524" layer="91"/>
+<junction x="66.04" y="86.36"/>
+<junction x="66.04" y="93.98"/>
+<pinref part="C40" gate="G$1" pin="1"/>
+<pinref part="R33" gate="G$1" pin="1"/>
+<pinref part="IC14" gate="A" pin="-IN"/>
+<pinref part="R51" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="RAW_HI" class="0">
+<segment>
+<wire x1="76.2" y1="93.98" x2="91.44" y2="93.98" width="0.1524" layer="91"/>
+<wire x1="91.44" y1="93.98" x2="91.44" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="91.44" y1="91.44" x2="91.44" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="91.44" y1="86.36" x2="91.44" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="91.44" y1="76.2" x2="83.82" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="78.74" y1="86.36" x2="91.44" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="91.44" y1="91.44" x2="160.02" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="160.02" y1="91.44" x2="160.02" y2="66.04" width="0.1524" layer="91"/>
+<wire x1="160.02" y1="66.04" x2="198.12" y2="66.04" width="0.1524" layer="91"/>
+<junction x="91.44" y="86.36"/>
+<junction x="91.44" y="91.44"/>
+<pinref part="C40" gate="G$1" pin="2"/>
+<pinref part="IC14" gate="A" pin="OUT"/>
+<pinref part="R33" gate="G$1" pin="2"/>
+<pinref part="IC11" gate="G$1" pin="A3"/>
+</segment>
+</net>
+<net name="MUXSEL_LOPKD" class="0">
+<segment>
+<wire x1="195.58" y1="71.12" x2="198.12" y2="71.12" width="0.1524" layer="91"/>
+<label x="195.58" y="71.12" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC11" gate="G$1" pin="C2"/>
+</segment>
+</net>
+<net name="MUXSEL_HIPKD" class="0">
+<segment>
+<wire x1="195.58" y1="55.88" x2="198.12" y2="55.88" width="0.1524" layer="91"/>
+<label x="195.58" y="55.88" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC11" gate="G$1" pin="C4"/>
+</segment>
+</net>
+<net name="MUXSEL_HIRAW" class="0">
+<segment>
+<wire x1="195.58" y1="63.5" x2="198.12" y2="63.5" width="0.1524" layer="91"/>
+<label x="195.58" y="63.5" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC11" gate="G$1" pin="C3"/>
+</segment>
+</net>
+<net name="MUXSEL_LORAW" class="0">
+<segment>
+<wire x1="195.58" y1="78.74" x2="198.12" y2="78.74" width="0.1524" layer="91"/>
+<label x="195.58" y="78.74" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC11" gate="G$1" pin="C1"/>
+</segment>
+</net>
+<net name="N$43" class="0">
+<segment>
+<wire x1="198.12" y1="81.28" x2="185.42" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="185.42" y1="81.28" x2="185.42" y2="132.08" width="0.1524" layer="91"/>
+<wire x1="185.42" y1="132.08" x2="177.8" y2="132.08" width="0.1524" layer="91"/>
+<wire x1="175.26" y1="142.24" x2="185.42" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="185.42" y1="142.24" x2="185.42" y2="132.08" width="0.1524" layer="91"/>
+<wire x1="172.72" y1="149.86" x2="185.42" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="185.42" y1="149.86" x2="185.42" y2="142.24" width="0.1524" layer="91"/>
+<junction x="185.42" y="132.08"/>
+<junction x="185.42" y="142.24"/>
+<pinref part="IC11" gate="G$1" pin="A1"/>
+<pinref part="IC14" gate="B" pin="OUT"/>
+<pinref part="R34" gate="G$1" pin="2"/>
+<pinref part="C41" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$53" class="0">
+<segment>
+<wire x1="165.1" y1="149.86" x2="160.02" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="160.02" y1="149.86" x2="160.02" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="160.02" y1="142.24" x2="160.02" y2="134.62" width="0.1524" layer="91"/>
+<wire x1="160.02" y1="134.62" x2="162.56" y2="134.62" width="0.1524" layer="91"/>
+<wire x1="165.1" y1="142.24" x2="160.02" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="157.48" x2="160.02" y2="157.48" width="0.1524" layer="91"/>
+<wire x1="160.02" y1="157.48" x2="160.02" y2="149.86" width="0.1524" layer="91"/>
+<junction x="160.02" y="142.24"/>
+<junction x="160.02" y="149.86"/>
+<pinref part="C41" gate="G$1" pin="1"/>
+<pinref part="IC14" gate="B" pin="-IN"/>
+<pinref part="R34" gate="G$1" pin="1"/>
+<pinref part="R50" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$54" class="0">
+<segment>
+<wire x1="152.4" y1="129.54" x2="157.48" y2="129.54" width="0.1524" layer="91"/>
+<wire x1="157.48" y1="127" x2="157.48" y2="129.54" width="0.1524" layer="91"/>
+<wire x1="157.48" y1="129.54" x2="162.56" y2="129.54" width="0.1524" layer="91"/>
+<junction x="157.48" y="129.54"/>
+<pinref part="R32" gate="G$1" pin="2"/>
+<pinref part="R48" gate="G$1" pin="2"/>
+<pinref part="IC14" gate="B" pin="+IN"/>
+</segment>
+</net>
+<net name="N$56" class="0">
+<segment>
+<wire x1="109.22" y1="27.94" x2="109.22" y2="25.4" width="0.1524" layer="91"/>
+<pinref part="R37" gate="G$1" pin="1"/>
+<pinref part="R38" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$35" class="0">
+<segment>
+<wire x1="25.4" y1="111.76" x2="22.86" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="111.76" x2="22.86" y2="109.22" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="109.22" x2="15.24" y2="109.22" width="0.1524" layer="91"/>
+<wire x1="15.24" y1="109.22" x2="15.24" y2="114.3" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="106.68" x2="22.86" y2="109.22" width="0.1524" layer="91"/>
+<junction x="22.86" y="109.22"/>
+<pinref part="RLY1" gate="L" pin="P$2"/>
+<pinref part="D7" gate="G$1" pin="A"/>
+<pinref part="Q1" gate="G$1" pin="C"/>
+</segment>
+</net>
+<net name="N$38" class="0">
+<segment>
+<wire x1="17.78" y1="101.6" x2="12.7" y2="101.6" width="0.1524" layer="91"/>
+<wire x1="12.7" y1="101.6" x2="12.7" y2="99.06" width="0.1524" layer="91"/>
+<pinref part="Q1" gate="G$1" pin="B"/>
+<pinref part="R40" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="RELAY_ON" class="0">
+<segment>
+<wire x1="12.7" y1="86.36" x2="12.7" y2="88.9" width="0.1524" layer="91"/>
+<label x="12.7" y="86.36" size="1.778" layer="95" rot="MR270"/>
+<pinref part="R40" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$36" class="0">
+<segment>
+<wire x1="20.32" y1="48.26" x2="22.86" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="48.26" x2="22.86" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="40.64" x2="30.48" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="40.64" x2="33.02" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="63.5" x2="30.48" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="63.5" x2="96.52" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="96.52" y1="63.5" x2="96.52" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="96.52" y1="81.28" x2="101.6" y2="81.28" width="0.1524" layer="91"/>
+<junction x="30.48" y="40.64"/>
+<pinref part="RLY1" gate="A" pin="NC"/>
+<pinref part="C14" gate="G$1" pin="1"/>
+<pinref part="R21" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$37" class="0">
+<segment>
+<wire x1="22.86" y1="58.42" x2="20.32" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="83.82" x2="22.86" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="83.82" x2="22.86" y2="83.82" width="0.1524" layer="91"/>
+<pinref part="RLY1" gate="A" pin="NO"/>
+<pinref part="C42" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="ANT_HI" class="0">
+<segment>
+<wire x1="20.32" y1="53.34" x2="27.94" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="27.94" y1="53.34" x2="27.94" y2="55.88" width="0.1524" layer="91"/>
+<label x="27.94" y="55.88" size="1.778" layer="95" rot="R90"/>
+<pinref part="RLY1" gate="A" pin="COM"/>
+</segment>
+</net>
+<net name="ANT_LO" class="0">
+<segment>
+<wire x1="22.86" y1="149.86" x2="30.48" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="149.86" x2="30.48" y2="152.4" width="0.1524" layer="91"/>
+<label x="30.48" y="152.4" size="1.778" layer="95" rot="R90"/>
+<pinref part="RLY1" gate="B" pin="COM"/>
+</segment>
+</net>
+<net name="N$39" class="0">
+<segment>
+<wire x1="55.88" y1="162.56" x2="33.02" y2="162.56" width="0.1524" layer="91"/>
+<wire x1="33.02" y1="162.56" x2="33.02" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="35.56" y1="127" x2="27.94" y2="127" width="0.1524" layer="91"/>
+<wire x1="27.94" y1="127" x2="27.94" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="27.94" y1="144.78" x2="22.86" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="33.02" y1="144.78" x2="27.94" y2="144.78" width="0.1524" layer="91"/>
+<junction x="27.94" y="144.78"/>
+<pinref part="R20" gate="G$1" pin="1"/>
+<pinref part="D1" gate="G$1" pin="A"/>
+<pinref part="RLY1" gate="B" pin="NC"/>
+</segment>
+</net>
+<net name="N$46" class="0">
+<segment>
+<wire x1="22.86" y1="154.94" x2="25.4" y2="154.94" width="0.1524" layer="91"/>
+<wire x1="25.4" y1="154.94" x2="25.4" y2="170.18" width="0.1524" layer="91"/>
+<wire x1="25.4" y1="170.18" x2="129.54" y2="170.18" width="0.1524" layer="91"/>
+<wire x1="129.54" y1="170.18" x2="129.54" y2="129.54" width="0.1524" layer="91"/>
+<wire x1="129.54" y1="129.54" x2="132.08" y2="129.54" width="0.1524" layer="91"/>
+<pinref part="RLY1" gate="B" pin="NO"/>
+<pinref part="C43" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="AMPL_HI" class="0">
+<segment>
+<wire x1="68.58" y1="55.88" x2="68.58" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="68.58" y1="58.42" x2="73.66" y2="58.42" width="0.1524" layer="91"/>
+<wire x1="63.5" y1="58.42" x2="68.58" y2="58.42" width="0.1524" layer="91"/>
+<junction x="68.58" y="58.42"/>
+<label x="63.5" y="58.42" size="1.778" layer="95" rot="MR0"/>
+<pinref part="R41" gate="G$1" pin="2"/>
+<pinref part="R42" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$50" class="0">
+<segment>
+<wire x1="142.24" y1="129.54" x2="139.7" y2="129.54" width="0.1524" layer="91"/>
+<pinref part="R32" gate="G$1" pin="1"/>
+<pinref part="C43" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$51" class="0">
+<segment>
+<wire x1="40.64" y1="83.82" x2="38.1" y2="83.82" width="0.1524" layer="91"/>
+<pinref part="R35" gate="G$1" pin="1"/>
+<pinref part="C42" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$47" class="0">
+<segment>
+<wire x1="68.58" y1="73.66" x2="60.96" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="73.66" x2="60.96" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="50.8" y1="83.82" x2="53.34" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="53.34" y1="81.28" x2="53.34" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="83.82" x2="53.34" y2="83.82" width="0.1524" layer="91"/>
+<junction x="53.34" y="83.82"/>
+<pinref part="IC14" gate="A" pin="+IN"/>
+<pinref part="R35" gate="G$1" pin="2"/>
+<pinref part="R49" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$21" class="0">
+<segment>
+<wire x1="53.34" y1="40.64" x2="58.42" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="58.42" y1="40.64" x2="66.04" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="66.04" y1="40.64" x2="66.04" y2="35.56" width="0.1524" layer="91"/>
+<wire x1="66.04" y1="40.64" x2="68.58" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="68.58" y1="40.64" x2="78.74" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="78.74" y1="40.64" x2="78.74" y2="35.56" width="0.1524" layer="91"/>
+<wire x1="78.74" y1="40.64" x2="83.82" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="68.58" y1="45.72" x2="68.58" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="58.42" y1="33.02" x2="58.42" y2="40.64" width="0.1524" layer="91"/>
+<junction x="66.04" y="40.64"/>
+<junction x="78.74" y="40.64"/>
+<junction x="68.58" y="40.64"/>
+<junction x="58.42" y="40.64"/>
+<pinref part="D10" gate="G$1" pin="C"/>
+<pinref part="D2" gate="G$1" pin="C"/>
+<pinref part="C15" gate="G$1" pin="1"/>
+<pinref part="R15" gate="G$1" pin="2"/>
+<pinref part="R16" gate="G$1" pin="1"/>
+<pinref part="R41" gate="G$1" pin="1"/>
+</segment>
+</net>
+</nets>
+</sheet>
+<sheet>
+<plain>
+<text x="165.1" y="17.78" size="2.54" layer="95">analog tx path</text>
+<text x="165.1" y="12.7" size="2.54" layer="95">(incl. coil drivers)</text>
+</plain>
+<instances>
+<instance part="FRAME5" gate="G$1" x="0" y="0"/>
+<instance part="SV2" gate="G$1" x="226.06" y="119.38"/>
+<instance part="IC9" gate="G$1" x="55.88" y="124.46"/>
+<instance part="V26" gate="GND" x="53.34" y="55.88" rot="MR0"/>
+<instance part="VDD5" gate="G$1" x="63.5" y="142.24" rot="MR0"/>
+<instance part="IC10" gate="G$1" x="127" y="124.46"/>
+<instance part="V27" gate="GND" x="124.46" y="55.88" rot="MR0"/>
+<instance part="VDD6" gate="G$1" x="134.62" y="142.24" rot="MR0"/>
+<instance part="R22" gate="G$1" x="78.74" y="78.74"/>
+<instance part="R27" gate="G$1" x="78.74" y="99.06"/>
+<instance part="R28" gate="G$1" x="149.86" y="124.46"/>
+<instance part="R29" gate="G$1" x="149.86" y="73.66"/>
+<instance part="C39" gate="G$1" x="167.64" y="109.22" rot="MR0"/>
+<instance part="V47" gate="GND" x="167.64" y="99.06" rot="MR0"/>
+<instance part="C20" gate="G$1" x="175.26" y="109.22" rot="MR0"/>
+<instance part="C35" gate="G$1" x="200.66" y="104.14" rot="MR0"/>
+<instance part="C36" gate="G$1" x="208.28" y="104.14" rot="MR0"/>
+<instance part="V41" gate="GND" x="200.66" y="93.98" rot="MR0"/>
+<instance part="R45" gate="G$1" x="78.74" y="91.44"/>
+<instance part="R46" gate="G$1" x="149.86" y="91.44"/>
+<instance part="TP2" gate="G$1" x="208.28" y="124.46"/>
+<instance part="TP3" gate="G$1" x="218.44" y="124.46"/>
+<instance part="TP4" gate="G$1" x="213.36" y="124.46"/>
+<instance part="TP5" gate="G$1" x="203.2" y="124.46"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="GND" class="0">
+<segment>
+<wire x1="53.34" y1="60.96" x2="53.34" y2="58.42" width="0.1524" layer="91"/>
+<pinref part="IC9" gate="G$1" pin="VSS"/>
+<pinref part="V26" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="124.46" y1="60.96" x2="124.46" y2="58.42" width="0.1524" layer="91"/>
+<pinref part="IC10" gate="G$1" pin="VSS"/>
+<pinref part="V27" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="167.64" y1="106.68" x2="167.64" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="167.64" y1="104.14" x2="167.64" y2="101.6" width="0.1524" layer="91"/>
+<wire x1="167.64" y1="104.14" x2="175.26" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="175.26" y1="104.14" x2="175.26" y2="106.68" width="0.1524" layer="91"/>
+<junction x="167.64" y="104.14"/>
+<pinref part="C20" gate="G$1" pin="2"/>
+<pinref part="V47" gate="GND" pin="GND"/>
+<pinref part="C39" gate="G$1" pin="2"/>
+</segment>
+<segment>
+<wire x1="200.66" y1="101.6" x2="200.66" y2="99.06" width="0.1524" layer="91"/>
+<wire x1="200.66" y1="99.06" x2="200.66" y2="96.52" width="0.1524" layer="91"/>
+<wire x1="200.66" y1="99.06" x2="208.28" y2="99.06" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="99.06" x2="208.28" y2="101.6" width="0.1524" layer="91"/>
+<junction x="200.66" y="99.06"/>
+<pinref part="C35" gate="G$1" pin="2"/>
+<pinref part="V41" gate="GND" pin="GND"/>
+<pinref part="C36" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="VDD" class="0">
+<segment>
+<wire x1="63.5" y1="139.7" x2="63.5" y2="137.16" width="0.1524" layer="91"/>
+<pinref part="VDD5" gate="G$1" pin="VDD"/>
+<pinref part="IC9" gate="G$1" pin="VDD"/>
+</segment>
+<segment>
+<wire x1="134.62" y1="139.7" x2="134.62" y2="137.16" width="0.1524" layer="91"/>
+<pinref part="VDD6" gate="G$1" pin="VDD"/>
+<pinref part="IC10" gate="G$1" pin="VDD"/>
+</segment>
+</net>
+<net name="N$31" class="0">
+<segment>
+<wire x1="93.98" y1="99.06" x2="93.98" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="83.82" y1="99.06" x2="86.36" y2="99.06" width="0.1524" layer="91"/>
+<wire x1="86.36" y1="99.06" x2="93.98" y2="99.06" width="0.1524" layer="91"/>
+<wire x1="93.98" y1="48.26" x2="157.48" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="157.48" y1="48.26" x2="157.48" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="157.48" y1="73.66" x2="154.94" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="157.48" y1="73.66" x2="182.88" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="182.88" y1="73.66" x2="182.88" y2="114.3" width="0.1524" layer="91"/>
+<wire x1="182.88" y1="114.3" x2="213.36" y2="114.3" width="0.1524" layer="91"/>
+<wire x1="213.36" y1="114.3" x2="220.98" y2="114.3" width="0.1524" layer="91"/>
+<wire x1="83.82" y1="91.44" x2="86.36" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="86.36" y1="91.44" x2="86.36" y2="99.06" width="0.1524" layer="91"/>
+<wire x1="213.36" y1="121.92" x2="213.36" y2="114.3" width="0.1524" layer="91"/>
+<junction x="157.48" y="73.66"/>
+<junction x="86.36" y="99.06"/>
+<junction x="213.36" y="114.3"/>
+<pinref part="R27" gate="G$1" pin="2"/>
+<pinref part="R29" gate="G$1" pin="2"/>
+<pinref part="SV2" gate="G$1" pin="PIN3"/>
+<pinref part="R45" gate="G$1" pin="2"/>
+<pinref part="TP4" gate="G$1" pin="P$1"/>
+</segment>
+</net>
+<net name="N$41" class="0">
+<segment>
+<wire x1="68.58" y1="83.82" x2="71.12" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="76.2" x2="71.12" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="78.74" x2="71.12" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="76.2" x2="68.58" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="68.58" x2="71.12" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="68.58" y1="68.58" x2="71.12" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="73.66" y1="78.74" x2="71.12" y2="78.74" width="0.1524" layer="91"/>
+<junction x="71.12" y="76.2"/>
+<junction x="71.12" y="78.74"/>
+<pinref part="IC9" gate="G$1" pin="2Y3"/>
+<pinref part="IC9" gate="G$1" pin="2Y2"/>
+<pinref part="IC9" gate="G$1" pin="2Y4"/>
+<pinref part="R22" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$33" class="0">
+<segment>
+<wire x1="68.58" y1="127" x2="71.12" y2="127" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="127" x2="71.12" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="119.38" x2="68.58" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="68.58" y1="111.76" x2="71.12" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="111.76" x2="71.12" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="68.58" y1="104.14" x2="71.12" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="104.14" x2="71.12" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="99.06" x2="71.12" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="73.66" y1="99.06" x2="71.12" y2="99.06" width="0.1524" layer="91"/>
+<junction x="71.12" y="119.38"/>
+<junction x="71.12" y="111.76"/>
+<junction x="71.12" y="104.14"/>
+<pinref part="IC9" gate="G$1" pin="1Y2"/>
+<pinref part="IC9" gate="G$1" pin="1Y1"/>
+<pinref part="IC9" gate="G$1" pin="1Y3"/>
+<pinref part="IC9" gate="G$1" pin="1Y4"/>
+<pinref part="R27" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$34" class="0">
+<segment>
+<wire x1="142.24" y1="104.14" x2="139.7" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="111.76" x2="142.24" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="139.7" y1="111.76" x2="142.24" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="139.7" y1="127" x2="142.24" y2="127" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="127" x2="142.24" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="144.78" y1="124.46" x2="142.24" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="124.46" x2="142.24" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="119.38" x2="142.24" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="139.7" y1="119.38" x2="142.24" y2="119.38" width="0.1524" layer="91"/>
+<junction x="142.24" y="111.76"/>
+<junction x="142.24" y="124.46"/>
+<junction x="142.24" y="119.38"/>
+<pinref part="IC10" gate="G$1" pin="1Y4"/>
+<pinref part="IC10" gate="G$1" pin="1Y3"/>
+<pinref part="IC10" gate="G$1" pin="1Y1"/>
+<pinref part="R28" gate="G$1" pin="1"/>
+<pinref part="IC10" gate="G$1" pin="1Y2"/>
+</segment>
+</net>
+<net name="N$42" class="0">
+<segment>
+<wire x1="139.7" y1="76.2" x2="142.24" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="139.7" y1="83.82" x2="142.24" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="83.82" x2="142.24" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="78.74" x2="142.24" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="81.28" x2="142.24" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="76.2" x2="142.24" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="73.66" x2="142.24" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="68.58" x2="139.7" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="144.78" y1="73.66" x2="142.24" y2="73.66" width="0.1524" layer="91"/>
+<junction x="142.24" y="81.28"/>
+<junction x="142.24" y="76.2"/>
+<junction x="142.24" y="73.66"/>
+<pinref part="IC10" gate="G$1" pin="2Y3"/>
+<pinref part="IC10" gate="G$1" pin="2Y2"/>
+<pinref part="IC10" gate="G$1" pin="2Y4"/>
+<pinref part="R29" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$32" class="0">
+<segment>
+<wire x1="220.98" y1="119.38" x2="203.2" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="203.2" y1="119.38" x2="185.42" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="185.42" y1="119.38" x2="185.42" y2="132.08" width="0.1524" layer="91"/>
+<wire x1="88.9" y1="78.74" x2="88.9" y2="147.32" width="0.1524" layer="91"/>
+<wire x1="88.9" y1="147.32" x2="157.48" y2="147.32" width="0.1524" layer="91"/>
+<wire x1="157.48" y1="147.32" x2="157.48" y2="132.08" width="0.1524" layer="91"/>
+<wire x1="157.48" y1="132.08" x2="157.48" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="83.82" y1="78.74" x2="88.9" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="124.46" x2="157.48" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="185.42" y1="132.08" x2="157.48" y2="132.08" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="91.44" x2="157.48" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="157.48" y1="91.44" x2="157.48" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="203.2" y1="121.92" x2="203.2" y2="119.38" width="0.1524" layer="91"/>
+<junction x="157.48" y="132.08"/>
+<junction x="157.48" y="124.46"/>
+<junction x="203.2" y="119.38"/>
+<pinref part="SV2" gate="G$1" pin="PIN1"/>
+<pinref part="R22" gate="G$1" pin="2"/>
+<pinref part="R28" gate="G$1" pin="2"/>
+<pinref part="R46" gate="G$1" pin="2"/>
+<pinref part="TP5" gate="G$1" pin="P$1"/>
+</segment>
+</net>
+<net name="PWR_OE1" class="0">
+<segment>
+<wire x1="48.26" y1="132.08" x2="38.1" y2="132.08" width="0.1524" layer="91"/>
+<label x="38.1" y="132.08" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC9" gate="G$1" pin="1NOE"/>
+</segment>
+</net>
+<net name="PWR_OE2" class="0">
+<segment>
+<wire x1="119.38" y1="132.08" x2="109.22" y2="132.08" width="0.1524" layer="91"/>
+<label x="109.22" y="132.08" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC10" gate="G$1" pin="1NOE"/>
+</segment>
+</net>
+<net name="PWR_LO" class="0">
+<segment>
+<wire x1="119.38" y1="127" x2="116.84" y2="127" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="127" x2="116.84" y2="121.92" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="121.92" x2="116.84" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="119.38" x2="119.38" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="111.76" x2="116.84" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="111.76" x2="116.84" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="104.14" x2="116.84" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="104.14" x2="116.84" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="91.44" x2="116.84" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="91.44" x2="116.84" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="121.92" x2="109.22" y2="121.92" width="0.1524" layer="91"/>
+<junction x="116.84" y="119.38"/>
+<junction x="116.84" y="111.76"/>
+<junction x="116.84" y="104.14"/>
+<junction x="116.84" y="121.92"/>
+<label x="109.22" y="121.92" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC10" gate="G$1" pin="1A1"/>
+<pinref part="IC10" gate="G$1" pin="1A2"/>
+<pinref part="IC10" gate="G$1" pin="1A3"/>
+<pinref part="IC10" gate="G$1" pin="1A4"/>
+<pinref part="IC10" gate="G$1" pin="2A1"/>
+</segment>
+<segment>
+<wire x1="48.26" y1="83.82" x2="45.72" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="83.82" x2="45.72" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="81.28" x2="45.72" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="76.2" x2="45.72" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="68.58" x2="48.26" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="76.2" x2="45.72" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="81.28" x2="38.1" y2="81.28" width="0.1524" layer="91"/>
+<junction x="45.72" y="76.2"/>
+<junction x="45.72" y="81.28"/>
+<label x="38.1" y="81.28" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC9" gate="G$1" pin="2A2"/>
+<pinref part="IC9" gate="G$1" pin="2A4"/>
+<pinref part="IC9" gate="G$1" pin="2A3"/>
+</segment>
+</net>
+<net name="PWR_HI" class="0">
+<segment>
+<wire x1="45.72" y1="104.14" x2="48.26" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="111.76" x2="45.72" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="119.38" x2="45.72" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="127" x2="45.72" y2="127" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="127" x2="45.72" y2="121.92" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="121.92" x2="45.72" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="119.38" x2="45.72" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="111.76" x2="45.72" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="91.44" x2="45.72" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="91.44" x2="45.72" y2="104.14" width="0.1524" layer="91"/>
+<wire x1="45.72" y1="121.92" x2="38.1" y2="121.92" width="0.1524" layer="91"/>
+<junction x="45.72" y="119.38"/>
+<junction x="45.72" y="111.76"/>
+<junction x="45.72" y="104.14"/>
+<junction x="45.72" y="121.92"/>
+<label x="38.1" y="121.92" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC9" gate="G$1" pin="1A4"/>
+<pinref part="IC9" gate="G$1" pin="1A3"/>
+<pinref part="IC9" gate="G$1" pin="1A2"/>
+<pinref part="IC9" gate="G$1" pin="1A1"/>
+<pinref part="IC9" gate="G$1" pin="2A1"/>
+</segment>
+<segment>
+<wire x1="119.38" y1="83.82" x2="116.84" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="83.82" x2="116.84" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="81.28" x2="116.84" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="76.2" x2="116.84" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="68.58" x2="119.38" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="119.38" y1="76.2" x2="116.84" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="81.28" x2="109.22" y2="81.28" width="0.1524" layer="91"/>
+<junction x="116.84" y="76.2"/>
+<junction x="116.84" y="81.28"/>
+<label x="109.22" y="81.28" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC10" gate="G$1" pin="2A2"/>
+<pinref part="IC10" gate="G$1" pin="2A4"/>
+<pinref part="IC10" gate="G$1" pin="2A3"/>
+</segment>
+</net>
+<net name="ANT_HI" class="0">
+<segment>
+<wire x1="220.98" y1="111.76" x2="218.44" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="218.44" y1="111.76" x2="208.28" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="111.76" x2="208.28" y2="109.22" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="111.76" x2="200.66" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="200.66" y1="111.76" x2="200.66" y2="109.22" width="0.1524" layer="91"/>
+<wire x1="200.66" y1="111.76" x2="198.12" y2="111.76" width="0.1524" layer="91"/>
+<wire x1="218.44" y1="121.92" x2="218.44" y2="111.76" width="0.1524" layer="91"/>
+<junction x="208.28" y="111.76"/>
+<junction x="200.66" y="111.76"/>
+<junction x="218.44" y="111.76"/>
+<label x="198.12" y="111.76" size="1.778" layer="95" rot="MR0"/>
+<pinref part="SV2" gate="G$1" pin="PIN4"/>
+<pinref part="C36" gate="G$1" pin="1"/>
+<pinref part="C35" gate="G$1" pin="1"/>
+<pinref part="TP3" gate="G$1" pin="P$1"/>
+</segment>
+</net>
+<net name="ANT_LO" class="0">
+<segment>
+<wire x1="220.98" y1="116.84" x2="208.28" y2="116.84" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="116.84" x2="175.26" y2="116.84" width="0.1524" layer="91"/>
+<wire x1="175.26" y1="116.84" x2="170.18" y2="116.84" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="116.84" x2="167.64" y2="116.84" width="0.1524" layer="91"/>
+<wire x1="167.64" y1="116.84" x2="167.64" y2="114.3" width="0.1524" layer="91"/>
+<wire x1="175.26" y1="114.3" x2="175.26" y2="116.84" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="116.84" x2="170.18" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="119.38" x2="172.72" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="121.92" x2="208.28" y2="116.84" width="0.1524" layer="91"/>
+<junction x="175.26" y="116.84"/>
+<junction x="170.18" y="116.84"/>
+<junction x="208.28" y="116.84"/>
+<label x="172.72" y="119.38" size="1.778" layer="95"/>
+<pinref part="SV2" gate="G$1" pin="PIN2"/>
+<pinref part="C39" gate="G$1" pin="1"/>
+<pinref part="C20" gate="G$1" pin="1"/>
+<pinref part="TP2" gate="G$1" pin="P$1"/>
+</segment>
+</net>
+<net name="PWR_OE3" class="0">
+<segment>
+<wire x1="38.1" y1="96.52" x2="48.26" y2="96.52" width="0.1524" layer="91"/>
+<label x="38.1" y="96.52" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC9" gate="G$1" pin="2NOE"/>
+</segment>
+</net>
+<net name="PWR_OE4" class="0">
+<segment>
+<wire x1="109.22" y1="96.52" x2="119.38" y2="96.52" width="0.1524" layer="91"/>
+<label x="109.22" y="96.52" size="1.778" layer="95" rot="MR0"/>
+<pinref part="IC10" gate="G$1" pin="2NOE"/>
+</segment>
+</net>
+<net name="N$44" class="0">
+<segment>
+<wire x1="73.66" y1="91.44" x2="68.58" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="IC9" gate="G$1" pin="2Y1"/>
+<pinref part="R45" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$45" class="0">
+<segment>
+<wire x1="144.78" y1="91.44" x2="139.7" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="IC10" gate="G$1" pin="2Y1"/>
+<pinref part="R46" gate="G$1" pin="1"/>
+</segment>
+</net>
+</nets>
+</sheet>
+</sheets>
+</schematic>
+</drawing>
+</eagle>

diff --git a/pcb/proxmark3_fix/CAD/proxmark3_exported_and_modified_components.lbr b/pcb/proxmark3_fix/CAD/proxmark3_exported_and_modified_components.lbr
new file mode 100644 (file)
index 0000000..f988c46
--- /dev/null
+++ b/pcb/proxmark3_fix/CAD/proxmark3_exported_and_modified_components.lbr
@@ -0,0 +1,2457 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="6.4">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="mm" unit="mm" style="dots" multiple="1" display="no" altdistance="0.025" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="2" name="Route2" color="1" fill="3" visible="yes" active="yes"/>
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+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
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+<deviceset name="--MERGED_CAPACITOR" prefix="C" uservalue="yes">
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+<device name="0603" package="--MERGED_RLC_0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
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+<technologies>
+<technology name=""/>
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+</device>
+<device name="0805" package="--MERGED_RLC_0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
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+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="1210" package="--MERGED_RLC_1210">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
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+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_CAPACITOR-POLARIZED" prefix="C" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="--MERGED_CAPACITOR-POLARIZED" x="0" y="0"/>
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+<devices>
+<device name="ALCHIP-MZA-F80" package="--MERGED_CAPCAITOR-ELECTROLYTIC-ALCHIP-MZA-F80">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
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+</technologies>
+</device>
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+<gates>
+<gate name="G$1" symbol="--MERGED_CD4066-ANALOG-SWITCH" x="-15.24" y="0"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_TSSOP-14">
+<connects>
+<connect gate="G$1" pin="A1" pad="1"/>
+<connect gate="G$1" pin="A2" pad="4"/>
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+<connect gate="G$1" pin="VDD" pad="14"/>
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+</device>
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+<deviceset name="--MERGED_COMP-TLV3502" prefix="IC">
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+<gate name="B" symbol="--MERGED_OPAMP" x="0" y="0"/>
+<gate name="P" symbol="--MERGED_POWER-PINS" x="-15.24" y="12.7"/>
+</gates>
+<devices>
+<device name="SOT-23-8" package="--MERGED_SOT-23-8">
+<connects>
+<connect gate="A" pin="+IN" pad="1"/>
+<connect gate="A" pin="-IN" pad="2"/>
+<connect gate="A" pin="OUT" pad="7"/>
+<connect gate="B" pin="+IN" pad="3"/>
+<connect gate="B" pin="-IN" pad="4"/>
+<connect gate="B" pin="OUT" pad="6"/>
+<connect gate="P" pin="V+" pad="8"/>
+<connect gate="P" pin="V-" pad="5"/>
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+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SOT-23-8-OR-MSOP-8" package="--MERGED_SOT-23-8-OR-MSOP-8">
+<connects>
+<connect gate="A" pin="+IN" pad="1"/>
+<connect gate="A" pin="-IN" pad="2"/>
+<connect gate="A" pin="OUT" pad="7"/>
+<connect gate="B" pin="+IN" pad="3"/>
+<connect gate="B" pin="-IN" pad="4"/>
+<connect gate="B" pin="OUT" pad="6"/>
+<connect gate="P" pin="V+" pad="8"/>
+<connect gate="P" pin="V-" pad="5"/>
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+<technologies>
+<technology name=""/>
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+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_DIODE-SMD-SOT23" prefix="D">
+<gates>
+<gate name="G$1" symbol="--MERGED_DIODE" x="2.54" y="0"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_SOT23-3LEAD">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="3"/>
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+<technologies>
+<technology name=""/>
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+</deviceset>
+<deviceset name="--MERGED_DUAL-TVS-COMMON-ANODE" prefix="D">
+<gates>
+<gate name="G$1" symbol="--MERGED_DUAL-TVS-COMMON-ANODE" x="0" y="0"/>
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+<devices>
+<device name="" package="--MERGED_SOT23-3LEAD">
+<connects>
+<connect gate="G$1" pin="A" pad="3"/>
+<connect gate="G$1" pin="K1" pad="1"/>
+<connect gate="G$1" pin="K2" pad="2"/>
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+</device>
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+<deviceset name="--MERGED_FERRITE" prefix="U">
+<gates>
+<gate name="G$1" symbol="--MERGED_FERRITE" x="-7.62" y="0"/>
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+<devices>
+<device name="0603" package="--MERGED_RLC_0603">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="B" pad="2"/>
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+<technologies>
+<technology name=""/>
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+</device>
+<device name="0805" package="--MERGED_RLC_0805">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="B" pad="2"/>
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+<technologies>
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+<device name="1210" package="--MERGED_RLC_1210">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="B" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_HCU-INVERTER" prefix="IC">
+<gates>
+<gate name="G$1" symbol="--MERGED_INVERTER" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_SMV-5">
+<connects>
+<connect gate="G$1" pin="A" pad="2"/>
+<connect gate="G$1" pin="VDD" pad="5"/>
+<connect gate="G$1" pin="VSS" pad="3"/>
+<connect gate="G$1" pin="Y" pad="4"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_HEADER-MALE-6X1" prefix="SV">
+<gates>
+<gate name="G$1" symbol="--MERGED_HEADER-MALE-6X1" x="0" y="-10.16"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_HEADER-MALE-6X1-0.100-UNKEYED">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_HEADER-MALE-10X2" prefix="SV" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="--MERGED_HEADER-MALE-10X2" x="2.54" y="-2.54"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_HEADER-MALE-10X2-0.100-SHROUDED">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="11" pad="11"/>
+<connect gate="G$1" pin="12" pad="12"/>
+<connect gate="G$1" pin="13" pad="13"/>
+<connect gate="G$1" pin="14" pad="14"/>
+<connect gate="G$1" pin="15" pad="15"/>
+<connect gate="G$1" pin="16" pad="16"/>
+<connect gate="G$1" pin="17" pad="17"/>
+<connect gate="G$1" pin="18" pad="18"/>
+<connect gate="G$1" pin="19" pad="19"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="20" pad="20"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_HIROSE-MQ172-4POS" prefix="SV">
+<gates>
+<gate name="G$1" symbol="--MERGED_4TERMSTRIP" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_HIROSE-MQ172-4POS">
+<connects>
+<connect gate="G$1" pin="PIN1" pad="1"/>
+<connect gate="G$1" pin="PIN2" pad="2"/>
+<connect gate="G$1" pin="PIN3" pad="3"/>
+<connect gate="G$1" pin="PIN4" pad="4"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_IRF7307" prefix="Q">
+<gates>
+<gate name="N" symbol="--MERGED_NFET" x="0" y="2.54"/>
+<gate name="P" symbol="--MERGED_PFET" x="10.16" y="0"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_SOIC-8">
+<connects>
+<connect gate="N" pin="D" pad="8"/>
+<connect gate="N" pin="G" pad="2"/>
+<connect gate="N" pin="S" pad="1"/>
+<connect gate="P" pin="D" pad="6"/>
+<connect gate="P" pin="G" pad="4"/>
+<connect gate="P" pin="S" pad="3"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_LED" prefix="D">
+<gates>
+<gate name="G$1" symbol="--MERGED_LED" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_LED_0603">
+<connects>
+<connect gate="G$1" pin="A" pad="+"/>
+<connect gate="G$1" pin="C" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_LP2989-LDO" prefix="IC" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="--MERGED_LP2989-LDO" x="0" y="-2.54"/>
+</gates>
+<devices>
+<device name="SOIC" package="--MERGED_SOIC-8">
+<connects>
+<connect gate="G$1" pin="/ERROR" pad="7"/>
+<connect gate="G$1" pin="/SHDN" pad="8"/>
+<connect gate="G$1" pin="BYP" pad="1"/>
+<connect gate="G$1" pin="GND" pad="3"/>
+<connect gate="G$1" pin="IN" pad="4"/>
+<connect gate="G$1" pin="OUT" pad="5"/>
+<connect gate="G$1" pin="SENSE" pad="6"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_MCP100" prefix="IC">
+<gates>
+<gate name="G$1" symbol="--MERGED_RESET-GENERATOR-3TERM" x="2.54" y="7.62"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_SOT23-3LEAD">
+<connects>
+<connect gate="G$1" pin="OUT" pad="1"/>
+<connect gate="G$1" pin="V+" pad="2"/>
+<connect gate="G$1" pin="V-" pad="3"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_NPN-SOT23-2N3904" prefix="Q">
+<gates>
+<gate name="G$1" symbol="--MERGED_NPN-THIN-SYMBOL" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_SOT23-3LEAD">
+<connects>
+<connect gate="G$1" pin="B" pad="1"/>
+<connect gate="G$1" pin="C" pad="3"/>
+<connect gate="G$1" pin="E" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_OPAMP-AD8052" prefix="IC">
+<gates>
+<gate name="A" symbol="--MERGED_OPAMP" x="0" y="0"/>
+<gate name="B" symbol="--MERGED_OPAMP" x="0" y="-12.7"/>
+<gate name="P" symbol="--MERGED_POWER-PINS" x="-20.32" y="2.54"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_MSOP8">
+<connects>
+<connect gate="A" pin="+IN" pad="3"/>
+<connect gate="A" pin="-IN" pad="2"/>
+<connect gate="A" pin="OUT" pad="1"/>
+<connect gate="B" pin="+IN" pad="5"/>
+<connect gate="B" pin="-IN" pad="6"/>
+<connect gate="B" pin="OUT" pad="7"/>
+<connect gate="P" pin="V+" pad="8"/>
+<connect gate="P" pin="V-" pad="4"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_OPAMP-TLC2274" prefix="IC">
+<gates>
+<gate name="A" symbol="--MERGED_OPAMP" x="0" y="0"/>
+<gate name="B" symbol="--MERGED_OPAMP" x="0" y="-12.7"/>
+<gate name="C" symbol="--MERGED_OPAMP" x="0" y="-25.4"/>
+<gate name="D" symbol="--MERGED_OPAMP" x="0" y="-38.1"/>
+<gate name="P" symbol="--MERGED_POWER-PINS" x="-30.48" y="-2.54"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_TSSOP-14">
+<connects>
+<connect gate="A" pin="+IN" pad="3"/>
+<connect gate="A" pin="-IN" pad="2"/>
+<connect gate="A" pin="OUT" pad="1"/>
+<connect gate="B" pin="+IN" pad="5"/>
+<connect gate="B" pin="-IN" pad="6"/>
+<connect gate="B" pin="OUT" pad="7"/>
+<connect gate="C" pin="+IN" pad="10"/>
+<connect gate="C" pin="-IN" pad="9"/>
+<connect gate="C" pin="OUT" pad="8"/>
+<connect gate="D" pin="+IN" pad="12"/>
+<connect gate="D" pin="-IN" pad="13"/>
+<connect gate="D" pin="OUT" pad="14"/>
+<connect gate="P" pin="V+" pad="4"/>
+<connect gate="P" pin="V-" pad="11"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_PQ1X331M2ZP-3V3-LDO-SOT-23-5" prefix="IC">
+<gates>
+<gate name="G$1" symbol="--MERGED_PQ1X331M2ZP-3V3-REG" x="-17.78" y="-2.54"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_SOT-23-5">
+<connects>
+<connect gate="G$1" pin="GND" pad="2"/>
+<connect gate="G$1" pin="NR" pad="4"/>
+<connect gate="G$1" pin="VC" pad="3"/>
+<connect gate="G$1" pin="VIN" pad="1"/>
+<connect gate="G$1" pin="VO" pad="5"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_RELAY-DPDT" prefix="RLY">
+<gates>
+<gate name="A" symbol="--MERGED_RELAY-NO-NC" x="-7.62" y="2.54"/>
+<gate name="B" symbol="--MERGED_RELAY-NO-NC" x="10.16" y="2.54"/>
+<gate name="L" symbol="--MERGED_RELAY-COIL" x="-2.54" y="17.78"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_TQ-SMD-RELAY">
+<connects>
+<connect gate="A" pin="COM" pad="8"/>
+<connect gate="A" pin="NC" pad="9"/>
+<connect gate="A" pin="NO" pad="7"/>
+<connect gate="B" pin="COM" pad="3"/>
+<connect gate="B" pin="NC" pad="2"/>
+<connect gate="B" pin="NO" pad="4"/>
+<connect gate="L" pin="P$1" pad="1"/>
+<connect gate="L" pin="P$2" pad="10"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_RESISTOR" prefix="R" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="--MERGED_RESISTOR" x="-5.08" y="0"/>
+</gates>
+<devices>
+<device name="0603" package="--MERGED_RLC_0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0805" package="--MERGED_RLC_0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="1210" package="--MERGED_RLC_1210">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="2512" package="--MERGED_2512">
+<connects>
+<connect gate="G$1" pin="1" pad="P$1"/>
+<connect gate="G$1" pin="2" pad="P$2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_SPARTAN-II-XC2S30-100-VQFP" prefix="IC">
+<gates>
+<gate name="G$1" symbol="--MERGED_SPARTAN-II-XC2S30-100-VQFP" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_VQFP-100">
+<connects>
+<connect gate="G$1" pin="/PROGRAM" pad="51"/>
+<connect gate="G$1" pin="CCLK" pad="75"/>
+<connect gate="G$1" pin="DIN" pad="73"/>
+<connect gate="G$1" pin="DONE" pad="49"/>
+<connect gate="G$1" pin="DOUT" pad="74"/>
+<connect gate="G$1" pin="GND1" pad="1"/>
+<connect gate="G$1" pin="GND2" pad="11"/>
+<connect gate="G$1" pin="GND3" pad="38"/>
+<connect gate="G$1" pin="GND4" pad="78"/>
+<connect gate="G$1" pin="GND5" pad="89"/>
+<connect gate="G$1" pin="GND6" pad="48"/>
+<connect gate="G$1" pin="GND7" pad="64"/>
+<connect gate="G$1" pin="GND8" pad="24"/>
+<connect gate="G$1" pin="M0" pad="25"/>
+<connect gate="G$1" pin="M1" pad="23"/>
+<connect gate="G$1" pin="M2" pad="27"/>
+<connect gate="G$1" pin="NC0" pad="28"/>
+<connect gate="G$1" pin="NC1" pad="29"/>
+<connect gate="G$1" pin="P10_IO7" pad="10"/>
+<connect gate="G$1" pin="P13_IO6" pad="13"/>
+<connect gate="G$1" pin="P15_IO6" pad="15"/>
+<connect gate="G$1" pin="P16_IOV6" pad="16"/>
+<connect gate="G$1" pin="P17_IO6" pad="17"/>
+<connect gate="G$1" pin="P18_IO6" pad="18"/>
+<connect gate="G$1" pin="P19_IO6" pad="19"/>
+<connect gate="G$1" pin="P20_IOV6" pad="20"/>
+<connect gate="G$1" pin="P21_IO6" pad="21"/>
+<connect gate="G$1" pin="P22_IO6" pad="22"/>
+<connect gate="G$1" pin="P30_IOV5" pad="30"/>
+<connect gate="G$1" pin="P31_IO5" pad="31"/>
+<connect gate="G$1" pin="P32_IO5" pad="32"/>
+<connect gate="G$1" pin="P34_IOV5" pad="34"/>
+<connect gate="G$1" pin="P36_IGCK5" pad="36"/>
+<connect gate="G$1" pin="P39_IGCK4" pad="39"/>
+<connect gate="G$1" pin="P3_IO7" pad="3"/>
+<connect gate="G$1" pin="P40_IO4" pad="40"/>
+<connect gate="G$1" pin="P41_IOV4" pad="41"/>
+<connect gate="G$1" pin="P43_IO4" pad="43"/>
+<connect gate="G$1" pin="P44_IO4" pad="44"/>
+<connect gate="G$1" pin="P45_IOV4" pad="45"/>
+<connect gate="G$1" pin="P46_IO4" pad="46"/>
+<connect gate="G$1" pin="P47_IO4" pad="47"/>
+<connect gate="G$1" pin="P4_IOV7" pad="4"/>
+<connect gate="G$1" pin="P52_IO3" pad="52"/>
+<connect gate="G$1" pin="P53_IO3" pad="53"/>
+<connect gate="G$1" pin="P54_IOV3" pad="54"/>
+<connect gate="G$1" pin="P55_IO3" pad="55"/>
+<connect gate="G$1" pin="P56_IO3" pad="56"/>
+<connect gate="G$1" pin="P57_IO3" pad="57"/>
+<connect gate="G$1" pin="P58_IO3" pad="58"/>
+<connect gate="G$1" pin="P59_IOV3" pad="59"/>
+<connect gate="G$1" pin="P5_IO7" pad="5"/>
+<connect gate="G$1" pin="P60_IO3" pad="60"/>
+<connect gate="G$1" pin="P62_IO3" pad="62"/>
+<connect gate="G$1" pin="P65_IO2" pad="65"/>
+<connect gate="G$1" pin="P66_IO2" pad="66"/>
+<connect gate="G$1" pin="P67_IOV2" pad="67"/>
+<connect gate="G$1" pin="P68_IO2" pad="68"/>
+<connect gate="G$1" pin="P69_IO2" pad="69"/>
+<connect gate="G$1" pin="P6_IO7" pad="6"/>
+<connect gate="G$1" pin="P70_IO2" pad="70"/>
+<connect gate="G$1" pin="P71_IO2" pad="71"/>
+<connect gate="G$1" pin="P72_IOV2" pad="72"/>
+<connect gate="G$1" pin="P7_IO7" pad="7"/>
+<connect gate="G$1" pin="P80_IO1" pad="80"/>
+<connect gate="G$1" pin="P81_IO1" pad="81"/>
+<connect gate="G$1" pin="P82_IOV1" pad="82"/>
+<connect gate="G$1" pin="P83_IO1" pad="83"/>
+<connect gate="G$1" pin="P84_IO1" pad="84"/>
+<connect gate="G$1" pin="P86_IOV1" pad="86"/>
+<connect gate="G$1" pin="P87_IO1" pad="87"/>
+<connect gate="G$1" pin="P88_IGCK1" pad="88"/>
+<connect gate="G$1" pin="P8_IOV7" pad="8"/>
+<connect gate="G$1" pin="P91_IGCK0" pad="91"/>
+<connect gate="G$1" pin="P93_IOV0" pad="93"/>
+<connect gate="G$1" pin="P95_IO0" pad="95"/>
+<connect gate="G$1" pin="P96_IO0" pad="96"/>
+<connect gate="G$1" pin="P97_IOV0" pad="97"/>
+<connect gate="G$1" pin="P98_IO0" pad="98"/>
+<connect gate="G$1" pin="P9_IO7" pad="9"/>
+<connect gate="G$1" pin="TCK" pad="99"/>
+<connect gate="G$1" pin="TDI" pad="79"/>
+<connect gate="G$1" pin="TDO" pad="77"/>
+<connect gate="G$1" pin="TMS" pad="2"/>
+<connect gate="G$1" pin="VCCINT1" pad="61"/>
+<connect gate="G$1" pin="VCCINT2" pad="92"/>
+<connect gate="G$1" pin="VCCINT3" pad="85"/>
+<connect gate="G$1" pin="VCCINT4" pad="94"/>
+<connect gate="G$1" pin="VCCINT5" pad="14"/>
+<connect gate="G$1" pin="VCCINT6" pad="33"/>
+<connect gate="G$1" pin="VCCINT7" pad="35"/>
+<connect gate="G$1" pin="VCCINT8" pad="42"/>
+<connect gate="G$1" pin="VCCO_B07" pad="100"/>
+<connect gate="G$1" pin="VCCO_B10" pad="90"/>
+<connect gate="G$1" pin="VCCO_B21" pad="76"/>
+<connect gate="G$1" pin="VCCO_B32" pad="63"/>
+<connect gate="G$1" pin="VCCO_B43" pad="50"/>
+<connect gate="G$1" pin="VCCO_B54" pad="37"/>
+<connect gate="G$1" pin="VCCO_B65" pad="26"/>
+<connect gate="G$1" pin="VCCO_B76" pad="12"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_SUPPLY_2V5" prefix="V">
+<gates>
+<gate name="G$1" symbol="--MERGED_SUPPLY_+2V5" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_SUPPLY_VMID" prefix="V">
+<gates>
+<gate name="G$1" symbol="--MERGED_SUPPLY_VMID" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_TACTSWITCH" prefix="SW">
+<gates>
+<gate name="G$1" symbol="--MERGED_TACTSWITCH" x="-10.16" y="5.08"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_TACTSWITCH-SMD-EVQQ1">
+<connects>
+<connect gate="G$1" pin="P$1" pad="A"/>
+<connect gate="G$1" pin="P$2" pad="B"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="THROUGHHOLE" package="--MERGED_TACTSWITCH">
+<connects>
+<connect gate="G$1" pin="P$1" pad="P$1"/>
+<connect gate="G$1" pin="P$2" pad="P$2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_TESTPAD" prefix="TP">
+<gates>
+<gate name="G$1" symbol="--MERGED_TESTPAD" x="0" y="2.54"/>
+</gates>
+<devices>
+<device name="0.7MM-ROUND-DRILLED" package="--MERGED_TESTPAD-PTH-0.7MM">
+<connects>
+<connect gate="G$1" pin="P$1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0.200&quot;-SQUARE" package="--MERGED_SQUARE-PAD-0.200-INCH">
+<connects>
+<connect gate="G$1" pin="P$1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="KEYSTONE-PTH" package="--MERGED_KEYSTONE-PTH-TESTPOINT-5011">
+<connects>
+<connect gate="G$1" pin="P$1" pad="A"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="KEYSTONE-SMD" package="--MERGED_KEYSTONE-SMD-TESTPOINT-5015">
+<connects>
+<connect gate="G$1" pin="P$1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_TLC5540" prefix="IC">
+<gates>
+<gate name="G$1" symbol="--MERGED_TLC5540" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_TSSOP-24">
+<connects>
+<connect gate="G$1" pin="AGND0" pad="20"/>
+<connect gate="G$1" pin="AGND1" pad="21"/>
+<connect gate="G$1" pin="ANALOGIN" pad="19"/>
+<connect gate="G$1" pin="CLK" pad="12"/>
+<connect gate="G$1" pin="D1" pad="3"/>
+<connect gate="G$1" pin="D2" pad="4"/>
+<connect gate="G$1" pin="D3" pad="5"/>
+<connect gate="G$1" pin="D4" pad="6"/>
+<connect gate="G$1" pin="D5" pad="7"/>
+<connect gate="G$1" pin="D6" pad="8"/>
+<connect gate="G$1" pin="D7" pad="9"/>
+<connect gate="G$1" pin="DGND0" pad="2"/>
+<connect gate="G$1" pin="DGND1" pad="24"/>
+<connect gate="G$1" pin="MSB-D8" pad="10"/>
+<connect gate="G$1" pin="NOE" pad="1"/>
+<connect gate="G$1" pin="REFB" pad="23"/>
+<connect gate="G$1" pin="REFBS" pad="22"/>
+<connect gate="G$1" pin="REFT" pad="17"/>
+<connect gate="G$1" pin="REFTS" pad="16"/>
+<connect gate="G$1" pin="VDDA0" pad="14"/>
+<connect gate="G$1" pin="VDDA1" pad="15"/>
+<connect gate="G$1" pin="VDDA2" pad="18"/>
+<connect gate="G$1" pin="VDDD0" pad="11"/>
+<connect gate="G$1" pin="VDDD1" pad="13"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_USB-MINIB" prefix="SV">
+<gates>
+<gate name="G$1" symbol="--MERGED_USB-MINIB" x="0" y="-2.54"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_USB-MINIB-SMD">
+<connects>
+<connect gate="G$1" pin="D+/3" pad="3"/>
+<connect gate="G$1" pin="D-/2" pad="2"/>
+<connect gate="G$1" pin="GND/5" pad="5"/>
+<connect gate="G$1" pin="ID/4" pad="4"/>
+<connect gate="G$1" pin="SHLD0" pad="TAB0"/>
+<connect gate="G$1" pin="SHLD1" pad="TAB1"/>
+<connect gate="G$1" pin="SHLD2" pad="TAB2"/>
+<connect gate="G$1" pin="SHLD3" pad="TAB3"/>
+<connect gate="G$1" pin="VBUS/1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="--MERGED_XTAL-SMD-CITIZEN-CS10" prefix="XT">
+<gates>
+<gate name="G$1" symbol="--MERGED_CRYSTAL" x="-10.16" y="2.54"/>
+</gates>
+<devices>
+<device name="" package="--MERGED_XTAL-SMD-CITIZEN-CS10">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="B" pad="B"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="FRAMES_A4L-LOC" prefix="FRAME" uservalue="yes">
+<description>&lt;b&gt;FRAME&lt;/b&gt;&lt;p&gt;
+DIN A4, landscape with location and doc. field</description>
+<gates>
+<gate name="G$1" symbol="FRAMES_A4L-LOC" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="SUPPLY1_+3V3" prefix="+3V3">
+<description>&lt;b&gt;SUPPLY SYMBOL&lt;/b&gt;</description>
+<gates>
+<gate name="G$1" symbol="SUPPLY1_+3V3" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="SUPPLY1_VDD" prefix="VDD">
+<description>&lt;b&gt;SUPPLY SYMBOL&lt;/b&gt;</description>
+<gates>
+<gate name="G$1" symbol="SUPPLY1_VDD" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="SUPPLY2_GND" prefix="SUPPLY">
+<description>&lt;b&gt;SUPPLY SYMBOL&lt;/b&gt;</description>
+<gates>
+<gate name="GND" symbol="SUPPLY2_GND" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</drawing>
+</eagle>

diff --git a/pcb/proxmark3_fix/CAM/README.txt b/pcb/proxmark3_fix/CAM/README.txt
new file mode 100644 (file)
index 0000000..dce98bf
--- /dev/null
+++ b/pcb/proxmark3_fix/CAM/README.txt
@@ -0,0 +1,35 @@
+
+project: proxmark3-00
+
+    * please make 18 boards
+    * panelize 3x1 (for total 6 panels)
+    * 0.062" finished thickness
+    * FR-4
+    * solder mask top and bottom
+    * silkscreen legend top
+    * either 1 ounce or 0.5 ounce copper acceptable (1 ounce preferred)
+
+Layer stackup:
+
+Top layer: *.GTL
+Inner Layer 1: *.GL1 (for 4-layer board)
+Inner Layer 2: *.GL2 (for 4-layer board)
+Bottom layer: *.GBL
+Solder Stop Mask top: *.GTS
+Solder Stop Mask Bottom: *.GBS
+Silk Top: *.GTO
+Silk Bottom: *.GBO
+NC Drill: *.TXT
+Outline layer: *.GKO or *.DO
+
+Note:
+ All the gerber files in RS-274x format, except the drill file in Excellon format. 
+
+
+
+Ship to
+
+<my shipping address>
+
+<my email address>
+

diff --git a/pcb/proxmark3_fix/CAM/proxmark3.GBL b/pcb/proxmark3_fix/CAM/proxmark3.GBL
new file mode 100644 (file)
index 0000000..5a0e4e2
--- /dev/null
+++ b/pcb/proxmark3_fix/CAM/proxmark3.GBL
@@ -0,0 +1,10632 @@
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diff --git a/pcb/proxmark3_fix/CAM/proxmark3.GBO b/pcb/proxmark3_fix/CAM/proxmark3.GBO
new file mode 100644 (file)
index 0000000..90d9b04
--- /dev/null
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diff --git a/pcb/proxmark3_fix/CAM/proxmark3.GBP b/pcb/proxmark3_fix/CAM/proxmark3.GBP
new file mode 100644 (file)
index 0000000..90d9b04
--- /dev/null
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new file mode 100644 (file)
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diff --git a/pcb/proxmark3_fix/CAM/proxmark3.GL1 b/pcb/proxmark3_fix/CAM/proxmark3.GL1
new file mode 100644 (file)
index 0000000..dc56942
--- /dev/null
+++ b/pcb/proxmark3_fix/CAM/proxmark3.GL1
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diff --git a/pcb/proxmark3_fix/CAM/proxmark3.GL2 b/pcb/proxmark3_fix/CAM/proxmark3.GL2
new file mode 100644 (file)
index 0000000..b92f2de
--- /dev/null
+++ b/pcb/proxmark3_fix/CAM/proxmark3.GL2
@@ -0,0 +1,1066 @@
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diff --git a/pcb/proxmark3_fix/CAM/proxmark3.GML b/pcb/proxmark3_fix/CAM/proxmark3.GML
new file mode 100644 (file)
index 0000000..90d9b04
--- /dev/null
+++ b/pcb/proxmark3_fix/CAM/proxmark3.GML
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diff --git a/pcb/proxmark3_fix/CAM/proxmark3.GTL b/pcb/proxmark3_fix/CAM/proxmark3.GTL
new file mode 100644 (file)
index 0000000..d3ed70f
--- /dev/null
+++ b/pcb/proxmark3_fix/CAM/proxmark3.GTL
@@ -0,0 +1,13664 @@
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diff --git a/pcb/proxmark3_fix/CAM/proxmark3.GTO b/pcb/proxmark3_fix/CAM/proxmark3.GTO
new file mode 100644 (file)
index 0000000..6942ad8
--- /dev/null
+++ b/pcb/proxmark3_fix/CAM/proxmark3.GTO
@@ -0,0 +1,2246 @@
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diff --git a/pcb/proxmark3_fix/CAM/proxmark3.GTP b/pcb/proxmark3_fix/CAM/proxmark3.GTP
new file mode 100644 (file)
index 0000000..74c3e09
--- /dev/null
+++ b/pcb/proxmark3_fix/CAM/proxmark3.GTP
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diff --git a/pcb/proxmark3_fix/CAM/proxmark3.GTS b/pcb/proxmark3_fix/CAM/proxmark3.GTS
new file mode 100644 (file)
index 0000000..6f5482a
--- /dev/null
+++ b/pcb/proxmark3_fix/CAM/proxmark3.GTS
@@ -0,0 +1,1146 @@
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diff --git a/pcb/proxmark3_fix/CAM/proxmark3.TXT b/pcb/proxmark3_fix/CAM/proxmark3.TXT
new file mode 100644 (file)
index 0000000..0222af7
--- /dev/null
+++ b/pcb/proxmark3_fix/CAM/proxmark3.TXT
@@ -0,0 +1,376 @@
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diff --git a/pcb/proxmark3_fix/CAM/proxmark3.do b/pcb/proxmark3_fix/CAM/proxmark3.do
new file mode 100644 (file)
index 0000000..84610a6
--- /dev/null
+++ b/pcb/proxmark3_fix/CAM/proxmark3.do
@@ -0,0 +1,23531 @@
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diff --git a/pcb/proxmark3_fix/CAM/proxmark3.dri b/pcb/proxmark3_fix/CAM/proxmark3.dri
new file mode 100644 (file)
index 0000000..77a9a07
--- /dev/null
+++ b/pcb/proxmark3_fix/CAM/proxmark3.dri
@@ -0,0 +1,41 @@
+Generated by EAGLE CAM Processor 6.4.0
+
+Drill Station Info File: proxmark3.dri
+
+ Date              : 2015.11.13. 16:16:25
+ Drills            : generated
+ Device            : Excellon drill station
+
+Parameter settings:
+
+ Tolerance Drill + :  0.00 %
+ Tolerance Drill - :  0.00 %
+ Rotate            : no
+ Mirror            : no
+ Optimize          : no
+ Auto fit          : yes
+ OffsetX           : 0inch
+ OffsetY           : 0inch
+ Layers            : Drills Holes
+
+Drill File Info:
+
+ Data Mode         : Absolute
+ Units             : 1/10000 Inch
+
+Drills used:
+
+ Code  Size       used
+
+ T01   0.0157inch   326
+ T02   0.0354inch     2
+ T03   0.0394inch     2
+ T04   0.0450inch    26
+ T05   0.0630inch     1
+ T06   0.0787inch     2
+
+Total number of drills: 359
+
+Plotfiles:
+
+ proxmark3.TXT

diff --git a/pcb/proxmark3_fix/CAM/proxmark3.gpi b/pcb/proxmark3_fix/CAM/proxmark3.gpi
new file mode 100644 (file)
index 0000000..2d5e684
--- /dev/null
+++ b/pcb/proxmark3_fix/CAM/proxmark3.gpi
@@ -0,0 +1,80 @@
+Generated by EAGLE CAM Processor 6.4.0
+
+Photoplotter Info File: proxmark3.gpi
+
+ Date              : 2015.11.13. 16:16:26
+ Plotfile          : proxmark3.GTL
+ Apertures         : generated: 
+ Device            : Gerber RS-274-X photoplotter, coordinate format 2.4 inch
+
+Parameter settings:
+
+ Emulate Apertures : no
+ Tolerance Draw  + :  0.00 %
+ Tolerance Draw  - :  0.00 %
+ Tolerance Flash + :  0.00 %
+ Tolerance Flash - :  0.00 %
+ Rotate            : no
+ Mirror            : no
+ Optimize          : yes
+ Auto fit          : yes
+ OffsetX           : 0inch
+ OffsetY           : 0inch
+
+Plotfile Info:
+
+ Coordinate Format : 2.4
+ Coordinate Units  : Inch
+ Data Mode         : Absolute
+ Zero Suppression  : None
+ End Of Block      : *
+
+Apertures used:
+
+ Code     Shape     Size                  used
+
+ D10      draw      0.0010inch               4
+ D11      draw      0.0160inch              89
+ D12      draw      0.0090inch              17
+ D13      draw      0.0110inch              16
+ D14      rectangle 0.0591inch x 0.0157inch    10
+ D15      rectangle 0.0906inch x 0.0197inch     5
+ D16      square    0.1378inch               4
+ D17      draw      0.0000inch               4
+ D18      rectangle 0.0433inch x 0.0394inch   126
+ D19      rectangle 0.0591inch x 0.0098inch    50
+ D20      rectangle 0.0098inch x 0.0492inch    50
+ D21      square    0.0945inch               4
+ D22      rectangle 0.0591inch x 0.0197inch     5
+ D23      rectangle 0.0098inch x 0.0787inch    32
+ D24      rectangle 0.0787inch x 0.0098inch    32
+ D25      rectangle 0.1496inch x 0.0906inch     2
+ D26      rectangle 0.0984inch x 0.0217inch     4
+ D27      rectangle 0.0142inch x 0.0512inch    28
+ D28      rectangle 0.0394inch x 0.0433inch    82
+ D29      rectangle 0.1142inch x 0.0591inch     6
+ D30      square    0.0675inch               2
+ D31      round     0.0675inch              24
+ D32      square    0.0400inch              18
+ D33      rectangle 0.0400inch x 0.0700inch     6
+ D34      rectangle 0.0700inch x 0.0400inch     3
+ D35      rectangle 0.0118inch x 0.0591inch    24
+ D36      rectangle 0.0142inch x 0.0551inch    40
+ D37      rectangle 0.0512inch x 0.0591inch     2
+ D38      rectangle 0.0128inch x 0.0709inch     8
+ D39      rectangle 0.0260inch x 0.0800inch     8
+ D40      rectangle 0.0591inch x 0.1142inch     2
+ D41      rectangle 0.0402inch x 0.0161inch     8
+ D42      rectangle 0.0394inch x 0.1181inch    10
+ D43      rectangle 0.1181inch x 0.0591inch     4
+ D44      rectangle 0.1378inch x 0.0591inch     2
+ D45      rectangle 0.0591inch x 0.1378inch     2
+ D46      rectangle 0.0700inch x 0.1350inch     1
+ D47      rectangle 0.1350inch x 0.0700inch     6
+ D48      round     0.0945inch               1
+ D49      rectangle 0.0800inch x 0.0260inch     8
+ D50      draw      0.0080inch            8696
+ D51      round     0.0317inch             326
+ D52      round     0.1575inch               2
+ D53      draw      0.0240inch              52
+

diff --git a/pcb/proxmark3_fix/IN1_layer_preview.png b/pcb/proxmark3_fix/IN1_layer_preview.png
new file mode 100644 (file)
index 0000000..f67aaab
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diff --git a/pcb/proxmark3_fix/IN2_layer_preview.png b/pcb/proxmark3_fix/IN2_layer_preview.png
new file mode 100644 (file)
index 0000000..3026b09
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diff --git a/pcb/proxmark3_fix/MFG/proxmark3_IN1.pdf b/pcb/proxmark3_fix/MFG/proxmark3_IN1.pdf
new file mode 100644 (file)
index 0000000..256c662
Binary files /dev/null and b/pcb/proxmark3_fix/MFG/proxmark3_IN1.pdf differ

diff --git a/pcb/proxmark3_fix/MFG/proxmark3_IN2.pdf b/pcb/proxmark3_fix/MFG/proxmark3_IN2.pdf
new file mode 100644 (file)
index 0000000..6382052
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diff --git a/pcb/proxmark3_fix/MFG/proxmark3_bot.pdf b/pcb/proxmark3_fix/MFG/proxmark3_bot.pdf
new file mode 100644 (file)
index 0000000..1969d3c
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diff --git a/pcb/proxmark3_fix/MFG/proxmark3_cam.zip b/pcb/proxmark3_fix/MFG/proxmark3_cam.zip
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index 0000000..3164e5b
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diff --git a/pcb/proxmark3_fix/MFG/proxmark3_sch.pdf b/pcb/proxmark3_fix/MFG/proxmark3_sch.pdf
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index 0000000..5e2b910
Binary files /dev/null and b/pcb/proxmark3_fix/MFG/proxmark3_sch.pdf differ

diff --git a/pcb/proxmark3_fix/MFG/proxmark3_top.pdf b/pcb/proxmark3_fix/MFG/proxmark3_top.pdf
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index 0000000..0edf7f1
Binary files /dev/null and b/pcb/proxmark3_fix/MFG/proxmark3_top.pdf differ

diff --git a/pcb/proxmark3_fix/README.md b/pcb/proxmark3_fix/README.md
new file mode 100644 (file)
index 0000000..774c59a
--- /dev/null
+++ b/pcb/proxmark3_fix/README.md
@@ -0,0 +1,3 @@
+Corrected Eagle layout files and re-generated CAM files. DRC checked (via eurocircuits.com 's PCB visualizer too) no problems found, ready to production!
+
+Please find the change list in the CAD folder text file.
\ No newline at end of file

diff --git a/pcb/proxmark3_fix/TOP_layer_preview.png b/pcb/proxmark3_fix/TOP_layer_preview.png
new file mode 100644 (file)
index 0000000..5bb1d2d
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