-# See the schematic for the pin assignment.\r
-\r
-NET "adc_d<0>" LOC = "P62" ; \r
-NET "adc_d<1>" LOC = "P60" ; \r
-NET "adc_d<2>" LOC = "P58" ; \r
-NET "adc_d<3>" LOC = "P57" ; \r
-NET "adc_d<4>" LOC = "P56" ; \r
-NET "adc_d<5>" LOC = "P55" ; \r
-NET "adc_d<6>" LOC = "P54" ; \r
-NET "adc_d<7>" LOC = "P53" ; \r
-#NET "cross_hi" LOC = "P88" ; \r
-#NET "miso" LOC = "P40" ; \r
-#PACE: Start of Constraints generated by PACE\r
-\r
-#PACE: Start of PACE I/O Pin Assignments\r
-NET "adc_clk" LOC = "P46" ; \r
-NET "adc_noe" LOC = "P47" ; \r
-NET "ck_1356meg" LOC = "P91" ; \r
-NET "ck_1356megb" LOC = "P93" ; \r
-NET "cross_lo" LOC = "P87" ; \r
-NET "dbg" LOC = "P22" ; \r
-NET "mosi" LOC = "P43" ; \r
-NET "ncs" LOC = "P44" ; \r
-NET "pck0" LOC = "P36" ; \r
-NET "pwr_hi" LOC = "P80" ; \r
-NET "pwr_lo" LOC = "P81" ; \r
-NET "pwr_oe1" LOC = "P82" ; \r
-NET "pwr_oe2" LOC = "P83" ; \r
-NET "pwr_oe3" LOC = "P84" ; \r
-NET "pwr_oe4" LOC = "P86" ; \r
-NET "spck" LOC = "P39" ; \r
-NET "ssp_clk" LOC = "P71" ; \r
-NET "ssp_din" LOC = "P32" ; \r
-NET "ssp_dout" LOC = "P34" ; \r
-NET "ssp_frame" LOC = "P31" ; \r
-\r
-#PACE: Start of PACE Area Constraints\r
-\r
-#PACE: Start of PACE Prohibit Constraints\r
-\r
-#PACE: End of Constraints generated by PACE\r
+# See the schematic for the pin assignment.
+
+NET "adc_d<0>" LOC = "P62" ;
+NET "adc_d<1>" LOC = "P60" ;
+NET "adc_d<2>" LOC = "P58" ;
+NET "adc_d<3>" LOC = "P57" ;
+NET "adc_d<4>" LOC = "P56" ;
+NET "adc_d<5>" LOC = "P55" ;
+NET "adc_d<6>" LOC = "P54" ;
+NET "adc_d<7>" LOC = "P53" ;
+#NET "cross_hi" LOC = "P88" ;
+#NET "miso" LOC = "P40" ;
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "adc_clk" LOC = "P46" ;
+NET "adc_noe" LOC = "P47" ;
+NET "ck_1356meg" LOC = "P91" ;
+NET "ck_1356megb" LOC = "P93" ;
+NET "cross_lo" LOC = "P87" ;
+NET "dbg" LOC = "P22" ;
+NET "mosi" LOC = "P43" ;
+NET "ncs" LOC = "P44" ;
+NET "pck0" LOC = "P36" ;
+NET "pwr_hi" LOC = "P80" ;
+NET "pwr_lo" LOC = "P81" ;
+NET "pwr_oe1" LOC = "P82" ;
+NET "pwr_oe2" LOC = "P83" ;
+NET "pwr_oe3" LOC = "P84" ;
+NET "pwr_oe4" LOC = "P86" ;
+NET "spck" LOC = "P39" ;
+NET "ssp_clk" LOC = "P71" ;
+NET "ssp_din" LOC = "P32" ;
+NET "ssp_dout" LOC = "P34" ;
+NET "ssp_frame" LOC = "P31" ;
+
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE
-//-----------------------------------------------------------------------------\r
-// The FPGA is responsible for interfacing between the A/D, the coil drivers,\r
-// and the ARM. In the low-frequency modes it passes the data straight\r
-// through, so that the ARM gets raw A/D samples over the SSP. In the high-\r
-// frequency modes, the FPGA might perform some demodulation first, to\r
-// reduce the amount of data that we must send to the ARM.\r
-//\r
-// I am not really an FPGA/ASIC designer, so I am sure that a lot of this\r
-// could be improved.\r
-//\r
-// Jonathan Westhues, March 2006\r
-// Added ISO14443-A support by Gerhard de Koning Gans, April 2008\r
-//-----------------------------------------------------------------------------\r
-\r
-`include "lo_read.v"\r
-`include "lo_passthru.v"\r
-`include "lo_simulate.v"\r
-`include "hi_read_tx.v"\r
-`include "hi_read_rx_xcorr.v"\r
-`include "hi_simulate.v"\r
-`include "hi_iso14443a.v"\r
-`include "util.v"\r
-\r
-module fpga(\r
- spcki, miso, mosi, ncs,\r
- pck0i, ck_1356meg, ck_1356megb,\r
- pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
- adc_d, adc_clk, adc_noe,\r
- ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
- cross_hi, cross_lo,\r
- dbg\r
-);\r
- input spcki, mosi, ncs;\r
- output miso;\r
- input pck0i, ck_1356meg, ck_1356megb;\r
- output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
- input [7:0] adc_d;\r
- output adc_clk, adc_noe;\r
- input ssp_dout;\r
- output ssp_frame, ssp_din, ssp_clk;\r
- input cross_hi, cross_lo;\r
- output dbg;\r
-\r
-//assign pck0 = pck0i;\r
- IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(\r
- .O(pck0),\r
- .I(pck0i)\r
- );\r
-//assign spck = spcki;\r
- IBUFG #(.IOSTANDARD("DEFAULT") ) spckb(\r
- .O(spck),\r
- .I(spcki)\r
- );\r
-//-----------------------------------------------------------------------------\r
-// The SPI receiver. This sets up the configuration word, which the rest of\r
-// the logic looks at to determine how to connect the A/D and the coil\r
-// drivers (i.e., which section gets it). Also assign some symbolic names\r
-// to the configuration bits, for use below.\r
-//-----------------------------------------------------------------------------\r
-\r
-reg [15:0] shift_reg;\r
-reg [7:0] divisor;\r
-reg [7:0] conf_word;\r
-\r
-// We switch modes between transmitting to the 13.56 MHz tag and receiving\r
-// from it, which means that we must make sure that we can do so without\r
-// glitching, or else we will glitch the transmitted carrier.\r
-always @(posedge ncs)\r
-begin\r
- case(shift_reg[15:12])\r
- 4'b0001: conf_word <= shift_reg[7:0];\r
- 4'b0010: divisor <= shift_reg[7:0];\r
- endcase\r
-end\r
-\r
-always @(posedge spck)\r
-begin\r
- if(~ncs)\r
- begin\r
- shift_reg[15:1] <= shift_reg[14:0];\r
- shift_reg[0] <= mosi;\r
- end\r
-end\r
-\r
-wire [2:0] major_mode;\r
-assign major_mode = conf_word[7:5];\r
-\r
-// For the low-frequency configuration:\r
-wire lo_is_125khz;\r
-assign lo_is_125khz = conf_word[3];\r
-\r
-// For the high-frequency transmit configuration: modulation depth, either\r
-// 100% (just quite driving antenna, steady LOW), or shallower (tri-state\r
-// some fraction of the buffers)\r
-wire hi_read_tx_shallow_modulation;\r
-assign hi_read_tx_shallow_modulation = conf_word[0];\r
-\r
-// For the high-frequency receive correlator: frequency against which to\r
-// correlate.\r
-wire hi_read_rx_xcorr_848;\r
-assign hi_read_rx_xcorr_848 = conf_word[0];\r
-// and whether to drive the coil (reader) or just short it (snooper)\r
-wire hi_read_rx_xcorr_snoop;\r
-assign hi_read_rx_xcorr_snoop = conf_word[1];\r
-\r
-// Divide the expected subcarrier frequency for hi_read_rx_xcorr by 4\r
-wire hi_read_rx_xcorr_quarter;\r
-assign hi_read_rx_xcorr_quarter = conf_word[2];\r
-\r
-// For the high-frequency simulated tag: what kind of modulation to use.\r
-wire [2:0] hi_simulate_mod_type;\r
-assign hi_simulate_mod_type = conf_word[2:0];\r
-\r
-//-----------------------------------------------------------------------------\r
-// And then we instantiate the modules corresponding to each of the FPGA's\r
-// major modes, and use muxes to connect the outputs of the active mode to\r
-// the output pins.\r
-//-----------------------------------------------------------------------------\r
-\r
-lo_read lr(\r
- pck0, ck_1356meg, ck_1356megb,\r
- lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,\r
- adc_d, lr_adc_clk,\r
- lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,\r
- cross_hi, cross_lo,\r
- lr_dbg,\r
- lo_is_125khz, divisor\r
-);\r
-\r
-lo_passthru lp(\r
- pck0, ck_1356meg, ck_1356megb,\r
- lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,\r
- adc_d, lp_adc_clk,\r
- lp_ssp_frame, lp_ssp_din, ssp_dout, lp_ssp_clk,\r
- cross_hi, cross_lo,\r
- lp_dbg, divisor\r
-);\r
-\r
-lo_simulate ls(\r
- pck0, ck_1356meg, ck_1356megb,\r
- ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4,\r
- adc_d, ls_adc_clk,\r
- ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,\r
- cross_hi, cross_lo,\r
- ls_dbg, divisor\r
-);\r
-\r
-hi_read_tx ht(\r
- pck0, ck_1356meg, ck_1356megb,\r
- ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,\r
- adc_d, ht_adc_clk,\r
- ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,\r
- cross_hi, cross_lo,\r
- ht_dbg,\r
- hi_read_tx_shallow_modulation\r
-);\r
-\r
-hi_read_rx_xcorr hrxc(\r
- pck0, ck_1356meg, ck_1356megb,\r
- hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,\r
- adc_d, hrxc_adc_clk,\r
- hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,\r
- cross_hi, cross_lo,\r
- hrxc_dbg,\r
- hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter\r
-);\r
-\r
-hi_simulate hs(\r
- pck0, ck_1356meg, ck_1356megb,\r
- hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,\r
- adc_d, hs_adc_clk,\r
- hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,\r
- cross_hi, cross_lo,\r
- hs_dbg,\r
- hi_simulate_mod_type\r
-);\r
-\r
-hi_iso14443a hisn(\r
- pck0, ck_1356meg, ck_1356megb,\r
- hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,\r
- adc_d, hisn_adc_clk,\r
- hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,\r
- cross_hi, cross_lo,\r
- hisn_dbg,\r
- hi_simulate_mod_type\r
-);\r
-\r
-// Major modes:\r
-// 000 -- LF reader (generic)\r
-// 001 -- LF simulated tag (generic)\r
-// 010 -- HF reader, transmitting to tag; modulation depth selectable\r
-// 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable\r
-// 100 -- HF simulated tag\r
-// 101 -- HF ISO14443-A\r
-// 110 -- LF passthrough\r
-// 111 -- everything off\r
-\r
-mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, lp_ssp_clk, 1'b0);\r
-mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, lp_ssp_din, 1'b0);\r
-mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, lp_ssp_frame, 1'b0);\r
-mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, lp_pwr_oe1, 1'b0);\r
-mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, lp_pwr_oe2, 1'b0);\r
-mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, lp_pwr_oe3, 1'b0);\r
-mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, lp_pwr_oe4, 1'b0);\r
-mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, lp_pwr_lo, 1'b0);\r
-mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, lp_pwr_hi, 1'b0);\r
-mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, lp_adc_clk, 1'b0);\r
-mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, lp_dbg, 1'b0);\r
-\r
-// In all modes, let the ADC's outputs be enabled.\r
-assign adc_noe = 1'b0;\r
-\r
-endmodule\r
+//-----------------------------------------------------------------------------
+// The FPGA is responsible for interfacing between the A/D, the coil drivers,
+// and the ARM. In the low-frequency modes it passes the data straight
+// through, so that the ARM gets raw A/D samples over the SSP. In the high-
+// frequency modes, the FPGA might perform some demodulation first, to
+// reduce the amount of data that we must send to the ARM.
+//
+// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
+// could be improved.
+//
+// Jonathan Westhues, March 2006
+// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
+//-----------------------------------------------------------------------------
+
+`include "lo_read.v"
+`include "lo_passthru.v"
+`include "lo_simulate.v"
+`include "hi_read_tx.v"
+`include "hi_read_rx_xcorr.v"
+`include "hi_simulate.v"
+`include "hi_iso14443a.v"
+`include "util.v"
+
+module fpga(
+ spcki, miso, mosi, ncs,
+ pck0i, ck_1356meg, ck_1356megb,
+ pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
+ adc_d, adc_clk, adc_noe,
+ ssp_frame, ssp_din, ssp_dout, ssp_clk,
+ cross_hi, cross_lo,
+ dbg
+);
+ input spcki, mosi, ncs;
+ output miso;
+ input pck0i, ck_1356meg, ck_1356megb;
+ output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
+ input [7:0] adc_d;
+ output adc_clk, adc_noe;
+ input ssp_dout;
+ output ssp_frame, ssp_din, ssp_clk;
+ input cross_hi, cross_lo;
+ output dbg;
+
+//assign pck0 = pck0i;
+ IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(
+ .O(pck0),
+ .I(pck0i)
+ );
+//assign spck = spcki;
+ IBUFG #(.IOSTANDARD("DEFAULT") ) spckb(
+ .O(spck),
+ .I(spcki)
+ );
+//-----------------------------------------------------------------------------
+// The SPI receiver. This sets up the configuration word, which the rest of
+// the logic looks at to determine how to connect the A/D and the coil
+// drivers (i.e., which section gets it). Also assign some symbolic names
+// to the configuration bits, for use below.
+//-----------------------------------------------------------------------------
+
+reg [15:0] shift_reg;
+reg [7:0] divisor;
+reg [7:0] conf_word;
+
+// We switch modes between transmitting to the 13.56 MHz tag and receiving
+// from it, which means that we must make sure that we can do so without
+// glitching, or else we will glitch the transmitted carrier.
+always @(posedge ncs)
+begin
+ case(shift_reg[15:12])
+ 4'b0001: conf_word <= shift_reg[7:0];
+ 4'b0010: divisor <= shift_reg[7:0];
+ endcase
+end
+
+always @(posedge spck)
+begin
+ if(~ncs)
+ begin
+ shift_reg[15:1] <= shift_reg[14:0];
+ shift_reg[0] <= mosi;
+ end
+end
+
+wire [2:0] major_mode;
+assign major_mode = conf_word[7:5];
+
+// For the low-frequency configuration:
+wire lo_is_125khz;
+assign lo_is_125khz = conf_word[3];
+
+// For the high-frequency transmit configuration: modulation depth, either
+// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
+// some fraction of the buffers)
+wire hi_read_tx_shallow_modulation;
+assign hi_read_tx_shallow_modulation = conf_word[0];
+
+// For the high-frequency receive correlator: frequency against which to
+// correlate.
+wire hi_read_rx_xcorr_848;
+assign hi_read_rx_xcorr_848 = conf_word[0];
+// and whether to drive the coil (reader) or just short it (snooper)
+wire hi_read_rx_xcorr_snoop;
+assign hi_read_rx_xcorr_snoop = conf_word[1];
+
+// Divide the expected subcarrier frequency for hi_read_rx_xcorr by 4
+wire hi_read_rx_xcorr_quarter;
+assign hi_read_rx_xcorr_quarter = conf_word[2];
+
+// For the high-frequency simulated tag: what kind of modulation to use.
+wire [2:0] hi_simulate_mod_type;
+assign hi_simulate_mod_type = conf_word[2:0];
+
+//-----------------------------------------------------------------------------
+// And then we instantiate the modules corresponding to each of the FPGA's
+// major modes, and use muxes to connect the outputs of the active mode to
+// the output pins.
+//-----------------------------------------------------------------------------
+
+lo_read lr(
+ pck0, ck_1356meg, ck_1356megb,
+ lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
+ adc_d, lr_adc_clk,
+ lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,
+ cross_hi, cross_lo,
+ lr_dbg,
+ lo_is_125khz, divisor
+);
+
+lo_passthru lp(
+ pck0, ck_1356meg, ck_1356megb,
+ lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
+ adc_d, lp_adc_clk,
+ lp_ssp_frame, lp_ssp_din, ssp_dout, lp_ssp_clk,
+ cross_hi, cross_lo,
+ lp_dbg, divisor
+);
+
+lo_simulate ls(
+ pck0, ck_1356meg, ck_1356megb,
+ ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4,
+ adc_d, ls_adc_clk,
+ ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,
+ cross_hi, cross_lo,
+ ls_dbg, divisor
+);
+
+hi_read_tx ht(
+ pck0, ck_1356meg, ck_1356megb,
+ ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
+ adc_d, ht_adc_clk,
+ ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
+ cross_hi, cross_lo,
+ ht_dbg,
+ hi_read_tx_shallow_modulation
+);
+
+hi_read_rx_xcorr hrxc(
+ pck0, ck_1356meg, ck_1356megb,
+ hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
+ adc_d, hrxc_adc_clk,
+ hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
+ cross_hi, cross_lo,
+ hrxc_dbg,
+ hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
+);
+
+hi_simulate hs(
+ pck0, ck_1356meg, ck_1356megb,
+ hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
+ adc_d, hs_adc_clk,
+ hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
+ cross_hi, cross_lo,
+ hs_dbg,
+ hi_simulate_mod_type
+);
+
+hi_iso14443a hisn(
+ pck0, ck_1356meg, ck_1356megb,
+ hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
+ adc_d, hisn_adc_clk,
+ hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
+ cross_hi, cross_lo,
+ hisn_dbg,
+ hi_simulate_mod_type
+);
+
+// Major modes:
+// 000 -- LF reader (generic)
+// 001 -- LF simulated tag (generic)
+// 010 -- HF reader, transmitting to tag; modulation depth selectable
+// 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
+// 100 -- HF simulated tag
+// 101 -- HF ISO14443-A
+// 110 -- LF passthrough
+// 111 -- everything off
+
+mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, lp_ssp_clk, 1'b0);
+mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, lp_ssp_din, 1'b0);
+mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, lp_ssp_frame, 1'b0);
+mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, lp_pwr_oe1, 1'b0);
+mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, lp_pwr_oe2, 1'b0);
+mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, lp_pwr_oe3, 1'b0);
+mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, lp_pwr_oe4, 1'b0);
+mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, lp_pwr_lo, 1'b0);
+mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, lp_pwr_hi, 1'b0);
+mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, lp_adc_clk, 1'b0);
+mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, lp_dbg, 1'b0);
+
+// In all modes, let the ADC's outputs be enabled.
+assign adc_noe = 1'b0;
+
+endmodule
-//-----------------------------------------------------------------------------\r
-//\r
-// Jonathan Westhues, April 2006\r
-//-----------------------------------------------------------------------------\r
-\r
-module hi_read_rx_xcorr(\r
- pck0, ck_1356meg, ck_1356megb,\r
- pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
- adc_d, adc_clk,\r
- ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
- cross_hi, cross_lo,\r
- dbg,\r
- xcorr_is_848, snoop, xcorr_quarter_freq\r
-);\r
- input pck0, ck_1356meg, ck_1356megb;\r
- output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
- input [7:0] adc_d;\r
- output adc_clk;\r
- input ssp_dout;\r
- output ssp_frame, ssp_din, ssp_clk;\r
- input cross_hi, cross_lo;\r
- output dbg;\r
- input xcorr_is_848, snoop, xcorr_quarter_freq;\r
-\r
-// Carrier is steady on through this, unless we're snooping.\r
-assign pwr_hi = ck_1356megb & (~snoop);\r
-assign pwr_oe1 = 1'b0;\r
-assign pwr_oe2 = 1'b0;\r
-assign pwr_oe3 = 1'b0;\r
-assign pwr_oe4 = 1'b0;\r
-\r
-reg ssp_clk;\r
-reg ssp_frame;\r
-\r
-reg fc_div_2;\r
-always @(posedge ck_1356meg)\r
- fc_div_2 = ~fc_div_2;\r
-\r
-reg fc_div_4;\r
-always @(posedge fc_div_2)\r
- fc_div_4 = ~fc_div_4;\r
-\r
-reg fc_div_8;\r
-always @(posedge fc_div_4)\r
- fc_div_8 = ~fc_div_8;\r
-\r
-reg adc_clk;\r
-\r
-always @(xcorr_is_848 or xcorr_quarter_freq or ck_1356meg)\r
- if(~xcorr_quarter_freq)\r
- begin\r
- if(xcorr_is_848)\r
- // The subcarrier frequency is fc/16; we will sample at fc, so that \r
- // means the subcarrier is 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 ...\r
- adc_clk <= ck_1356meg;\r
- else\r
- // The subcarrier frequency is fc/32; we will sample at fc/2, and\r
- // the subcarrier will look identical.\r
- adc_clk <= fc_div_2;\r
- end\r
- else\r
- begin\r
- if(xcorr_is_848)\r
- // The subcarrier frequency is fc/64\r
- adc_clk <= fc_div_4;\r
- else\r
- // The subcarrier frequency is fc/128\r
- adc_clk <= fc_div_8;\r
- end\r
-\r
-// When we're a reader, we just need to do the BPSK demod; but when we're an\r
-// eavesdropper, we also need to pick out the commands sent by the reader,\r
-// using AM. Do this the same way that we do it for the simulated tag.\r
-reg after_hysteresis, after_hysteresis_prev;\r
-reg [11:0] has_been_low_for;\r
-always @(negedge adc_clk)\r
-begin\r
- if(& adc_d[7:0]) after_hysteresis <= 1'b1;\r
- else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;\r
-\r
- if(after_hysteresis)\r
- begin\r
- has_been_low_for <= 7'b0;\r
- end\r
- else\r
- begin\r
- if(has_been_low_for == 12'd4095)\r
- begin\r
- has_been_low_for <= 12'd0;\r
- after_hysteresis <= 1'b1;\r
- end\r
- else\r
- has_been_low_for <= has_been_low_for + 1;\r
- end\r
-end\r
-\r
-// Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,\r
-// so we need a 6-bit counter.\r
-reg [5:0] corr_i_cnt;\r
-reg [5:0] corr_q_cnt;\r
-// And a couple of registers in which to accumulate the correlations.\r
-reg signed [15:0] corr_i_accum;\r
-reg signed [15:0] corr_q_accum;\r
-reg signed [7:0] corr_i_out;\r
-reg signed [7:0] corr_q_out;\r
-\r
-// ADC data appears on the rising edge, so sample it on the falling edge\r
-always @(negedge adc_clk)\r
-begin\r
- // These are the correlators: we correlate against in-phase and quadrature\r
- // versions of our reference signal, and keep the (signed) result to\r
- // send out later over the SSP.\r
- if(corr_i_cnt == 7'd63)\r
- begin\r
- if(snoop)\r
- begin\r
- corr_i_out <= {corr_i_accum[12:6], after_hysteresis_prev};\r
- corr_q_out <= {corr_q_accum[12:6], after_hysteresis};\r
- end\r
- else\r
- begin\r
- // Only correlations need to be delivered.\r
- corr_i_out <= corr_i_accum[13:6];\r
- corr_q_out <= corr_q_accum[13:6];\r
- end\r
-\r
- corr_i_accum <= adc_d;\r
- corr_q_accum <= adc_d;\r
- corr_q_cnt <= 4;\r
- corr_i_cnt <= 0;\r
- end\r
- else\r
- begin\r
- if(corr_i_cnt[3])\r
- corr_i_accum <= corr_i_accum - adc_d;\r
- else\r
- corr_i_accum <= corr_i_accum + adc_d;\r
-\r
- if(corr_q_cnt[3])\r
- corr_q_accum <= corr_q_accum - adc_d;\r
- else\r
- corr_q_accum <= corr_q_accum + adc_d;\r
-\r
- corr_i_cnt <= corr_i_cnt + 1;\r
- corr_q_cnt <= corr_q_cnt + 1;\r
- end\r
-\r
- // The logic in hi_simulate.v reports 4 samples per bit. We report two\r
- // (I, Q) pairs per bit, so we should do 2 samples per pair.\r
- if(corr_i_cnt == 6'd31)\r
- after_hysteresis_prev <= after_hysteresis;\r
-\r
- // Then the result from last time is serialized and send out to the ARM.\r
- // We get one report each cycle, and each report is 16 bits, so the\r
- // ssp_clk should be the adc_clk divided by 64/16 = 4.\r
-\r
- if(corr_i_cnt[1:0] == 2'b10)\r
- ssp_clk <= 1'b0;\r
-\r
- if(corr_i_cnt[1:0] == 2'b00)\r
- begin\r
- ssp_clk <= 1'b1;\r
- // Don't shift if we just loaded new data, obviously.\r
- if(corr_i_cnt != 7'd0)\r
- begin\r
- corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};\r
- corr_q_out[7:1] <= corr_q_out[6:0];\r
- end\r
- end\r
-\r
- if(corr_i_cnt[5:2] == 4'b000 || corr_i_cnt[5:2] == 4'b1000)\r
- ssp_frame = 1'b1;\r
- else\r
- ssp_frame = 1'b0;\r
-\r
-end\r
-\r
-assign ssp_din = corr_i_out[7];\r
-\r
-assign dbg = corr_i_cnt[3];\r
-\r
-// Unused.\r
-assign pwr_lo = 1'b0;\r
-\r
-endmodule\r
+//-----------------------------------------------------------------------------
+//
+// Jonathan Westhues, April 2006
+//-----------------------------------------------------------------------------
+
+module hi_read_rx_xcorr(
+ pck0, ck_1356meg, ck_1356megb,
+ pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
+ adc_d, adc_clk,
+ ssp_frame, ssp_din, ssp_dout, ssp_clk,
+ cross_hi, cross_lo,
+ dbg,
+ xcorr_is_848, snoop, xcorr_quarter_freq
+);
+ input pck0, ck_1356meg, ck_1356megb;
+ output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
+ input [7:0] adc_d;
+ output adc_clk;
+ input ssp_dout;
+ output ssp_frame, ssp_din, ssp_clk;
+ input cross_hi, cross_lo;
+ output dbg;
+ input xcorr_is_848, snoop, xcorr_quarter_freq;
+
+// Carrier is steady on through this, unless we're snooping.
+assign pwr_hi = ck_1356megb & (~snoop);
+assign pwr_oe1 = 1'b0;
+assign pwr_oe2 = 1'b0;
+assign pwr_oe3 = 1'b0;
+assign pwr_oe4 = 1'b0;
+
+reg ssp_clk;
+reg ssp_frame;
+
+reg fc_div_2;
+always @(posedge ck_1356meg)
+ fc_div_2 = ~fc_div_2;
+
+reg fc_div_4;
+always @(posedge fc_div_2)
+ fc_div_4 = ~fc_div_4;
+
+reg fc_div_8;
+always @(posedge fc_div_4)
+ fc_div_8 = ~fc_div_8;
+
+reg adc_clk;
+
+always @(xcorr_is_848 or xcorr_quarter_freq or ck_1356meg)
+ if(~xcorr_quarter_freq)
+ begin
+ if(xcorr_is_848)
+ // The subcarrier frequency is fc/16; we will sample at fc, so that
+ // means the subcarrier is 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 ...
+ adc_clk <= ck_1356meg;
+ else
+ // The subcarrier frequency is fc/32; we will sample at fc/2, and
+ // the subcarrier will look identical.
+ adc_clk <= fc_div_2;
+ end
+ else
+ begin
+ if(xcorr_is_848)
+ // The subcarrier frequency is fc/64
+ adc_clk <= fc_div_4;
+ else
+ // The subcarrier frequency is fc/128
+ adc_clk <= fc_div_8;
+ end
+
+// When we're a reader, we just need to do the BPSK demod; but when we're an
+// eavesdropper, we also need to pick out the commands sent by the reader,
+// using AM. Do this the same way that we do it for the simulated tag.
+reg after_hysteresis, after_hysteresis_prev;
+reg [11:0] has_been_low_for;
+always @(negedge adc_clk)
+begin
+ if(& adc_d[7:0]) after_hysteresis <= 1'b1;
+ else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
+
+ if(after_hysteresis)
+ begin
+ has_been_low_for <= 7'b0;
+ end
+ else
+ begin
+ if(has_been_low_for == 12'd4095)
+ begin
+ has_been_low_for <= 12'd0;
+ after_hysteresis <= 1'b1;
+ end
+ else
+ has_been_low_for <= has_been_low_for + 1;
+ end
+end
+
+// Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,
+// so we need a 6-bit counter.
+reg [5:0] corr_i_cnt;
+reg [5:0] corr_q_cnt;
+// And a couple of registers in which to accumulate the correlations.
+reg signed [15:0] corr_i_accum;
+reg signed [15:0] corr_q_accum;
+reg signed [7:0] corr_i_out;
+reg signed [7:0] corr_q_out;
+
+// ADC data appears on the rising edge, so sample it on the falling edge
+always @(negedge adc_clk)
+begin
+ // These are the correlators: we correlate against in-phase and quadrature
+ // versions of our reference signal, and keep the (signed) result to
+ // send out later over the SSP.
+ if(corr_i_cnt == 7'd63)
+ begin
+ if(snoop)
+ begin
+ corr_i_out <= {corr_i_accum[12:6], after_hysteresis_prev};
+ corr_q_out <= {corr_q_accum[12:6], after_hysteresis};
+ end
+ else
+ begin
+ // Only correlations need to be delivered.
+ corr_i_out <= corr_i_accum[13:6];
+ corr_q_out <= corr_q_accum[13:6];
+ end
+
+ corr_i_accum <= adc_d;
+ corr_q_accum <= adc_d;
+ corr_q_cnt <= 4;
+ corr_i_cnt <= 0;
+ end
+ else
+ begin
+ if(corr_i_cnt[3])
+ corr_i_accum <= corr_i_accum - adc_d;
+ else
+ corr_i_accum <= corr_i_accum + adc_d;
+
+ if(corr_q_cnt[3])
+ corr_q_accum <= corr_q_accum - adc_d;
+ else
+ corr_q_accum <= corr_q_accum + adc_d;
+
+ corr_i_cnt <= corr_i_cnt + 1;
+ corr_q_cnt <= corr_q_cnt + 1;
+ end
+
+ // The logic in hi_simulate.v reports 4 samples per bit. We report two
+ // (I, Q) pairs per bit, so we should do 2 samples per pair.
+ if(corr_i_cnt == 6'd31)
+ after_hysteresis_prev <= after_hysteresis;
+
+ // Then the result from last time is serialized and send out to the ARM.
+ // We get one report each cycle, and each report is 16 bits, so the
+ // ssp_clk should be the adc_clk divided by 64/16 = 4.
+
+ if(corr_i_cnt[1:0] == 2'b10)
+ ssp_clk <= 1'b0;
+
+ if(corr_i_cnt[1:0] == 2'b00)
+ begin
+ ssp_clk <= 1'b1;
+ // Don't shift if we just loaded new data, obviously.
+ if(corr_i_cnt != 7'd0)
+ begin
+ corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
+ corr_q_out[7:1] <= corr_q_out[6:0];
+ end
+ end
+
+ if(corr_i_cnt[5:2] == 4'b000 || corr_i_cnt[5:2] == 4'b1000)
+ ssp_frame = 1'b1;
+ else
+ ssp_frame = 1'b0;
+
+end
+
+assign ssp_din = corr_i_out[7];
+
+assign dbg = corr_i_cnt[3];
+
+// Unused.
+assign pwr_lo = 1'b0;
+
+endmodule
-//-----------------------------------------------------------------------------\r
-// The way that we connect things when transmitting a command to an ISO\r
-// 15693 tag, using 100% modulation only for now.\r
-//\r
-// Jonathan Westhues, April 2006\r
-//-----------------------------------------------------------------------------\r
-\r
-module hi_read_tx(\r
- pck0, ck_1356meg, ck_1356megb,\r
- pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
- adc_d, adc_clk,\r
- ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
- cross_hi, cross_lo,\r
- dbg,\r
- shallow_modulation\r
-);\r
- input pck0, ck_1356meg, ck_1356megb;\r
- output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
- input [7:0] adc_d;\r
- output adc_clk;\r
- input ssp_dout;\r
- output ssp_frame, ssp_din, ssp_clk;\r
- input cross_hi, cross_lo;\r
- output dbg;\r
- input shallow_modulation;\r
-\r
-// The high-frequency stuff. For now, for testing, just bring out the carrier,\r
-// and allow the ARM to modulate it over the SSP.\r
-reg pwr_hi;\r
-reg pwr_oe1;\r
-reg pwr_oe2;\r
-reg pwr_oe3;\r
-reg pwr_oe4;\r
-always @(ck_1356megb or ssp_dout or shallow_modulation)\r
-begin\r
- if(shallow_modulation)\r
- begin\r
- pwr_hi <= ck_1356megb;\r
- pwr_oe1 <= ~ssp_dout;\r
- pwr_oe2 <= ~ssp_dout;\r
- pwr_oe3 <= ~ssp_dout;\r
- pwr_oe4 <= 1'b0;\r
- end\r
- else\r
- begin\r
- pwr_hi <= ck_1356megb & ssp_dout;\r
- pwr_oe1 <= 1'b0;\r
- pwr_oe2 <= 1'b0;\r
- pwr_oe3 <= 1'b0;\r
- pwr_oe4 <= 1'b0;\r
- end\r
-end\r
-\r
-// Then just divide the 13.56 MHz clock down to produce appropriate clocks\r
-// for the synchronous serial port.\r
-\r
-reg [6:0] hi_div_by_128;\r
-\r
-always @(posedge ck_1356meg)\r
- hi_div_by_128 <= hi_div_by_128 + 1;\r
-\r
-assign ssp_clk = hi_div_by_128[6];\r
-\r
-reg [2:0] hi_byte_div;\r
-\r
-always @(negedge ssp_clk)\r
- hi_byte_div <= hi_byte_div + 1;\r
-\r
-assign ssp_frame = (hi_byte_div == 3'b000);\r
-\r
-// Implement a hysteresis to give out the received signal on\r
-// ssp_din. Sample at fc.\r
-assign adc_clk = ck_1356meg;\r
-\r
-// ADC data appears on the rising edge, so sample it on the falling edge\r
-reg after_hysteresis;\r
-always @(negedge adc_clk)\r
-begin\r
- if(& adc_d[7:0]) after_hysteresis <= 1'b1;\r
- else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;\r
-end\r
-\r
-\r
-assign ssp_din = after_hysteresis;\r
-\r
-assign pwr_lo = 1'b0;\r
-assign dbg = ssp_din;\r
-\r
-endmodule\r
+//-----------------------------------------------------------------------------
+// The way that we connect things when transmitting a command to an ISO
+// 15693 tag, using 100% modulation only for now.
+//
+// Jonathan Westhues, April 2006
+//-----------------------------------------------------------------------------
+
+module hi_read_tx(
+ pck0, ck_1356meg, ck_1356megb,
+ pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
+ adc_d, adc_clk,
+ ssp_frame, ssp_din, ssp_dout, ssp_clk,
+ cross_hi, cross_lo,
+ dbg,
+ shallow_modulation
+);
+ input pck0, ck_1356meg, ck_1356megb;
+ output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
+ input [7:0] adc_d;
+ output adc_clk;
+ input ssp_dout;
+ output ssp_frame, ssp_din, ssp_clk;
+ input cross_hi, cross_lo;
+ output dbg;
+ input shallow_modulation;
+
+// The high-frequency stuff. For now, for testing, just bring out the carrier,
+// and allow the ARM to modulate it over the SSP.
+reg pwr_hi;
+reg pwr_oe1;
+reg pwr_oe2;
+reg pwr_oe3;
+reg pwr_oe4;
+always @(ck_1356megb or ssp_dout or shallow_modulation)
+begin
+ if(shallow_modulation)
+ begin
+ pwr_hi <= ck_1356megb;
+ pwr_oe1 <= ~ssp_dout;
+ pwr_oe2 <= ~ssp_dout;
+ pwr_oe3 <= ~ssp_dout;
+ pwr_oe4 <= 1'b0;
+ end
+ else
+ begin
+ pwr_hi <= ck_1356megb & ssp_dout;
+ pwr_oe1 <= 1'b0;
+ pwr_oe2 <= 1'b0;
+ pwr_oe3 <= 1'b0;
+ pwr_oe4 <= 1'b0;
+ end
+end
+
+// Then just divide the 13.56 MHz clock down to produce appropriate clocks
+// for the synchronous serial port.
+
+reg [6:0] hi_div_by_128;
+
+always @(posedge ck_1356meg)
+ hi_div_by_128 <= hi_div_by_128 + 1;
+
+assign ssp_clk = hi_div_by_128[6];
+
+reg [2:0] hi_byte_div;
+
+always @(negedge ssp_clk)
+ hi_byte_div <= hi_byte_div + 1;
+
+assign ssp_frame = (hi_byte_div == 3'b000);
+
+// Implement a hysteresis to give out the received signal on
+// ssp_din. Sample at fc.
+assign adc_clk = ck_1356meg;
+
+// ADC data appears on the rising edge, so sample it on the falling edge
+reg after_hysteresis;
+always @(negedge adc_clk)
+begin
+ if(& adc_d[7:0]) after_hysteresis <= 1'b1;
+ else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
+end
+
+
+assign ssp_din = after_hysteresis;
+
+assign pwr_lo = 1'b0;
+assign dbg = ssp_din;
+
+endmodule
-//-----------------------------------------------------------------------------\r
-// Pretend to be an ISO 14443 tag. We will do this by alternately short-\r
-// circuiting and open-circuiting the antenna coil, with the tri-state\r
-// pins. \r
-//\r
-// We communicate over the SSP, as a bitstream (i.e., might as well be\r
-// unframed, though we still generate the word sync signal). The output\r
-// (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA\r
-// -> ARM) is us using the A/D as a fancy comparator; this is with\r
-// (software-added) hysteresis, to undo the high-pass filter.\r
-//\r
-// At this point only Type A is implemented. This means that we are using a\r
-// bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make\r
-// things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)\r
-//\r
-// Jonathan Westhues, October 2006\r
-//-----------------------------------------------------------------------------\r
-\r
-module hi_simulate(\r
- pck0, ck_1356meg, ck_1356megb,\r
- pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
- adc_d, adc_clk,\r
- ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
- cross_hi, cross_lo,\r
- dbg,\r
- mod_type\r
-);\r
- input pck0, ck_1356meg, ck_1356megb;\r
- output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
- input [7:0] adc_d;\r
- output adc_clk;\r
- input ssp_dout;\r
- output ssp_frame, ssp_din, ssp_clk;\r
- input cross_hi, cross_lo;\r
- output dbg;\r
- input [2:0] mod_type;\r
-\r
-// Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can\r
-// always be low.\r
-assign pwr_hi = 1'b0;\r
-assign pwr_lo = 1'b0;\r
-\r
-// The comparator with hysteresis on the output from the peak detector.\r
-reg after_hysteresis;\r
-assign adc_clk = ck_1356meg;\r
-\r
-always @(negedge adc_clk)\r
-begin\r
- if(& adc_d[7:5]) after_hysteresis = 1'b1;\r
- else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;\r
-end\r
-\r
-// Divide 13.56 MHz by 32 to produce the SSP_CLK\r
-// The register is bigger to allow higher division factors of up to /128\r
-reg [6:0] ssp_clk_divider;\r
-always @(posedge adc_clk)\r
- ssp_clk_divider <= (ssp_clk_divider + 1);\r
-assign ssp_clk = ssp_clk_divider[4];\r
-\r
-// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of\r
-// this is arbitrary, because it's just a bitstream.\r
-// One nasty issue, though: I can't make it work with both rx and tx at\r
-// once. The phase wrt ssp_clk must be changed. TODO to find out why\r
-// that is and make a better fix.\r
-reg [2:0] ssp_frame_divider_to_arm;\r
-always @(posedge ssp_clk)\r
- ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1);\r
-reg [2:0] ssp_frame_divider_from_arm;\r
-always @(negedge ssp_clk)\r
- ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);\r
-\r
-reg ssp_frame;\r
-always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)\r
- if(mod_type == 3'b000) // not modulating, so listening, to ARM\r
- ssp_frame = (ssp_frame_divider_to_arm == 3'b000);\r
- else\r
- ssp_frame = (ssp_frame_divider_from_arm == 3'b000);\r
-\r
-// Synchronize up the after-hysteresis signal, to produce DIN.\r
-reg ssp_din;\r
-always @(posedge ssp_clk)\r
- ssp_din = after_hysteresis;\r
-\r
-// Modulating carrier frequency is fc/16, reuse ssp_clk divider for that\r
-reg modulating_carrier;\r
-always @(mod_type or ssp_clk or ssp_dout)\r
- if(mod_type == 3'b000)\r
- modulating_carrier <= 1'b0; // no modulation\r
- else if(mod_type == 3'b001)\r
- modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK\r
- else if(mod_type == 3'b010)\r
- modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off\r
- else\r
- modulating_carrier <= 1'b0; // yet unused\r
-\r
-// This one is all LF, so doesn't matter\r
-assign pwr_oe2 = modulating_carrier;\r
-\r
-// Toggle only one of these, since we are already producing much deeper\r
-// modulation than a real tag would.\r
-assign pwr_oe1 = modulating_carrier;\r
-assign pwr_oe4 = modulating_carrier;\r
-\r
-// This one is always on, so that we can watch the carrier.\r
-assign pwr_oe3 = 1'b0;\r
-\r
-assign dbg = after_hysteresis;\r
-\r
-endmodule\r
+//-----------------------------------------------------------------------------
+// Pretend to be an ISO 14443 tag. We will do this by alternately short-
+// circuiting and open-circuiting the antenna coil, with the tri-state
+// pins.
+//
+// We communicate over the SSP, as a bitstream (i.e., might as well be
+// unframed, though we still generate the word sync signal). The output
+// (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA
+// -> ARM) is us using the A/D as a fancy comparator; this is with
+// (software-added) hysteresis, to undo the high-pass filter.
+//
+// At this point only Type A is implemented. This means that we are using a
+// bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
+// things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
+//
+// Jonathan Westhues, October 2006
+//-----------------------------------------------------------------------------
+
+module hi_simulate(
+ pck0, ck_1356meg, ck_1356megb,
+ pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
+ adc_d, adc_clk,
+ ssp_frame, ssp_din, ssp_dout, ssp_clk,
+ cross_hi, cross_lo,
+ dbg,
+ mod_type
+);
+ input pck0, ck_1356meg, ck_1356megb;
+ output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
+ input [7:0] adc_d;
+ output adc_clk;
+ input ssp_dout;
+ output ssp_frame, ssp_din, ssp_clk;
+ input cross_hi, cross_lo;
+ output dbg;
+ input [2:0] mod_type;
+
+// Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can
+// always be low.
+assign pwr_hi = 1'b0;
+assign pwr_lo = 1'b0;
+
+// The comparator with hysteresis on the output from the peak detector.
+reg after_hysteresis;
+assign adc_clk = ck_1356meg;
+
+always @(negedge adc_clk)
+begin
+ if(& adc_d[7:5]) after_hysteresis = 1'b1;
+ else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;
+end
+
+// Divide 13.56 MHz by 32 to produce the SSP_CLK
+// The register is bigger to allow higher division factors of up to /128
+reg [6:0] ssp_clk_divider;
+always @(posedge adc_clk)
+ ssp_clk_divider <= (ssp_clk_divider + 1);
+assign ssp_clk = ssp_clk_divider[4];
+
+// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
+// this is arbitrary, because it's just a bitstream.
+// One nasty issue, though: I can't make it work with both rx and tx at
+// once. The phase wrt ssp_clk must be changed. TODO to find out why
+// that is and make a better fix.
+reg [2:0] ssp_frame_divider_to_arm;
+always @(posedge ssp_clk)
+ ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1);
+reg [2:0] ssp_frame_divider_from_arm;
+always @(negedge ssp_clk)
+ ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
+
+reg ssp_frame;
+always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
+ if(mod_type == 3'b000) // not modulating, so listening, to ARM
+ ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
+ else
+ ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
+
+// Synchronize up the after-hysteresis signal, to produce DIN.
+reg ssp_din;
+always @(posedge ssp_clk)
+ ssp_din = after_hysteresis;
+
+// Modulating carrier frequency is fc/16, reuse ssp_clk divider for that
+reg modulating_carrier;
+always @(mod_type or ssp_clk or ssp_dout)
+ if(mod_type == 3'b000)
+ modulating_carrier <= 1'b0; // no modulation
+ else if(mod_type == 3'b001)
+ modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
+ else if(mod_type == 3'b010)
+ modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
+ else
+ modulating_carrier <= 1'b0; // yet unused
+
+// This one is all LF, so doesn't matter
+assign pwr_oe2 = modulating_carrier;
+
+// Toggle only one of these, since we are already producing much deeper
+// modulation than a real tag would.
+assign pwr_oe1 = modulating_carrier;
+assign pwr_oe4 = modulating_carrier;
+
+// This one is always on, so that we can watch the carrier.
+assign pwr_oe3 = 1'b0;
+
+assign dbg = after_hysteresis;
+
+endmodule
-//-----------------------------------------------------------------------------\r
-// For reading TI tags, we need to place the FPGA in pass through mode\r
-// and pass everything through to the ARM\r
-//-----------------------------------------------------------------------------\r
-\r
-module lo_passthru(\r
- pck0, ck_1356meg, ck_1356megb,\r
- pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
- adc_d, adc_clk,\r
- ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
- cross_hi, cross_lo,\r
- dbg, divisor\r
-);\r
- input pck0, ck_1356meg, ck_1356megb;\r
- output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
- input [7:0] adc_d;\r
- output adc_clk;\r
- input ssp_dout;\r
- output ssp_frame, ssp_din, ssp_clk;\r
- input cross_hi, cross_lo;\r
- output dbg;\r
- input [7:0] divisor;\r
-\r
-reg [7:0] pck_divider;\r
-reg ant_lo;\r
-\r
-// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo\r
-// which is high for (divisor+1) pck0 cycles and low for the same duration\r
-// ant_lo is therefore a 50% duty cycle clock signal with a frequency of\r
-// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk\r
-always @(posedge pck0)\r
-begin\r
- if(pck_divider == divisor[7:0])\r
- begin\r
- pck_divider <= 8'd0;\r
- ant_lo = !ant_lo;\r
- end\r
- else\r
- begin\r
- pck_divider <= pck_divider + 1;\r
- end\r
-end\r
-\r
-// the antenna is modulated when ssp_dout = 1, when 0 the\r
-// antenna drivers stop modulating and go into listen mode\r
-assign pwr_oe3 = 1'b0;\r
-assign pwr_oe1 = ssp_dout;\r
-assign pwr_oe2 = ssp_dout;\r
-assign pwr_oe4 = ssp_dout;\r
-assign pwr_lo = ant_lo && ssp_dout;\r
-assign pwr_hi = 1'b0;\r
-assign adc_clk = 1'b0;\r
-assign ssp_din = cross_lo;\r
-assign dbg = cross_lo;\r
-\r
-endmodule\r
+//-----------------------------------------------------------------------------
+// For reading TI tags, we need to place the FPGA in pass through mode
+// and pass everything through to the ARM
+//-----------------------------------------------------------------------------
+
+module lo_passthru(
+ pck0, ck_1356meg, ck_1356megb,
+ pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
+ adc_d, adc_clk,
+ ssp_frame, ssp_din, ssp_dout, ssp_clk,
+ cross_hi, cross_lo,
+ dbg, divisor
+);
+ input pck0, ck_1356meg, ck_1356megb;
+ output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
+ input [7:0] adc_d;
+ output adc_clk;
+ input ssp_dout;
+ output ssp_frame, ssp_din, ssp_clk;
+ input cross_hi, cross_lo;
+ output dbg;
+ input [7:0] divisor;
+
+reg [7:0] pck_divider;
+reg ant_lo;
+
+// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo
+// which is high for (divisor+1) pck0 cycles and low for the same duration
+// ant_lo is therefore a 50% duty cycle clock signal with a frequency of
+// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk
+always @(posedge pck0)
+begin
+ if(pck_divider == divisor[7:0])
+ begin
+ pck_divider <= 8'd0;
+ ant_lo = !ant_lo;
+ end
+ else
+ begin
+ pck_divider <= pck_divider + 1;
+ end
+end
+
+// the antenna is modulated when ssp_dout = 1, when 0 the
+// antenna drivers stop modulating and go into listen mode
+assign pwr_oe3 = 1'b0;
+assign pwr_oe1 = ssp_dout;
+assign pwr_oe2 = ssp_dout;
+assign pwr_oe4 = ssp_dout;
+assign pwr_lo = ant_lo && ssp_dout;
+assign pwr_hi = 1'b0;
+assign adc_clk = 1'b0;
+assign ssp_din = cross_lo;
+assign dbg = cross_lo;
+
+endmodule
-//-----------------------------------------------------------------------------\r
-// The way that we connect things in low-frequency read mode. In this case\r
-// we are generating the unmodulated low frequency carrier.\r
-// The A/D samples at that same rate and the result is serialized.\r
-//\r
-// Jonathan Westhues, April 2006\r
-//-----------------------------------------------------------------------------\r
-\r
-module lo_read(\r
- pck0, ck_1356meg, ck_1356megb,\r
- pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
- adc_d, adc_clk,\r
- ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
- cross_hi, cross_lo,\r
- dbg,\r
- lo_is_125khz, divisor\r
-);\r
- input pck0, ck_1356meg, ck_1356megb;\r
- output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
- input [7:0] adc_d;\r
- output adc_clk;\r
- input ssp_dout;\r
- output ssp_frame, ssp_din, ssp_clk;\r
- input cross_hi, cross_lo;\r
- output dbg;\r
- input lo_is_125khz; // redundant signal, no longer used anywhere\r
- input [7:0] divisor;\r
-\r
-reg [7:0] to_arm_shiftreg;\r
-reg [7:0] pck_divider;\r
-reg ant_lo;\r
-\r
-// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo\r
-// which is high for (divisor+1) pck0 cycles and low for the same duration\r
-// ant_lo is therefore a 50% duty cycle clock signal with a frequency of\r
-// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk\r
-always @(posedge pck0)\r
-begin\r
- if(pck_divider == divisor[7:0])\r
- begin\r
- pck_divider <= 8'd0;\r
- ant_lo = !ant_lo;\r
- end\r
- else\r
- begin\r
- pck_divider <= pck_divider + 1;\r
- end\r
-end\r
-\r
-// this task also runs at pck0 frequency (24Mhz) and is used to serialize\r
-// the ADC output which is then clocked into the ARM SSP.\r
-\r
-// because ant_lo always transitions when pck_divider = 0 we use the\r
-// pck_divider counter to sync our other signals off it\r
-// we read the ADC value when pck_divider=7 and shift it out on counts 8..15\r
-always @(posedge pck0)\r
-begin\r
- if((pck_divider == 8'd7) && !ant_lo)\r
- to_arm_shiftreg <= adc_d;\r
- else\r
- begin\r
- to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];\r
- // simulation showed a glitch occuring due to the LSB of the shifter\r
- // not being set as we shift bits out\r
- // this ensures the ssp_din remains low after a transfer and suppresses\r
- // the glitch that would occur when the last data shifted out ended in\r
- // a 1 bit and the next data shifted out started with a 0 bit\r
- to_arm_shiftreg[0] <= 1'b0;\r
- end\r
-end\r
-\r
-// ADC samples on falling edge of adc_clk, data available on the rising edge\r
-\r
-// example of ssp transfer of binary value 1100101\r
-// start of transfer is indicated by the rise of the ssp_frame signal\r
-// ssp_din changes on the rising edge of the ssp_clk clock and is clocked into\r
-// the ARM by the falling edge of ssp_clk\r
-// _______________________________\r
-// ssp_frame__| |__\r
-// _______ ___ ___\r
-// ssp_din __| |_______| |___| |______\r
-// _ _ _ _ _ _ _ _ _ _\r
-// ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_\r
-\r
-// serialized SSP data is gated by ant_lo to suppress unwanted signal\r
-assign ssp_din = to_arm_shiftreg[7] && !ant_lo;\r
-// SSP clock always runs at 24Mhz\r
-assign ssp_clk = pck0;\r
-// SSP frame is gated by ant_lo and goes high when pck_divider=8..15\r
-assign ssp_frame = (pck_divider[7:3] == 5'd1) && !ant_lo;\r
-// unused signals tied low\r
-assign pwr_hi = 1'b0;\r
-assign pwr_oe1 = 1'b0;\r
-assign pwr_oe2 = 1'b0;\r
-assign pwr_oe3 = 1'b0;\r
-assign pwr_oe4 = 1'b0;\r
-// this is the antenna driver signal\r
-assign pwr_lo = ant_lo;\r
-// ADC clock out of phase with antenna driver\r
-assign adc_clk = ~ant_lo;\r
-// ADC clock also routed to debug pin\r
-assign dbg = adc_clk;\r
-endmodule\r
+//-----------------------------------------------------------------------------
+// The way that we connect things in low-frequency read mode. In this case
+// we are generating the unmodulated low frequency carrier.
+// The A/D samples at that same rate and the result is serialized.
+//
+// Jonathan Westhues, April 2006
+//-----------------------------------------------------------------------------
+
+module lo_read(
+ pck0, ck_1356meg, ck_1356megb,
+ pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
+ adc_d, adc_clk,
+ ssp_frame, ssp_din, ssp_dout, ssp_clk,
+ cross_hi, cross_lo,
+ dbg,
+ lo_is_125khz, divisor
+);
+ input pck0, ck_1356meg, ck_1356megb;
+ output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
+ input [7:0] adc_d;
+ output adc_clk;
+ input ssp_dout;
+ output ssp_frame, ssp_din, ssp_clk;
+ input cross_hi, cross_lo;
+ output dbg;
+ input lo_is_125khz; // redundant signal, no longer used anywhere
+ input [7:0] divisor;
+
+reg [7:0] to_arm_shiftreg;
+reg [7:0] pck_divider;
+reg ant_lo;
+
+// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo
+// which is high for (divisor+1) pck0 cycles and low for the same duration
+// ant_lo is therefore a 50% duty cycle clock signal with a frequency of
+// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk
+always @(posedge pck0)
+begin
+ if(pck_divider == divisor[7:0])
+ begin
+ pck_divider <= 8'd0;
+ ant_lo = !ant_lo;
+ end
+ else
+ begin
+ pck_divider <= pck_divider + 1;
+ end
+end
+
+// this task also runs at pck0 frequency (24Mhz) and is used to serialize
+// the ADC output which is then clocked into the ARM SSP.
+
+// because ant_lo always transitions when pck_divider = 0 we use the
+// pck_divider counter to sync our other signals off it
+// we read the ADC value when pck_divider=7 and shift it out on counts 8..15
+always @(posedge pck0)
+begin
+ if((pck_divider == 8'd7) && !ant_lo)
+ to_arm_shiftreg <= adc_d;
+ else
+ begin
+ to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
+ // simulation showed a glitch occuring due to the LSB of the shifter
+ // not being set as we shift bits out
+ // this ensures the ssp_din remains low after a transfer and suppresses
+ // the glitch that would occur when the last data shifted out ended in
+ // a 1 bit and the next data shifted out started with a 0 bit
+ to_arm_shiftreg[0] <= 1'b0;
+ end
+end
+
+// ADC samples on falling edge of adc_clk, data available on the rising edge
+
+// example of ssp transfer of binary value 1100101
+// start of transfer is indicated by the rise of the ssp_frame signal
+// ssp_din changes on the rising edge of the ssp_clk clock and is clocked into
+// the ARM by the falling edge of ssp_clk
+// _______________________________
+// ssp_frame__| |__
+// _______ ___ ___
+// ssp_din __| |_______| |___| |______
+// _ _ _ _ _ _ _ _ _ _
+// ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
+
+// serialized SSP data is gated by ant_lo to suppress unwanted signal
+assign ssp_din = to_arm_shiftreg[7] && !ant_lo;
+// SSP clock always runs at 24Mhz
+assign ssp_clk = pck0;
+// SSP frame is gated by ant_lo and goes high when pck_divider=8..15
+assign ssp_frame = (pck_divider[7:3] == 5'd1) && !ant_lo;
+// unused signals tied low
+assign pwr_hi = 1'b0;
+assign pwr_oe1 = 1'b0;
+assign pwr_oe2 = 1'b0;
+assign pwr_oe3 = 1'b0;
+assign pwr_oe4 = 1'b0;
+// this is the antenna driver signal
+assign pwr_lo = ant_lo;
+// ADC clock out of phase with antenna driver
+assign adc_clk = ~ant_lo;
+// ADC clock also routed to debug pin
+assign dbg = adc_clk;
+endmodule
-//-----------------------------------------------------------------------------\r
-// The way that we connect things in low-frequency simulation mode. In this\r
-// case just pass everything through to the ARM, which can bit-bang this\r
-// (because it is so slow).\r
-//\r
-// Jonathan Westhues, April 2006\r
-//-----------------------------------------------------------------------------\r
-\r
-module lo_simulate(\r
- pck0, ck_1356meg, ck_1356megb,\r
- pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
- adc_d, adc_clk,\r
- ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
- cross_hi, cross_lo,\r
+//-----------------------------------------------------------------------------
+// The way that we connect things in low-frequency simulation mode. In this
+// case just pass everything through to the ARM, which can bit-bang this
+// (because it is so slow).
+//
+// Jonathan Westhues, April 2006
+//-----------------------------------------------------------------------------
+
+module lo_simulate(
+ pck0, ck_1356meg, ck_1356megb,
+ pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
+ adc_d, adc_clk,
+ ssp_frame, ssp_din, ssp_dout, ssp_clk,
+ cross_hi, cross_lo,
dbg,
- divisor\r
-);\r
- input pck0, ck_1356meg, ck_1356megb;\r
- output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
- input [7:0] adc_d;\r
- output adc_clk;\r
- input ssp_dout;\r
- output ssp_frame, ssp_din, ssp_clk;\r
- input cross_hi, cross_lo;\r
+ divisor
+);
+ input pck0, ck_1356meg, ck_1356megb;
+ output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
+ input [7:0] adc_d;
+ output adc_clk;
+ input ssp_dout;
+ output ssp_frame, ssp_din, ssp_clk;
+ input cross_hi, cross_lo;
output dbg;
- input [7:0] divisor;\r
-\r
-// No logic, straight through.\r
-assign pwr_oe3 = 1'b0;\r
-assign pwr_oe1 = ssp_dout;\r
-assign pwr_oe2 = ssp_dout;\r
-assign pwr_oe4 = ssp_dout;\r
-assign ssp_clk = cross_lo;\r
-assign pwr_lo = 1'b0;\r
-assign pwr_hi = 1'b0;\r
-assign dbg = ssp_frame;\r
+ input [7:0] divisor;
+
+// No logic, straight through.
+assign pwr_oe3 = 1'b0;
+assign pwr_oe1 = ssp_dout;
+assign pwr_oe2 = ssp_dout;
+assign pwr_oe4 = ssp_dout;
+assign ssp_clk = cross_lo;
+assign pwr_lo = 1'b0;
+assign pwr_hi = 1'b0;
+assign dbg = ssp_frame;
// Divide the clock to be used for the ADC
reg [7:0] pck_divider;
reg clk_state;
-\r
-always @(posedge pck0)\r
-begin\r
- if(pck_divider == divisor[7:0])\r
- begin\r
+
+always @(posedge pck0)
+begin
+ if(pck_divider == divisor[7:0])
+ begin
pck_divider <= 8'd0;
- clk_state = !clk_state;\r
- end\r
- else\r
- begin\r
- pck_divider <= pck_divider + 1;\r
- end\r
-end\r
+ clk_state = !clk_state;
+ end
+ else
+ begin
+ pck_divider <= pck_divider + 1;
+ end
+end
assign adc_clk = ~clk_state;
reg is_low;
reg output_state;
-always @(posedge pck0)\r
-begin\r
+always @(posedge pck0)
+begin
if((pck_divider == 8'd7) && !clk_state) begin
is_high = (adc_d >= 8'd200);
is_low = (adc_d <= 8'd64);
end
assign ssp_frame = output_state;
-\r
-endmodule\r
+
+endmodule
+
-#------------------------------------------------------------------------------\r
-# Run the simulation testbench in ModelSim: recompile both Verilog source\r
-# files, then start the simulation, add a lot of signals to the waveform\r
-# viewer, and run. I should (TODO) fix the absolute paths at some point.\r
-#\r
-# Jonathan Westhues, Mar 2006\r
-#------------------------------------------------------------------------------\r
-\r
-vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga.v\r
-vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga_tb.v\r
-\r
-vsim work.fpga_tb\r
-\r
-add wave sim:/fpga_tb/adc_clk\r
-add wave sim:/fpga_tb/adc_d\r
-add wave sim:/fpga_tb/pwr_lo\r
-add wave sim:/fpga_tb/ssp_clk\r
-add wave sim:/fpga_tb/ssp_frame\r
-add wave sim:/fpga_tb/ssp_din\r
-add wave sim:/fpga_tb/ssp_dout\r
-\r
-add wave sim:/fpga_tb/dut/clk_lo\r
-add wave sim:/fpga_tb/dut/pck_divider\r
-add wave sim:/fpga_tb/dut/carrier_divider_lo\r
-add wave sim:/fpga_tb/dut/conf_word\r
-\r
-run 30000\r
+#------------------------------------------------------------------------------
+# Run the simulation testbench in ModelSim: recompile both Verilog source
+# files, then start the simulation, add a lot of signals to the waveform
+# viewer, and run. I should (TODO) fix the absolute paths at some point.
+#
+# Jonathan Westhues, Mar 2006
+#------------------------------------------------------------------------------
+
+vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga.v
+vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga_tb.v
+
+vsim work.fpga_tb
+
+add wave sim:/fpga_tb/adc_clk
+add wave sim:/fpga_tb/adc_d
+add wave sim:/fpga_tb/pwr_lo
+add wave sim:/fpga_tb/ssp_clk
+add wave sim:/fpga_tb/ssp_frame
+add wave sim:/fpga_tb/ssp_din
+add wave sim:/fpga_tb/ssp_dout
+
+add wave sim:/fpga_tb/dut/clk_lo
+add wave sim:/fpga_tb/dut/pck_divider
+add wave sim:/fpga_tb/dut/carrier_divider_lo
+add wave sim:/fpga_tb/dut/conf_word
+
+run 30000
-`include "fpga.v"\r
-\r
-module testbed_fpga;\r
- reg spck, mosi, ncs;\r
- wire miso;\r
- reg pck0i, ck_1356meg, ck_1356megb;\r
- wire pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
- reg [7:0] adc_d;\r
- wire adc_clk, adc_noe;\r
- reg ssp_dout;\r
- wire ssp_frame, ssp_din, ssp_clk;\r
-\r
- fpga dut(\r
- spck, miso, mosi, ncs,\r
- pck0i, ck_1356meg, ck_1356megb,\r
- pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
- adc_d, adc_clk, adc_noe,\r
- ssp_frame, ssp_din, ssp_dout, ssp_clk\r
- );\r
-\r
- integer i;\r
-\r
- initial begin\r
-\r
- // init inputs\r
- #5 ncs=1;\r
- #5 spck = 1;\r
- #5 mosi = 1;\r
-\r
- #50 ncs=0;\r
- for (i = 0 ; i < 8 ; i = i + 1) begin\r
- #5 mosi = $random;\r
- #5 spck = 0;\r
- #5 spck = 1;\r
- end\r
- #5 ncs=1;\r
-\r
- #50 ncs=0;\r
- for (i = 0 ; i < 8 ; i = i + 1) begin\r
- #5 mosi = $random;\r
- #5 spck = 0;\r
- #5 spck = 1;\r
- end\r
- #5 ncs=1;\r
-\r
- #50 mosi=1;\r
- $finish;\r
- end\r
- \r
-endmodule // main\r
+`include "fpga.v"
+
+module testbed_fpga;
+ reg spck, mosi, ncs;
+ wire miso;
+ reg pck0i, ck_1356meg, ck_1356megb;
+ wire pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
+ reg [7:0] adc_d;
+ wire adc_clk, adc_noe;
+ reg ssp_dout;
+ wire ssp_frame, ssp_din, ssp_clk;
+
+ fpga dut(
+ spck, miso, mosi, ncs,
+ pck0i, ck_1356meg, ck_1356megb,
+ pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
+ adc_d, adc_clk, adc_noe,
+ ssp_frame, ssp_din, ssp_dout, ssp_clk
+ );
+
+ integer i;
+
+ initial begin
+
+ // init inputs
+ #5 ncs=1;
+ #5 spck = 1;
+ #5 mosi = 1;
+
+ #50 ncs=0;
+ for (i = 0 ; i < 8 ; i = i + 1) begin
+ #5 mosi = $random;
+ #5 spck = 0;
+ #5 spck = 1;
+ end
+ #5 ncs=1;
+
+ #50 ncs=0;
+ for (i = 0 ; i < 8 ; i = i + 1) begin
+ #5 mosi = $random;
+ #5 spck = 0;
+ #5 spck = 1;
+ end
+ #5 ncs=1;
+
+ #50 mosi=1;
+ $finish;
+ end
+
+endmodule // main
-`include "hi_read_tx.v"\r
-\r
-/*\r
- pck0 - input main 24Mhz clock (PLL / 4)\r
- [7:0] adc_d - input data from A/D converter\r
- shallow_modulation - modulation type\r
-\r
- pwr_lo - output to coil drivers (ssp_clk / 8)\r
- adc_clk - output A/D clock signal\r
- ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)\r
- ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)\r
- ssp_clk - output SSP clock signal\r
-\r
- ck_1356meg - input unused\r
- ck_1356megb - input unused\r
- ssp_dout - input unused\r
- cross_hi - input unused\r
- cross_lo - input unused\r
-\r
- pwr_hi - output unused, tied low\r
- pwr_oe1 - output unused, undefined\r
- pwr_oe2 - output unused, undefined\r
- pwr_oe3 - output unused, undefined\r
- pwr_oe4 - output unused, undefined\r
- dbg - output alias for adc_clk\r
-*/\r
-\r
-module testbed_hi_read_tx;\r
- reg pck0;\r
- reg [7:0] adc_d;\r
- reg shallow_modulation;\r
-\r
- wire pwr_lo;\r
- wire adc_clk;\r
- reg ck_1356meg;\r
- reg ck_1356megb;\r
- wire ssp_frame;\r
- wire ssp_din;\r
- wire ssp_clk;\r
- reg ssp_dout;\r
- wire pwr_hi;\r
- wire pwr_oe1;\r
- wire pwr_oe2;\r
- wire pwr_oe3;\r
- wire pwr_oe4;\r
- wire cross_lo;\r
- wire cross_hi;\r
- wire dbg;\r
-\r
- hi_read_tx #(5,200) dut(\r
- .pck0(pck0),\r
- .ck_1356meg(ck_1356meg),\r
- .ck_1356megb(ck_1356megb),\r
- .pwr_lo(pwr_lo),\r
- .pwr_hi(pwr_hi),\r
- .pwr_oe1(pwr_oe1),\r
- .pwr_oe2(pwr_oe2),\r
- .pwr_oe3(pwr_oe3),\r
- .pwr_oe4(pwr_oe4),\r
- .adc_d(adc_d),\r
- .adc_clk(adc_clk),\r
- .ssp_frame(ssp_frame),\r
- .ssp_din(ssp_din),\r
- .ssp_dout(ssp_dout),\r
- .ssp_clk(ssp_clk),\r
- .cross_hi(cross_hi),\r
- .cross_lo(cross_lo),\r
- .dbg(dbg),\r
- .shallow_modulation(shallow_modulation)\r
- );\r
-\r
- integer idx, i;\r
-\r
- // main clock\r
- always #5 begin \r
- ck_1356megb = !ck_1356megb;\r
- ck_1356meg = ck_1356megb;\r
- end\r
-\r
- //crank DUT\r
- task crank_dut;\r
- begin\r
- @(posedge ssp_clk) ;\r
- ssp_dout = $random;\r
- end\r
- endtask\r
-\r
- initial begin\r
-\r
- // init inputs\r
- ck_1356megb = 0;\r
- adc_d = 0;\r
- ssp_dout=0;\r
-\r
- // shallow modulation off\r
- shallow_modulation=0;\r
- for (i = 0 ; i < 16 ; i = i + 1) begin\r
- crank_dut;\r
- end\r
-\r
- // shallow modulation on\r
- shallow_modulation=1;\r
- for (i = 0 ; i < 16 ; i = i + 1) begin\r
- crank_dut;\r
- end\r
- $finish;\r
- end\r
- \r
-endmodule // main\r
+`include "hi_read_tx.v"
+
+/*
+ pck0 - input main 24Mhz clock (PLL / 4)
+ [7:0] adc_d - input data from A/D converter
+ shallow_modulation - modulation type
+
+ pwr_lo - output to coil drivers (ssp_clk / 8)
+ adc_clk - output A/D clock signal
+ ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
+ ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
+ ssp_clk - output SSP clock signal
+
+ ck_1356meg - input unused
+ ck_1356megb - input unused
+ ssp_dout - input unused
+ cross_hi - input unused
+ cross_lo - input unused
+
+ pwr_hi - output unused, tied low
+ pwr_oe1 - output unused, undefined
+ pwr_oe2 - output unused, undefined
+ pwr_oe3 - output unused, undefined
+ pwr_oe4 - output unused, undefined
+ dbg - output alias for adc_clk
+*/
+
+module testbed_hi_read_tx;
+ reg pck0;
+ reg [7:0] adc_d;
+ reg shallow_modulation;
+
+ wire pwr_lo;
+ wire adc_clk;
+ reg ck_1356meg;
+ reg ck_1356megb;
+ wire ssp_frame;
+ wire ssp_din;
+ wire ssp_clk;
+ reg ssp_dout;
+ wire pwr_hi;
+ wire pwr_oe1;
+ wire pwr_oe2;
+ wire pwr_oe3;
+ wire pwr_oe4;
+ wire cross_lo;
+ wire cross_hi;
+ wire dbg;
+
+ hi_read_tx #(5,200) dut(
+ .pck0(pck0),
+ .ck_1356meg(ck_1356meg),
+ .ck_1356megb(ck_1356megb),
+ .pwr_lo(pwr_lo),
+ .pwr_hi(pwr_hi),
+ .pwr_oe1(pwr_oe1),
+ .pwr_oe2(pwr_oe2),
+ .pwr_oe3(pwr_oe3),
+ .pwr_oe4(pwr_oe4),
+ .adc_d(adc_d),
+ .adc_clk(adc_clk),
+ .ssp_frame(ssp_frame),
+ .ssp_din(ssp_din),
+ .ssp_dout(ssp_dout),
+ .ssp_clk(ssp_clk),
+ .cross_hi(cross_hi),
+ .cross_lo(cross_lo),
+ .dbg(dbg),
+ .shallow_modulation(shallow_modulation)
+ );
+
+ integer idx, i;
+
+ // main clock
+ always #5 begin
+ ck_1356megb = !ck_1356megb;
+ ck_1356meg = ck_1356megb;
+ end
+
+ //crank DUT
+ task crank_dut;
+ begin
+ @(posedge ssp_clk) ;
+ ssp_dout = $random;
+ end
+ endtask
+
+ initial begin
+
+ // init inputs
+ ck_1356megb = 0;
+ adc_d = 0;
+ ssp_dout=0;
+
+ // shallow modulation off
+ shallow_modulation=0;
+ for (i = 0 ; i < 16 ; i = i + 1) begin
+ crank_dut;
+ end
+
+ // shallow modulation on
+ shallow_modulation=1;
+ for (i = 0 ; i < 16 ; i = i + 1) begin
+ crank_dut;
+ end
+ $finish;
+ end
+
+endmodule // main
-`include "hi_simulate.v"\r
-\r
-/*\r
- pck0 - input main 24Mhz clock (PLL / 4)\r
- [7:0] adc_d - input data from A/D converter\r
- mod_type - modulation type\r
-\r
- pwr_lo - output to coil drivers (ssp_clk / 8)\r
- adc_clk - output A/D clock signal\r
- ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)\r
- ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)\r
- ssp_clk - output SSP clock signal\r
-\r
- ck_1356meg - input unused\r
- ck_1356megb - input unused\r
- ssp_dout - input unused\r
- cross_hi - input unused\r
- cross_lo - input unused\r
-\r
- pwr_hi - output unused, tied low\r
- pwr_oe1 - output unused, undefined\r
- pwr_oe2 - output unused, undefined\r
- pwr_oe3 - output unused, undefined\r
- pwr_oe4 - output unused, undefined\r
- dbg - output alias for adc_clk\r
-*/\r
-\r
-module testbed_hi_simulate;\r
- reg pck0;\r
- reg [7:0] adc_d;\r
- reg mod_type;\r
-\r
- wire pwr_lo;\r
- wire adc_clk;\r
- reg ck_1356meg;\r
- reg ck_1356megb;\r
- wire ssp_frame;\r
- wire ssp_din;\r
- wire ssp_clk;\r
- reg ssp_dout;\r
- wire pwr_hi;\r
- wire pwr_oe1;\r
- wire pwr_oe2;\r
- wire pwr_oe3;\r
- wire pwr_oe4;\r
- wire cross_lo;\r
- wire cross_hi;\r
- wire dbg;\r
-\r
- hi_simulate #(5,200) dut(\r
- .pck0(pck0),\r
- .ck_1356meg(ck_1356meg),\r
- .ck_1356megb(ck_1356megb),\r
- .pwr_lo(pwr_lo),\r
- .pwr_hi(pwr_hi),\r
- .pwr_oe1(pwr_oe1),\r
- .pwr_oe2(pwr_oe2),\r
- .pwr_oe3(pwr_oe3),\r
- .pwr_oe4(pwr_oe4),\r
- .adc_d(adc_d),\r
- .adc_clk(adc_clk),\r
- .ssp_frame(ssp_frame),\r
- .ssp_din(ssp_din),\r
- .ssp_dout(ssp_dout),\r
- .ssp_clk(ssp_clk),\r
- .cross_hi(cross_hi),\r
- .cross_lo(cross_lo),\r
- .dbg(dbg),\r
- .mod_type(mod_type)\r
- );\r
-\r
- integer idx, i;\r
-\r
- // main clock\r
- always #5 begin \r
- ck_1356megb = !ck_1356megb;\r
- ck_1356meg = ck_1356megb;\r
- end\r
-\r
- always begin \r
- @(negedge adc_clk) ;\r
- adc_d = $random;\r
- end\r
-\r
- //crank DUT\r
- task crank_dut;\r
- begin\r
- @(negedge ssp_clk) ;\r
- ssp_dout = $random;\r
- end\r
- endtask\r
-\r
- initial begin\r
-\r
- // init inputs\r
- ck_1356megb = 0;\r
- // random values\r
- adc_d = 0;\r
- ssp_dout=1;\r
-\r
- // shallow modulation off\r
- mod_type=0;\r
- for (i = 0 ; i < 16 ; i = i + 1) begin\r
- crank_dut;\r
- end\r
-\r
- // shallow modulation on\r
- mod_type=1;\r
- for (i = 0 ; i < 16 ; i = i + 1) begin\r
- crank_dut;\r
- end\r
- $finish;\r
- end\r
- \r
-endmodule // main\r
-\r
+`include "hi_simulate.v"
+
+/*
+ pck0 - input main 24Mhz clock (PLL / 4)
+ [7:0] adc_d - input data from A/D converter
+ mod_type - modulation type
+
+ pwr_lo - output to coil drivers (ssp_clk / 8)
+ adc_clk - output A/D clock signal
+ ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
+ ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
+ ssp_clk - output SSP clock signal
+
+ ck_1356meg - input unused
+ ck_1356megb - input unused
+ ssp_dout - input unused
+ cross_hi - input unused
+ cross_lo - input unused
+
+ pwr_hi - output unused, tied low
+ pwr_oe1 - output unused, undefined
+ pwr_oe2 - output unused, undefined
+ pwr_oe3 - output unused, undefined
+ pwr_oe4 - output unused, undefined
+ dbg - output alias for adc_clk
+*/
+
+module testbed_hi_simulate;
+ reg pck0;
+ reg [7:0] adc_d;
+ reg mod_type;
+
+ wire pwr_lo;
+ wire adc_clk;
+ reg ck_1356meg;
+ reg ck_1356megb;
+ wire ssp_frame;
+ wire ssp_din;
+ wire ssp_clk;
+ reg ssp_dout;
+ wire pwr_hi;
+ wire pwr_oe1;
+ wire pwr_oe2;
+ wire pwr_oe3;
+ wire pwr_oe4;
+ wire cross_lo;
+ wire cross_hi;
+ wire dbg;
+
+ hi_simulate #(5,200) dut(
+ .pck0(pck0),
+ .ck_1356meg(ck_1356meg),
+ .ck_1356megb(ck_1356megb),
+ .pwr_lo(pwr_lo),
+ .pwr_hi(pwr_hi),
+ .pwr_oe1(pwr_oe1),
+ .pwr_oe2(pwr_oe2),
+ .pwr_oe3(pwr_oe3),
+ .pwr_oe4(pwr_oe4),
+ .adc_d(adc_d),
+ .adc_clk(adc_clk),
+ .ssp_frame(ssp_frame),
+ .ssp_din(ssp_din),
+ .ssp_dout(ssp_dout),
+ .ssp_clk(ssp_clk),
+ .cross_hi(cross_hi),
+ .cross_lo(cross_lo),
+ .dbg(dbg),
+ .mod_type(mod_type)
+ );
+
+ integer idx, i;
+
+ // main clock
+ always #5 begin
+ ck_1356megb = !ck_1356megb;
+ ck_1356meg = ck_1356megb;
+ end
+
+ always begin
+ @(negedge adc_clk) ;
+ adc_d = $random;
+ end
+
+ //crank DUT
+ task crank_dut;
+ begin
+ @(negedge ssp_clk) ;
+ ssp_dout = $random;
+ end
+ endtask
+
+ initial begin
+
+ // init inputs
+ ck_1356megb = 0;
+ // random values
+ adc_d = 0;
+ ssp_dout=1;
+
+ // shallow modulation off
+ mod_type=0;
+ for (i = 0 ; i < 16 ; i = i + 1) begin
+ crank_dut;
+ end
+
+ // shallow modulation on
+ mod_type=1;
+ for (i = 0 ; i < 16 ; i = i + 1) begin
+ crank_dut;
+ end
+ $finish;
+ end
+
+endmodule // main
+
-`include "lo_read.v"\r
-/*\r
- pck0 - input main 24Mhz clock (PLL / 4)\r
- [7:0] adc_d - input data from A/D converter\r
- lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)\r
-\r
- pwr_lo - output to coil drivers (ssp_clk / 8)\r
- adc_clk - output A/D clock signal\r
- ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)\r
- ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)\r
- ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )\r
-\r
- ck_1356meg - input unused\r
- ck_1356megb - input unused\r
- ssp_dout - input unused\r
- cross_hi - input unused\r
- cross_lo - input unused\r
-\r
- pwr_hi - output unused, tied low\r
- pwr_oe1 - output unused, undefined\r
- pwr_oe2 - output unused, undefined\r
- pwr_oe3 - output unused, undefined\r
- pwr_oe4 - output unused, undefined\r
- dbg - output alias for adc_clk\r
-*/\r
-\r
-module testbed_lo_read;\r
- reg pck0;\r
- reg [7:0] adc_d;\r
- reg lo_is_125khz;\r
- reg [15:0] divisor;\r
-\r
- wire pwr_lo;\r
- wire adc_clk;\r
- wire ck_1356meg;\r
- wire ck_1356megb;\r
- wire ssp_frame;\r
- wire ssp_din;\r
- wire ssp_clk;\r
- reg ssp_dout;\r
- wire pwr_hi;\r
- wire pwr_oe1;\r
- wire pwr_oe2;\r
- wire pwr_oe3;\r
- wire pwr_oe4;\r
- wire cross_lo;\r
- wire cross_hi;\r
- wire dbg;\r
-\r
- lo_read #(5,10) dut(\r
- .pck0(pck0),\r
- .ck_1356meg(ck_1356meg),\r
- .ck_1356megb(ck_1356megb),\r
- .pwr_lo(pwr_lo),\r
- .pwr_hi(pwr_hi),\r
- .pwr_oe1(pwr_oe1),\r
- .pwr_oe2(pwr_oe2),\r
- .pwr_oe3(pwr_oe3),\r
- .pwr_oe4(pwr_oe4),\r
- .adc_d(adc_d),\r
- .adc_clk(adc_clk),\r
- .ssp_frame(ssp_frame),\r
- .ssp_din(ssp_din),\r
- .ssp_dout(ssp_dout),\r
- .ssp_clk(ssp_clk),\r
- .cross_hi(cross_hi),\r
- .cross_lo(cross_lo),\r
- .dbg(dbg),\r
- .lo_is_125khz(lo_is_125khz),\r
- .divisor(divisor)\r
- );\r
-\r
- integer idx, i, adc_val=8;\r
-\r
- // main clock\r
- always #5 pck0 = !pck0;\r
-\r
- task crank_dut;\r
- begin\r
- @(posedge adc_clk) ;\r
- adc_d = adc_val;\r
- adc_val = (adc_val *2) + 53;\r
- end\r
- endtask\r
-\r
- initial begin\r
-\r
- // init inputs\r
- pck0 = 0;\r
- adc_d = 0;\r
- ssp_dout = 0;\r
- lo_is_125khz = 1;\r
- divisor = 255; //min 16, 95=125Khz, max 255\r
-\r
- // simulate 4 A/D cycles at 125Khz\r
- for (i = 0 ; i < 8 ; i = i + 1) begin\r
- crank_dut;\r
- end\r
- $finish;\r
- end\r
-endmodule // main\r
+`include "lo_read.v"
+/*
+ pck0 - input main 24Mhz clock (PLL / 4)
+ [7:0] adc_d - input data from A/D converter
+ lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)
+
+ pwr_lo - output to coil drivers (ssp_clk / 8)
+ adc_clk - output A/D clock signal
+ ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
+ ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
+ ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
+
+ ck_1356meg - input unused
+ ck_1356megb - input unused
+ ssp_dout - input unused
+ cross_hi - input unused
+ cross_lo - input unused
+
+ pwr_hi - output unused, tied low
+ pwr_oe1 - output unused, undefined
+ pwr_oe2 - output unused, undefined
+ pwr_oe3 - output unused, undefined
+ pwr_oe4 - output unused, undefined
+ dbg - output alias for adc_clk
+*/
+
+module testbed_lo_read;
+ reg pck0;
+ reg [7:0] adc_d;
+ reg lo_is_125khz;
+ reg [15:0] divisor;
+
+ wire pwr_lo;
+ wire adc_clk;
+ wire ck_1356meg;
+ wire ck_1356megb;
+ wire ssp_frame;
+ wire ssp_din;
+ wire ssp_clk;
+ reg ssp_dout;
+ wire pwr_hi;
+ wire pwr_oe1;
+ wire pwr_oe2;
+ wire pwr_oe3;
+ wire pwr_oe4;
+ wire cross_lo;
+ wire cross_hi;
+ wire dbg;
+
+ lo_read #(5,10) dut(
+ .pck0(pck0),
+ .ck_1356meg(ck_1356meg),
+ .ck_1356megb(ck_1356megb),
+ .pwr_lo(pwr_lo),
+ .pwr_hi(pwr_hi),
+ .pwr_oe1(pwr_oe1),
+ .pwr_oe2(pwr_oe2),
+ .pwr_oe3(pwr_oe3),
+ .pwr_oe4(pwr_oe4),
+ .adc_d(adc_d),
+ .adc_clk(adc_clk),
+ .ssp_frame(ssp_frame),
+ .ssp_din(ssp_din),
+ .ssp_dout(ssp_dout),
+ .ssp_clk(ssp_clk),
+ .cross_hi(cross_hi),
+ .cross_lo(cross_lo),
+ .dbg(dbg),
+ .lo_is_125khz(lo_is_125khz),
+ .divisor(divisor)
+ );
+
+ integer idx, i, adc_val=8;
+
+ // main clock
+ always #5 pck0 = !pck0;
+
+ task crank_dut;
+ begin
+ @(posedge adc_clk) ;
+ adc_d = adc_val;
+ adc_val = (adc_val *2) + 53;
+ end
+ endtask
+
+ initial begin
+
+ // init inputs
+ pck0 = 0;
+ adc_d = 0;
+ ssp_dout = 0;
+ lo_is_125khz = 1;
+ divisor = 255; //min 16, 95=125Khz, max 255
+
+ // simulate 4 A/D cycles at 125Khz
+ for (i = 0 ; i < 8 ; i = i + 1) begin
+ crank_dut;
+ end
+ $finish;
+ end
+endmodule // main
-`include "lo_simulate.v"\r
-\r
-/*\r
- pck0 - input main 24Mhz clock (PLL / 4)\r
- [7:0] adc_d - input data from A/D converter\r
-\r
-\r
- pwr_lo - output to coil drivers (ssp_clk / 8)\r
- adc_clk - output A/D clock signal\r
- ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)\r
- ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)\r
- ssp_clk - output SSP clock signal\r
-\r
- ck_1356meg - input unused\r
- ck_1356megb - input unused\r
- ssp_dout - input unused\r
- cross_hi - input unused\r
- cross_lo - input unused\r
-\r
- pwr_hi - output unused, tied low\r
- pwr_oe1 - output unused, undefined\r
- pwr_oe2 - output unused, undefined\r
- pwr_oe3 - output unused, undefined\r
- pwr_oe4 - output unused, undefined\r
- dbg - output alias for adc_clk\r
-*/\r
-\r
-module testbed_lo_simulate;\r
- reg pck0;\r
- reg [7:0] adc_d;\r
-\r
-\r
- wire pwr_lo;\r
- wire adc_clk;\r
- wire ck_1356meg;\r
- wire ck_1356megb;\r
- wire ssp_frame;\r
- wire ssp_din;\r
- wire ssp_clk;\r
- reg ssp_dout;\r
- wire pwr_hi;\r
- wire pwr_oe1;\r
- wire pwr_oe2;\r
- wire pwr_oe3;\r
- wire pwr_oe4;\r
- reg cross_lo;\r
- wire cross_hi;\r
- wire dbg;\r
-\r
- lo_simulate #(5,200) dut(\r
- .pck0(pck0),\r
- .ck_1356meg(ck_1356meg),\r
- .ck_1356megb(ck_1356megb),\r
- .pwr_lo(pwr_lo),\r
- .pwr_hi(pwr_hi),\r
- .pwr_oe1(pwr_oe1),\r
- .pwr_oe2(pwr_oe2),\r
- .pwr_oe3(pwr_oe3),\r
- .pwr_oe4(pwr_oe4),\r
- .adc_d(adc_d),\r
- .adc_clk(adc_clk),\r
- .ssp_frame(ssp_frame),\r
- .ssp_din(ssp_din),\r
- .ssp_dout(ssp_dout),\r
- .ssp_clk(ssp_clk),\r
- .cross_hi(cross_hi),\r
- .cross_lo(cross_lo),\r
- .dbg(dbg)\r
- );\r
-\r
-\r
- integer i, counter=0;\r
-\r
- // main clock\r
- always #5 pck0 = !pck0;\r
-\r
- //cross_lo is not really synced to pck0 but it's roughly pck0/192 (24Mhz/192=125Khz)\r
- task crank_dut;\r
- begin\r
- @(posedge pck0) ;\r
- counter = counter + 1;\r
- if (counter == 192) begin\r
- counter = 0;\r
- ssp_dout = $random;\r
- cross_lo = 1;\r
- end else begin\r
- cross_lo = 0;\r
- end\r
- \r
- end\r
- endtask\r
-\r
- initial begin\r
- pck0 = 0;\r
- for (i = 0 ; i < 4096 ; i = i + 1) begin\r
- crank_dut;\r
- end\r
- $finish;\r
- end\r
-\r
-endmodule // main\r
+`include "lo_simulate.v"
+
+/*
+ pck0 - input main 24Mhz clock (PLL / 4)
+ [7:0] adc_d - input data from A/D converter
+
+
+ pwr_lo - output to coil drivers (ssp_clk / 8)
+ adc_clk - output A/D clock signal
+ ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
+ ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
+ ssp_clk - output SSP clock signal
+
+ ck_1356meg - input unused
+ ck_1356megb - input unused
+ ssp_dout - input unused
+ cross_hi - input unused
+ cross_lo - input unused
+
+ pwr_hi - output unused, tied low
+ pwr_oe1 - output unused, undefined
+ pwr_oe2 - output unused, undefined
+ pwr_oe3 - output unused, undefined
+ pwr_oe4 - output unused, undefined
+ dbg - output alias for adc_clk
+*/
+
+module testbed_lo_simulate;
+ reg pck0;
+ reg [7:0] adc_d;
+
+
+ wire pwr_lo;
+ wire adc_clk;
+ wire ck_1356meg;
+ wire ck_1356megb;
+ wire ssp_frame;
+ wire ssp_din;
+ wire ssp_clk;
+ reg ssp_dout;
+ wire pwr_hi;
+ wire pwr_oe1;
+ wire pwr_oe2;
+ wire pwr_oe3;
+ wire pwr_oe4;
+ reg cross_lo;
+ wire cross_hi;
+ wire dbg;
+
+ lo_simulate #(5,200) dut(
+ .pck0(pck0),
+ .ck_1356meg(ck_1356meg),
+ .ck_1356megb(ck_1356megb),
+ .pwr_lo(pwr_lo),
+ .pwr_hi(pwr_hi),
+ .pwr_oe1(pwr_oe1),
+ .pwr_oe2(pwr_oe2),
+ .pwr_oe3(pwr_oe3),
+ .pwr_oe4(pwr_oe4),
+ .adc_d(adc_d),
+ .adc_clk(adc_clk),
+ .ssp_frame(ssp_frame),
+ .ssp_din(ssp_din),
+ .ssp_dout(ssp_dout),
+ .ssp_clk(ssp_clk),
+ .cross_hi(cross_hi),
+ .cross_lo(cross_lo),
+ .dbg(dbg)
+ );
+
+
+ integer i, counter=0;
+
+ // main clock
+ always #5 pck0 = !pck0;
+
+ //cross_lo is not really synced to pck0 but it's roughly pck0/192 (24Mhz/192=125Khz)
+ task crank_dut;
+ begin
+ @(posedge pck0) ;
+ counter = counter + 1;
+ if (counter == 192) begin
+ counter = 0;
+ ssp_dout = $random;
+ cross_lo = 1;
+ end else begin
+ cross_lo = 0;
+ end
+
+ end
+ endtask
+
+ initial begin
+ pck0 = 0;
+ for (i = 0 ; i < 4096 ; i = i + 1) begin
+ crank_dut;
+ end
+ $finish;
+ end
+
+endmodule // main
-//-----------------------------------------------------------------------------\r
-// General-purpose miscellany.\r
-//\r
-// Jonathan Westhues, April 2006.\r
-//-----------------------------------------------------------------------------\r
-\r
-module mux8(sel, y, x0, x1, x2, x3, x4, x5, x6, x7);\r
- input [2:0] sel;\r
- input x0, x1, x2, x3, x4, x5, x6, x7;\r
- output y;\r
- reg y;\r
-\r
-always @(x0 or x1 or x2 or x3 or x4 or x5 or x6 or x7 or sel)\r
-begin\r
- case (sel)\r
- 3'b000: y = x0;\r
- 3'b001: y = x1;\r
- 3'b010: y = x2;\r
- 3'b011: y = x3;\r
- 3'b100: y = x4;\r
- 3'b101: y = x5;\r
- 3'b110: y = x6;\r
- 3'b111: y = x7;\r
- endcase\r
-end\r
-\r
-endmodule\r
+//-----------------------------------------------------------------------------
+// General-purpose miscellany.
+//
+// Jonathan Westhues, April 2006.
+//-----------------------------------------------------------------------------
+
+module mux8(sel, y, x0, x1, x2, x3, x4, x5, x6, x7);
+ input [2:0] sel;
+ input x0, x1, x2, x3, x4, x5, x6, x7;
+ output y;
+ reg y;
+
+always @(x0 or x1 or x2 or x3 or x4 or x5 or x6 or x7 or sel)
+begin
+ case (sel)
+ 3'b000: y = x0;
+ 3'b001: y = x1;
+ 3'b010: y = x2;
+ 3'b011: y = x3;
+ 3'b100: y = x4;
+ 3'b101: y = x5;
+ 3'b110: y = x6;
+ 3'b111: y = x7;
+ endcase
+end
+
+endmodule
-run -ifn fpga.v -ifmt Verilog -ofn fpga.ngc -ofmt NGC -p xc2s30-6vq100 -opt_mode Speed -opt_level 1 -ent fpga\r
+run -ifn fpga.v -ifmt Verilog -ofn fpga.ngc -ofmt NGC -p xc2s30-6vq100 -opt_mode Speed -opt_level 1 -ent fpga
-#define our ports\r
-telnet_port 4444\r
-gdb_port 3333\r
-\r
-#commands specific to the Olimex ARM-USB-OCD Dongle\r
-interface ft2232\r
-ft2232_device_desc "Olimex OpenOCD JTAG"\r
-ft2232_layout "olimex-jtag"\r
-ft2232_vid_pid 0x15BA 0x0003\r
-jtag_speed 2\r
-jtag_nsrst_delay 200\r
-jtag_ntrst_delay 200\r
-\r
-#reset_config <signals> [combination] [trst_type] [srst_type]\r
-reset_config srst_only srst_pulls_trst\r
-\r
-#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>\r
-jtag_device 4 0x1 0xf 0xe\r
-\r
-#daemon_startup <'attach'|'reset'>\r
-daemon_startup reset\r
-\r
-#target <type> <endianess> <reset_mode> <jtag#> [variant]\r
-target arm7tdmi little run_and_init 0 arm7tdmi_r4\r
-\r
-#run_and_halt_time <target#> <time_in_ms>\r
-run_and_halt_time 0 30\r
-\r
-# commands below are specific to AT91sam7 Flash Programming\r
-# ---------------------------------------------------------\r
-\r
-#target_script specifies the flash programming script file\r
-target_script 0 reset script.ocd\r
-\r
-#working_area <target#> <address> <size> <'backup'|'nobackup'>\r
-working_area 0 0x40000000 0x4000 nobackup\r
-\r
-#flash bank at91sam7 0 0 0 0 <target#>\r
-flash bank at91sam7 0 0 0 0 0\r
+#define our ports
+telnet_port 4444
+gdb_port 3333
+
+#commands specific to the Olimex ARM-USB-OCD Dongle
+interface ft2232
+ft2232_device_desc "Olimex OpenOCD JTAG"
+ft2232_layout "olimex-jtag"
+ft2232_vid_pid 0x15BA 0x0003
+jtag_speed 2
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+#reset_config <signals> [combination] [trst_type] [srst_type]
+reset_config srst_only srst_pulls_trst
+
+#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>
+jtag_device 4 0x1 0xf 0xe
+
+#daemon_startup <'attach'|'reset'>
+daemon_startup reset
+
+#target <type> <endianess> <reset_mode> <jtag#> [variant]
+target arm7tdmi little run_and_init 0 arm7tdmi_r4
+
+#run_and_halt_time <target#> <time_in_ms>
+run_and_halt_time 0 30
+
+# commands below are specific to AT91sam7 Flash Programming
+# ---------------------------------------------------------
+
+#target_script specifies the flash programming script file
+target_script 0 reset script.ocd
+
+#working_area <target#> <address> <size> <'backup'|'nobackup'>
+working_area 0 0x40000000 0x4000 nobackup
+
+#flash bank at91sam7 0 0 0 0 <target#>
+flash bank at91sam7 0 0 0 0 0
-#define our ports\r
-telnet_port 4444\r
-gdb_port 3333\r
-\r
-#commands specific to the Amontec JTAGKey\r
-interface ft2232\r
-ft2232_device_desc "Amontec JTAGkey A"\r
-ft2232_layout jtagkey\r
-ft2232_vid_pid 0x0403 0xcff8\r
-jtag_khz 200\r
-jtag_nsrst_delay 200\r
-jtag_ntrst_delay 200\r
-\r
-#reset_config <signals> [combination] [trst_type] [srst_type]\r
-reset_config srst_only srst_pulls_trst\r
-\r
-jtag newtap sam7x256 cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x3f0f0f0f\r
-\r
-target create sam7x256.cpu arm7tdmi -endian little -chain-position sam7x256.cpu -variant arm7tdmi\r
-\r
-gdb_memory_map enable\r
-\r
-sam7x256.cpu configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x10000 -work-area-backup 0\r
-flash bank at91sam7 0x100000 0x40000 0 4 sam7x256.cpu\r
+#define our ports
+telnet_port 4444
+gdb_port 3333
+
+#commands specific to the Amontec JTAGKey
+interface ft2232
+ft2232_device_desc "Amontec JTAGkey A"
+ft2232_layout jtagkey
+ft2232_vid_pid 0x0403 0xcff8
+jtag_khz 200
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+#reset_config <signals> [combination] [trst_type] [srst_type]
+reset_config srst_only srst_pulls_trst
+
+jtag newtap sam7x256 cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x3f0f0f0f
+
+target create sam7x256.cpu arm7tdmi -endian little -chain-position sam7x256.cpu -variant arm7tdmi
+
+gdb_memory_map enable
+
+sam7x256.cpu configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x10000 -work-area-backup 0
+flash bank at91sam7 0x100000 0x40000 0 4 sam7x256.cpu
-telnet_port 4444\r
-gdb_port 3333\r
-\r
-interface parport\r
-parport_port 0x378\r
-parport_cable wiggler\r
-jtag_speed 0\r
-jtag_nsrst_delay 200\r
-jtag_ntrst_delay 200\r
-\r
-reset_config srst_only srst_pulls_trst\r
-\r
-jtag newtap sam7x256 cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x3f0f0f0f\r
-#jtag newtap xilinx tap -irlen 6 -ircapture 0x1 -irmask 0xf -expected-id 0x1c1a093\r
-\r
-target create sam7x256.cpu arm7tdmi -endian little -chain-position sam7x256.cpu -variant arm7tdmi\r
-sam7x256.cpu configure -event reset-init {\r
- # disable watchdog\r
- mww 0xfffffd44 0x00008000\r
- # enable user reset\r
- mww 0xfffffd08 0xa5000001\r
- # CKGR_MOR : enable the main oscillator\r
- mww 0xfffffc20 0x00000601\r
- sleep 10\r
- # CKGR_PLLR: 16 MHz * (5+1) /1 = 96Mhz\r
- mww 0xfffffc2c 0x00051c01\r
- sleep 10\r
- # PMC_MCKR : MCK = PLL / 2 = 48 MHz\r
- mww 0xfffffc30 0x00000007\r
- sleep 10\r
- # MC_FMR: flash mode (FWS=1,FMCN=60)\r
- mww 0xffffff60 0x003c0100\r
- sleep 100\r
-}\r
-\r
-gdb_memory_map enable\r
-\r
-sam7x256.cpu configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x10000 -work-area-backup 0\r
-flash bank at91sam7 0 0 0 0 0\r
+telnet_port 4444
+gdb_port 3333
+
+interface parport
+parport_port 0x378
+parport_cable wiggler
+jtag_speed 0
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+reset_config srst_only srst_pulls_trst
+
+jtag newtap sam7x256 cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x3f0f0f0f
+#jtag newtap xilinx tap -irlen 6 -ircapture 0x1 -irmask 0xf -expected-id 0x1c1a093
+
+target create sam7x256.cpu arm7tdmi -endian little -chain-position sam7x256.cpu -variant arm7tdmi
+sam7x256.cpu configure -event reset-init {
+ # disable watchdog
+ mww 0xfffffd44 0x00008000
+ # enable user reset
+ mww 0xfffffd08 0xa5000001
+ # CKGR_MOR : enable the main oscillator
+ mww 0xfffffc20 0x00000601
+ sleep 10
+ # CKGR_PLLR: 16 MHz * (5+1) /1 = 96Mhz
+ mww 0xfffffc2c 0x00051c01
+ sleep 10
+ # PMC_MCKR : MCK = PLL / 2 = 48 MHz
+ mww 0xfffffc30 0x00000007
+ sleep 10
+ # MC_FMR: flash mode (FWS=1,FMCN=60)
+ mww 0xffffff60 0x003c0100
+ sleep 100
+}
+
+gdb_memory_map enable
+
+sam7x256.cpu configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x10000 -work-area-backup 0
+flash bank at91sam7 0 0 0 0 0
projects / proxmark3-svn / commitdiff