FPGA changes ISO14443B:

* slightly increase reader field strength
* increase sensitivity when reading, allowing increased reading distance

diff --git a/fpga/fpga_hf.bit b/fpga/fpga_hf.bit
index b9f2e6292e42801a73b57aa3e43dff00191ec8b9..bd8cf8e7dcf7ae80756e29f2417a94da7e9dd290 100644 (file)
Binary files a/fpga/fpga_hf.bit and b/fpga/fpga_hf.bit differ

diff --git a/fpga/hi_read_rx_xcorr.v b/fpga/hi_read_rx_xcorr.v
index afa46c4437a2870f3065c03d4ed0cd7759f7ef4d..433d6736f1814c0f3cc529e807f8cfb70ed3c1eb 100644 (file)
--- a/fpga/hi_read_rx_xcorr.v
+++ b/fpga/hi_read_rx_xcorr.v
@@ -34,13 +34,13 @@ always @(negedge ck_1356megb)
 
 (* clock_signal = "yes" *) reg adc_clk;                                // sample frequency, always 16 * fc
 always @(ck_1356megb, xcorr_is_848, xcorr_quarter_freq, fc_div)
 
 (* clock_signal = "yes" *) reg adc_clk;                                // sample frequency, always 16 * fc
 always @(ck_1356megb, xcorr_is_848, xcorr_quarter_freq, fc_div)

-       if (xcorr_is_848 & ~xcorr_quarter_freq)                 // fc = 847.5 kHz
+       if (xcorr_is_848 & ~xcorr_quarter_freq)                 // fc = 847.5 kHz, standard ISO14443B

                adc_clk <= ck_1356megb;
                adc_clk <= ck_1356megb;

-       else if (~xcorr_is_848 & ~xcorr_quarter_freq)   // fc = 424.25 kHz 
+       else if (~xcorr_is_848 & ~xcorr_quarter_freq)   // fc = 423.75 kHz 

                adc_clk <= fc_div[0];
                adc_clk <= fc_div[0];

-       else if (xcorr_is_848 & xcorr_quarter_freq)             // fc = 212.125 kHz
+       else if (xcorr_is_848 & xcorr_quarter_freq)             // fc = 211.875 kHz

                adc_clk <= fc_div[1];
                adc_clk <= fc_div[1];

-       else                                                                                    // fc = 106.0625 kHz
+       else                                                                                    // fc = 105.9375 kHz

                adc_clk <= fc_div[2];
                
 // When we're a reader, we just need to do the BPSK demod; but when we're an
                adc_clk <= fc_div[2];
                
 // When we're a reader, we just need to do the BPSK demod; but when we're an


@@ -69,13 +69,16 @@ begin
     end
 end
 
     end
 end
 

-// Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,
+// Let us report a correlation every 4 subcarrier cycles, or 4*16=64 samples,

 // so we need a 6-bit counter.
 reg [5:0] corr_i_cnt;
 // And a couple of registers in which to accumulate the correlations.
 // so we need a 6-bit counter.
 reg [5:0] corr_i_cnt;
 // And a couple of registers in which to accumulate the correlations.

-// we would add/sub at most 32 times adc_d, the signed result can be held in 14 bits. 
-reg signed [13:0] corr_i_accum;
-reg signed [13:0] corr_q_accum;
+// We would add at most 32 times the difference between unmodulated and modulated signal. It should
+// be safe to assume that a tag will not be able to modulate the carrier signal by more than 25%.
+// 32 * 255 * 0,25 = 2040, which can be held in 11 bits. Add 1 bit for sign.
+reg signed [11:0] corr_i_accum;
+reg signed [11:0] corr_q_accum;
+// we will report maximum 8 significant bits

 reg signed [7:0] corr_i_out;
 reg signed [7:0] corr_q_out;
 // clock and frame signal for communication to ARM
 reg signed [7:0] corr_i_out;
 reg signed [7:0] corr_q_out;
 // clock and frame signal for communication to ARM


@@ -99,16 +102,16 @@ begin
     begin
         if(snoop)
         begin
     begin
         if(snoop)
         begin

-                       // Send only 7 most significant bits of tag signal (signed), LSB is reader signal:
-            corr_i_out <= {corr_i_accum[13:7], after_hysteresis_prev_prev};
-            corr_q_out <= {corr_q_accum[13:7], after_hysteresis_prev};
+                       // Send 7 most significant bits of tag signal (signed), plus 1 bit reader signal
+            corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
+            corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};

                        after_hysteresis_prev_prev <= after_hysteresis;
         end
         else
         begin
                        after_hysteresis_prev_prev <= after_hysteresis;
         end
         else
         begin

-            // 8 most significant bits of tag signal
-            corr_i_out <= corr_i_accum[13:6];
-            corr_q_out <= corr_q_accum[13:6];
+            // 8 bits of tag signal
+            corr_i_out <= corr_i_accum[11:4];
+            corr_q_out <= corr_q_accum[11:4];

         end
 
         corr_i_accum <= adc_d;
         end
 
         corr_i_accum <= adc_d;

diff --git a/fpga/hi_read_tx.v b/fpga/hi_read_tx.v
index f12e64eb65c2f8fea1adf6eba8dd211a8ff33a61..fc309cde6cedb60fd86f12a72aaeb44110f832e2 100644 (file)
--- a/fpga/hi_read_tx.v
+++ b/fpga/hi_read_tx.v
@@ -24,33 +24,36 @@ module hi_read_tx(
     output dbg;
     input shallow_modulation;
 
     output dbg;
     input shallow_modulation;
 

+// low frequency outputs, not relevant
+assign pwr_lo = 1'b0;
+assign pwr_oe2 = 1'b0;
+       

 // The high-frequency stuff. For now, for testing, just bring out the carrier,
 // and allow the ARM to modulate it over the SSP.
 reg pwr_hi;
 reg pwr_oe1;
 // The high-frequency stuff. For now, for testing, just bring out the carrier,
 // and allow the ARM to modulate it over the SSP.
 reg pwr_hi;
 reg pwr_oe1;

-reg pwr_oe2;

 reg pwr_oe3;
 reg pwr_oe4;
 reg pwr_oe3;
 reg pwr_oe4;

+

 always @(ck_1356megb or ssp_dout or shallow_modulation)
 begin
     if(shallow_modulation)
     begin
         pwr_hi <= ck_1356megb;
 always @(ck_1356megb or ssp_dout or shallow_modulation)
 begin
     if(shallow_modulation)
     begin
         pwr_hi <= ck_1356megb;

-        pwr_oe1 <= ~ssp_dout;
-        pwr_oe2 <= ~ssp_dout;
-        pwr_oe3 <= ~ssp_dout;
-        pwr_oe4 <= 1'b0;
+        pwr_oe1 <= 1'b0;
+        pwr_oe3 <= 1'b0;
+        pwr_oe4 <= ~ssp_dout;

     end
     else
     begin
         pwr_hi <= ck_1356megb & ssp_dout;
         pwr_oe1 <= 1'b0;
     end
     else
     begin
         pwr_hi <= ck_1356megb & ssp_dout;
         pwr_oe1 <= 1'b0;

-        pwr_oe2 <= 1'b0;

         pwr_oe3 <= 1'b0;
         pwr_oe4 <= 1'b0;
     end
 end
 
         pwr_oe3 <= 1'b0;
         pwr_oe4 <= 1'b0;
     end
 end
 

+

 // Then just divide the 13.56 MHz clock down to produce appropriate clocks
 // for the synchronous serial port.
 
 // Then just divide the 13.56 MHz clock down to produce appropriate clocks
 // for the synchronous serial port.
 


@@ -83,7 +86,6 @@ end
 
 assign ssp_din = after_hysteresis;
 
 
 assign ssp_din = after_hysteresis;
 

-assign pwr_lo = 1'b0;

 assign dbg = ssp_din;
 
 endmodule
 assign dbg = ssp_din;
 
 endmodule