| 95764a11 |
1 | --+-------------------------------------------------------------------------------------------------+\r |
| 2 | --| |\r |
| 3 | --| File: pcipargen.vhd |\r |
| 4 | --| |\r |
| 5 | --| Project: pci32tlite_oc |\r |
| 6 | --| |\r |
| 7 | --| Description: PCI Parity Generator. |\r |
| 8 | --| PCI Target generates PAR in the data phase of a read cycle. The 1's sum on AD, |\r |
| 9 | --| CBE and PAR is even. |\r |
| 10 | --| |\r |
| 11 | --+-------------------------------------------------------------------------------------------------+\r |
| 12 | --| |\r |
| 13 | --| Revision history : |\r |
| 14 | --| Date Version Author Description |\r |
| 15 | --| 2005-05-13 R00A00 PAU First alfa revision (eng) |\r |
| 16 | --| |\r |
| 17 | --| To do: |\r |
| 18 | --| |\r |
| 19 | --+-------------------------------------------------------------------------------------------------+\r |
| 20 | --+-----------------------------------------------------------------+\r |
| 21 | --| |\r |
| 22 | --| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | \r |
| 23 | --| |\r |
| 24 | --| This source file may be used and distributed without |\r |
| 25 | --| restriction provided that this copyright statement is not |\r |
| 26 | --| removed from the file and that any derivative work contains |\r |
| 27 | --| the original copyright notice and the associated disclaimer. |\r |
| 28 | --| |\r |
| 29 | --| This source file is free software; you can redistribute it |\r |
| 30 | --| and/or modify it under the terms of the GNU Lesser General |\r |
| 31 | --| Public License as published by the Free Software Foundation; |\r |
| 32 | --| either version 2.1 of the License, or (at your option) any |\r |
| 33 | --| later version. |\r |
| 34 | --| |\r |
| 35 | --| This source is distributed in the hope that it will be |\r |
| 36 | --| useful, but WITHOUT ANY WARRANTY; without even the implied |\r |
| 37 | --| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |\r |
| 38 | --| PURPOSE. See the GNU Lesser General Public License for more |\r |
| 39 | --| details. |\r |
| 40 | --| |\r |
| 41 | --| You should have received a copy of the GNU Lesser General |\r |
| 42 | --| Public License along with this source; if not, download it |\r |
| 43 | --| from http://www.opencores.org/lgpl.shtml |\r |
| 44 | --| |\r |
| 45 | --+-----------------------------------------------------------------+ \r |
| 46 | \r |
| 47 | \r |
| 48 | --+-----------------------------------------------------------------------------+\r |
| 49 | --| LIBRARIES |\r |
| 50 | --+-----------------------------------------------------------------------------+\r |
| 51 | \r |
| 52 | library ieee;\r |
| 53 | use ieee.std_logic_1164.all;\r |
| 54 | \r |
| 55 | \r |
| 56 | \r |
| 57 | --+-----------------------------------------------------------------------------+\r |
| 58 | --| ENTITY |\r |
| 59 | --+-----------------------------------------------------------------------------+\r |
| 60 | \r |
| 61 | entity pcipargen is\r |
| 62 | port (\r |
| 63 | \r |
| 64 | clk_i : in std_logic;\r |
| 65 | pcidatout_i : in std_logic_vector(31 downto 0);\r |
| 66 | cbe_i : in std_logic_vector(3 downto 0);\r |
| 67 | parOE_i : in std_logic;\r |
| 68 | par_o : out std_logic\r |
| 69 | \r |
| 70 | ); \r |
| 71 | end pcipargen;\r |
| 72 | \r |
| 73 | \r |
| 74 | architecture rtl of pcipargen is\r |
| 75 | \r |
| 76 | \r |
| 77 | --+-----------------------------------------------------------------------------+\r |
| 78 | --| COMPONENTS |\r |
| 79 | --+-----------------------------------------------------------------------------+\r |
| 80 | --+-----------------------------------------------------------------------------+\r |
| 81 | --| CONSTANTS |\r |
| 82 | --+-----------------------------------------------------------------------------+\r |
| 83 | --+-----------------------------------------------------------------------------+\r |
| 84 | --| SIGNALS |\r |
| 85 | --+-----------------------------------------------------------------------------+\r |
| 86 | \r |
| 87 | signal d : std_logic_vector(31 downto 0);\r |
| 88 | signal pardat : std_logic;\r |
| 89 | signal parcbe : std_logic;\r |
| 90 | signal par : std_logic;\r |
| 91 | signal par_s : std_logic;\r |
| 92 | \r |
| 93 | component sync\r |
| 94 | port (\r |
| 95 | clk : in std_logic;\r |
| 96 | d : in std_logic;\r |
| 97 | q : out std_logic\r |
| 98 | );\r |
| 99 | end component;\r |
| 100 | \r |
| 101 | component sync2\r |
| 102 | port (\r |
| 103 | clk : in std_logic;\r |
| 104 | d : in std_logic;\r |
| 105 | q : out std_logic\r |
| 106 | );\r |
| 107 | end component;\r |
| 108 | \r |
| 109 | begin\r |
| 110 | \r |
| 111 | \r |
| 112 | d <= pcidatout_i;\r |
| 113 | \r |
| 114 | \r |
| 115 | --+-------------------------------------------------------------------------+\r |
| 116 | --| building parity |\r |
| 117 | --+-------------------------------------------------------------------------+\r |
| 118 | \r |
| 119 | pardat <= d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor \r |
| 120 | d(8) xor d(9) xor d(10) xor d(11) xor d(12) xor d(13) xor d(14) xor d(15) xor \r |
| 121 | d(16) xor d(17) xor d(18) xor d(19) xor d(20) xor d(21) xor d(22) xor d(23) xor \r |
| 122 | d(24) xor d(25) xor d(26) xor d(27) xor d(28) xor d(29) xor d(30) xor d(31);\r |
| 123 | \r |
| 124 | parcbe <= cbe_i(0) xor cbe_i(1) xor cbe_i(2) xor cbe_i(3); \r |
| 125 | \r |
| 126 | par <= pardat xor parcbe;\r |
| 127 | \r |
| 128 | -- u1: sync port map ( clk => clk_i, d => par, q => par_s );\r |
| 129 | \r |
| 130 | u1: sync2 port map (\r |
| 131 | clk => clk_i,\r |
| 132 | d => par,\r |
| 133 | q => par_s\r |
| 134 | );\r |
| 135 | \r |
| 136 | \r |
| 137 | --+-------------------------------------------------------------------------+\r |
| 138 | --| PAR |\r |
| 139 | --+-------------------------------------------------------------------------+\r |
| 140 | \r |
| 141 | par_o <= par_s when ( parOE_i = '1' ) else 'Z';\r |
| 142 | \r |
| 143 | \r |
| 144 | end rtl;\r |
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