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Commit | Line | Data |
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696ded12 | 1 | -- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007 |
2 | ||
696ded12 | 3 | LIBRARY ieee; |
4 | ||
5 | USE ieee.std_logic_1164.ALL; | |
6 | USE ieee.numeric_std.ALL; | |
7 | ||
8 | ||
9 | entity CONFIG_SPACE_HEADER is | |
2612d712 | 10 | Port ( AD_REG : In std_logic_vector (31 downto 0); |
11 | ADDR_REG : In std_logic_vector (31 downto 0); | |
12 | CBE_REGn : In std_logic_vector (3 downto 0); | |
13 | CF_RD_COM : In std_logic; | |
14 | CF_WR_COM : In std_logic; | |
15 | IRDY_REGn : In std_logic; | |
16 | PCI_CLOCK : In std_logic; | |
17 | PCI_RSTn : In std_logic; | |
18 | PERR : In std_logic; | |
19 | REVISION_ID : In std_logic_vector (7 downto 0); | |
20 | SERR : In std_logic; | |
21 | TRDYn : In std_logic; | |
22 | VENDOR_ID : In std_logic_vector (15 downto 0); | |
23 | CONF_DATA : Out std_logic_vector (31 downto 0); | |
24 | CONF_DATA_04H : Out std_logic_vector (31 downto 0); | |
25 | CONF_DATA_10H : Out std_logic_vector (31 downto 0) ); | |
696ded12 | 26 | end CONFIG_SPACE_HEADER; |
27 | ||
28 | architecture SCHEMATIC of CONFIG_SPACE_HEADER is | |
29 | ||
ffdaba18 | 30 | constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE"; |
e90b12fe | 31 | --other comm. device |
32 | constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000"; | |
ffdaba18 | 33 | |
6d5ab91b | 34 | signal CONF_MAX_LAT :std_logic_vector (31 downto 24); |
35 | signal CONF_MIN_GNT :std_logic_vector (23 downto 16); | |
36 | signal CONF_INT_PIN :std_logic_vector (15 downto 8); | |
37 | signal CONF_INT_LINE :std_logic_vector ( 7 downto 0); | |
38 | ||
2612d712 | 39 | SIGNAL gnd : std_logic := '0'; |
40 | SIGNAL vcc : std_logic := '1'; | |
41 | ||
42 | signal CONF_WR_04H : std_logic; | |
43 | signal CONF_WR_10H : std_logic; | |
44 | signal CONF_WR_3CH : std_logic; | |
45 | signal CONF_READ_SEL : std_logic_vector (2 downto 0); | |
46 | signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0); | |
47 | signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0); | |
48 | signal CONF_DATA_3CH : std_logic_vector (31 downto 0); | |
49 | signal CONF_DATA_08H : std_logic_vector (31 downto 0); | |
50 | signal CONF_DATA_00H : std_logic_vector (31 downto 0); | |
51 | ||
52 | component CONFIG_MUX_0 | |
53 | Port ( CONF_DATA_00H : In std_logic_vector (31 downto 0); | |
54 | CONF_DATA_04H : In std_logic_vector (31 downto 0); | |
55 | CONF_DATA_08H : In std_logic_vector (31 downto 0); | |
56 | CONF_DATA_10H : In std_logic_vector (31 downto 0); | |
57 | CONF_DATA_3CH : In std_logic_vector (31 downto 0); | |
58 | READ_SEL : In std_logic_vector (2 downto 0); | |
59 | CONF_DATA : Out std_logic_vector (31 downto 0) ); | |
60 | end component; | |
61 | ||
62 | component CONFIG_RD_0 | |
63 | Port ( ADDR_REG : In std_logic_vector (31 downto 0); | |
64 | CF_RD_COM : In std_logic; | |
65 | READ_SEL : Out std_logic_vector (2 downto 0) ); | |
66 | end component; | |
67 | ||
68 | component CONFIG_WR_0 | |
69 | Port ( ADDR_REG : In std_logic_vector (31 downto 0); | |
70 | CF_WR_COM : In std_logic; | |
71 | IRDY_REGn : In std_logic; | |
72 | TRDYn : In std_logic; | |
73 | CONF_WR_04H : Out std_logic; | |
74 | CONF_WR_10H : Out std_logic; | |
75 | CONF_WR_3CH : Out std_logic ); | |
76 | end component; | |
77 | ||
2612d712 | 78 | component CONFIG_10H |
79 | Port ( AD_REG : In std_logic_vector (31 downto 0); | |
80 | CBE_REGn : In std_logic_vector (3 downto 0); | |
81 | CONF_WR_10H : In std_logic; | |
82 | PCI_CLOCK : In std_logic; | |
83 | PCI_RSTn : In std_logic; | |
84 | CONF_DATA_10H : Out std_logic_vector (31 downto 0) ); | |
85 | end component; | |
86 | ||
2612d712 | 87 | component CONFIG_04H |
88 | Port ( AD_REG : In std_logic_vector (31 downto 0); | |
89 | CBE_REGn : In std_logic_vector (3 downto 0); | |
90 | CONF_WR_04H : In std_logic; | |
91 | PCI_CLOCK : In std_logic; | |
92 | PCI_RSTn : In std_logic; | |
93 | PERR : In std_logic; | |
94 | SERR : In std_logic; | |
95 | CONF_DATA_04H : Out std_logic_vector (31 downto 0) ); | |
96 | end component; | |
696ded12 | 97 | |
98 | begin | |
ffdaba18 | 99 | CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID; |
e90b12fe | 100 | CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID; |
696ded12 | 101 | |
2612d712 | 102 | CONF_DATA_04H <= CONF_DATA_04H_DUMMY; |
103 | CONF_DATA_10H <= CONF_DATA_10H_DUMMY; | |
104 | ||
6d5ab91b | 105 | CONF_MAX_LAT <= X"00"; |
106 | CONF_MIN_GNT <= X"00"; | |
107 | -- CONF_INT_PIN <= X"00"; -- Interrupt - | |
108 | CONF_INT_PIN <= X"01"; -- Interrupt A | |
109 | -- CONF_INT_PIN <= X"02"; -- Interrupt B | |
110 | -- CONF_INT_PIN <= X"03"; -- Interrupt C | |
111 | -- CONF_INT_PIN <= X"04"; -- Interrupt D | |
112 | -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert | |
113 | CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE; | |
114 | ||
2612d712 | 115 | I10 : CONFIG_MUX_0 |
116 | Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0), | |
117 | CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0), | |
118 | CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0), | |
119 | CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0), | |
120 | CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0), | |
121 | READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0), | |
122 | CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) ); | |
123 | I9 : CONFIG_RD_0 | |
124 | Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0), | |
125 | CF_RD_COM=>CF_RD_COM, | |
126 | READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) ); | |
127 | I8 : CONFIG_WR_0 | |
128 | Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0), | |
129 | CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn, | |
130 | TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H, | |
131 | CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH ); | |
2612d712 | 132 | I5 : CONFIG_10H |
133 | Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0), | |
134 | CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0), | |
135 | CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK, | |
136 | PCI_RSTn=>PCI_RSTn, | |
137 | CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) ); | |
2612d712 | 138 | I2 : CONFIG_04H |
139 | Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0), | |
140 | CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0), | |
141 | CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK, | |
142 | PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR, | |
143 | CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) ); | |
696ded12 | 144 | |
6d5ab91b | 145 | process (PCI_CLOCK,PCI_RSTn) |
146 | begin | |
147 | if PCI_RSTn = '0' then | |
148 | CONF_INT_LINE <= (others => '0'); | |
149 | ||
150 | elsif (rising_edge(PCI_CLOCK)) then | |
151 | if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then | |
152 | CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0); | |
153 | end if; | |
154 | end if; | |
155 | end process; | |
696ded12 | 156 | end SCHEMATIC; |