etnerprise level consolidation

diff --git a/dhwk/dhwk.prj b/dhwk/dhwk.prj
index 90b711408a6af66ef1cc4ac157c98790b1321daf..30cbe67a0e57e9fdabbe403880cfd7d3227141a5 100644 (file)
--- a/dhwk/dhwk.prj
+++ b/dhwk/dhwk.prj
@@ -5,7 +5,6 @@ vhdl work "source/pci/comm_dec.vhd"
 vhdl work "source/pci/comm_fsm.vhd"
 vhdl work "source/pci/config_04h.vhd"
 vhdl work "source/pci/config_10h.vhd"
-vhdl work "source/pci/config_3Ch.vhd"
 vhdl work "source/pci/config_mux_0.vhd"
 vhdl work "source/pci/config_rd_0.vhd"
 vhdl work "source/pci/config_space_header.vhd"

diff --git a/dhwk/source/pci/config_3Ch.vhd b/dhwk/source/pci/config_3Ch.vhd
deleted file mode 100644 (file)
index 00d93eb..0000000
--- a/dhwk/source/pci/config_3Ch.vhd
+++ /dev/null
@@ -1,59 +0,0 @@
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: CONFIG_3CH.VHD
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity CONFIG_3CH is
-        port (
-                     PCI_CLOCK :in std_logic;
-                     PCI_RSTn :in std_logic;
-                     AD_REG :in std_logic_vector (31 downto 0);
-                     CBE_REGn :in std_logic_vector ( 3 downto 0);
-                     CONF_WR_3CH :in std_logic;
-                     CONF_DATA_3CH :out std_logic_vector (31 downto 0)
-             );
-end entity CONFIG_3CH;
-
-architecture CONFIG_3CH_DESIGN of CONFIG_3CH is
-
- -- PCI Configuration Space Header Addr : HEX 3C --
-
-        signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
-        signal CONF_MIN_GNT :std_logic_vector (23 downto 16);
-        signal CONF_INT_PIN :std_logic_vector (15 downto 8);
-        signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);
-
-        constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011";
-begin
-
- --*******************************************************************
- --*********** PCI Configuration Space Header "INTERRUPT" ************
- --*******************************************************************
-
-        CONF_MAX_LAT <= X"00";
-        CONF_MIN_GNT <= X"00";
-        -- CONF_INT_PIN <= X"00"; -- Interrupt -
-        CONF_INT_PIN <= X"01"; -- Interrupt A
-        -- CONF_INT_PIN <= X"02"; -- Interrupt B
-        -- CONF_INT_PIN <= X"03"; -- Interrupt C
-        -- CONF_INT_PIN <= X"04"; -- Interrupt D
-        -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert
-
-        process (PCI_CLOCK,PCI_RSTn)
-        begin
-                if PCI_RSTn = '0' then
-                        CONF_INT_LINE <= (others => '0');
-
-                elsif (rising_edge(PCI_CLOCK)) then
-                        if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
-                                CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
-                        end if;
-                end if;
-        end process;
-
-        CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
-
-end architecture CONFIG_3CH_DESIGN;

diff --git a/dhwk/source/pci/config_space_header.vhd b/dhwk/source/pci/config_space_header.vhd
index 0cd142012c487f435c33ffd6184bb9c648aee0f1..9114785f5c75f6df64246c4686a27ea38e987717 100644 (file)
--- a/dhwk/source/pci/config_space_header.vhd
+++ b/dhwk/source/pci/config_space_header.vhd
@@ -31,6 +31,11 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
         --other comm. device
         constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000";
 
+        signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
+        signal CONF_MIN_GNT :std_logic_vector (23 downto 16);
+        signal CONF_INT_PIN :std_logic_vector (15 downto 8);
+        signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);
+
         SIGNAL gnd : std_logic := '0';
         SIGNAL vcc : std_logic := '1';
 
@@ -70,15 +75,6 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
                        CONF_WR_3CH : Out std_logic );
         end component;
 
-        component CONFIG_3CH
-                Port ( AD_REG : In std_logic_vector (31 downto 0);
-                       CBE_REGn : In std_logic_vector (3 downto 0);
-                       CONF_WR_3CH : In std_logic;
-                       PCI_CLOCK : In std_logic;
-                       PCI_RSTn : In std_logic;
-                       CONF_DATA_3CH : Out std_logic_vector (31 downto 0) );
-        end component;
-
         component CONFIG_10H
                 Port ( AD_REG : In std_logic_vector (31 downto 0);
                        CBE_REGn : In std_logic_vector (3 downto 0);
@@ -106,6 +102,16 @@ begin
         CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
         CONF_DATA_10H <= CONF_DATA_10H_DUMMY;
 
+        CONF_MAX_LAT <= X"00";
+        CONF_MIN_GNT <= X"00";
+        -- CONF_INT_PIN <= X"00"; -- Interrupt -
+        CONF_INT_PIN <= X"01"; -- Interrupt A
+        -- CONF_INT_PIN <= X"02"; -- Interrupt B
+        -- CONF_INT_PIN <= X"03"; -- Interrupt C
+        -- CONF_INT_PIN <= X"04"; -- Interrupt D
+        -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert
+        CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
+
         I10 : CONFIG_MUX_0
         Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),
         CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),
@@ -123,12 +129,6 @@ begin
                    CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
                    TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
                    CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
-        I6 : CONFIG_3CH
-        Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
-        CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
-        CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,
-        PCI_RSTn=>PCI_RSTn,
-        CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );
         I5 : CONFIG_10H
         Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
         CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
@@ -142,4 +142,15 @@ begin
         PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,
         CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );
 
+        process (PCI_CLOCK,PCI_RSTn)
+        begin
+                if PCI_RSTn = '0' then
+                        CONF_INT_LINE <= (others => '0');
+
+                elsif (rising_edge(PCI_CLOCK)) then
+                        if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
+                                CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
+                        end if;
+                end if;
+        end process;
 end SCHEMATIC;