[raggedstone] / dhwk_old / source / generic_fifo_sc_a.v

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Universal FIFO Single Clock                                ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  D/L from: http://www.opencores.org/cores/generic_fifos/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

//  CVS Log
//
//  $Id: generic_fifo_sc_a.v,v 1.1 2007-02-11 21:58:30 sithglan Exp $
//
//  $Date: 2007-02-11 21:58:30 $
//  $Revision: 1.1 $
//  $Author: sithglan $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: generic_fifo_sc_a.v,v $
//               Revision 1.1  2007-02-11 21:58:30  sithglan
//               += fifo
//
//               Revision 1.1.1.1  2002/09/25 05:42:06  rudi
//               Initial Checkin
//
//
//
//
//
//
//
//
//
//
//

`include "timescale.v"

/*

Description
===========

I/Os
----
rst	low active, either sync. or async. master reset (see below how to select)
clr	synchronous clear (just like reset but always synchronous), high active
re	read enable, synchronous, high active
we	read enable, synchronous, high active
din	Data Input
dout	Data Output

full	Indicates the FIFO is full (combinatorial output)
full_r	same as above, but registered output (see note below)
empty	Indicates the FIFO is empty
empty_r	same as above, but registered output (see note below)

full_n		Indicates if the FIFO has space for N entries (combinatorial output)
full_n_r	same as above, but registered output (see note below)
empty_n		Indicates the FIFO has at least N entries (combinatorial output)
empty_n_r	same as above, but registered output (see note below)

level		indicates the FIFO level:
		2'b00	0-25%	 full
		2'b01	25-50%	 full
		2'b10	50-75%	 full
		2'b11	%75-100% full

combinatorial vs. registered status outputs
-------------------------------------------
Both the combinatorial and registered status outputs have exactly the same
synchronous timing. Meaning they are being asserted immediately at the clock
edge after the last read or write. The combinatorial outputs however, pass
through several levels of logic before they are output. The registered status
outputs are direct outputs of a flip-flop. The reason both are provided, is
that the registered outputs require quite a bit of additional logic inside
the FIFO. If you can meet timing of your device with the combinatorial
outputs, use them ! The FIFO will be smaller. If the status signals are
in the critical pass, use the registered outputs, they have a much smaller
output delay (actually only Tcq).

Parameters
----------
The FIFO takes 3 parameters:
dw	Data bus width
aw	Address bus width (Determines the FIFO size by evaluating 2^aw)
n	N is a second status threshold constant for full_n and empty_n
	If you have no need for the second status threshold, do not
	connect the outputs and the logic should be removed by your
	synthesis tool.

Synthesis Results
-----------------
In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs
at about 116 MHz (IO insertion disabled). The registered status outputs
are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be
available.


Misc
----
This design assumes you will do appropriate status checking externally.

IMPORTANT ! writing while the FIFO is full or reading while the FIFO is
empty will place the FIFO in an undefined state.

*/


// Selecting Sync. or Async Reset
// ------------------------------
// Uncomment one of the two lines below. The first line for
// synchronous reset, the second for asynchronous reset

`define SC_FIFO_ASYNC_RESET				// Uncomment for Syncr. reset
//`define SC_FIFO_ASYNC_RESET	or negedge rst		// Uncomment for Async. reset


module generic_fifo_sc_a(clk, rst, clr, din, we, dout, re,
			full, empty, full_r, empty_r,
			full_n, empty_n, full_n_r, empty_n_r,
			level);

parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;

input			clk, rst, clr;
input	[dw-1:0]	din;
input			we;
output	[dw-1:0]	dout;
input			re;
output			full, full_r;
output			empty, empty_r;
output			full_n, full_n_r;
output			empty_n, empty_n_r;
output	[1:0]		level;

////////////////////////////////////////////////////////////////////
//
// Local Wires
//

reg	[aw-1:0]	wp;
wire	[aw-1:0]	wp_pl1;
wire	[aw-1:0]	wp_pl2;
reg	[aw-1:0]	rp;
wire	[aw-1:0]	rp_pl1;
reg			full_r;
reg			empty_r;
reg			gb;
reg			gb2;
reg	[aw:0]		cnt;
wire			full_n, empty_n;
reg			full_n_r, empty_n_r;

////////////////////////////////////////////////////////////////////
//
// Memory Block
//

generic_dpram  #(aw,dw) u0(
	.rclk(		clk		),
	.rrst(		!rst		),
	.rce(		1'b1		),
	.oe(		1'b1		),
	.raddr(		rp		),
	.do(		dout		),
	.wclk(		clk		),
	.wrst(		!rst		),
	.wce(		1'b1		),
	.we(		we		),
	.waddr(		wp		),
	.di(		din		)
	);

////////////////////////////////////////////////////////////////////
//
// Misc Logic
//

always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)	wp <= #1 {aw{1'b0}};
	else
	if(clr)		wp <= #1 {aw{1'b0}};
	else
	if(we)		wp <= #1 wp_pl1;

assign wp_pl1 = wp + { {aw-1{1'b0}}, 1'b1};
assign wp_pl2 = wp + { {aw-2{1'b0}}, 2'b10};

always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)	rp <= #1 {aw{1'b0}};
	else
	if(clr)		rp <= #1 {aw{1'b0}};
	else
	if(re)		rp <= #1 rp_pl1;

assign rp_pl1 = rp + { {aw-1{1'b0}}, 1'b1};

////////////////////////////////////////////////////////////////////
//
// Combinatorial Full & Empty Flags
//

assign empty = ((wp == rp) & !gb);
assign full  = ((wp == rp) &  gb);

// Guard Bit ...
always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)			gb <= #1 1'b0;
	else
	if(clr)				gb <= #1 1'b0;
	else
	if((wp_pl1 == rp) & we)		gb <= #1 1'b1;
	else
	if(re)				gb <= #1 1'b0;

////////////////////////////////////////////////////////////////////
//
// Registered Full & Empty Flags
//

// Guard Bit ...
always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)			gb2 <= #1 1'b0;
	else
	if(clr)				gb2 <= #1 1'b0;
	else
	if((wp_pl2 == rp) & we)		gb2 <= #1 1'b1;
	else
	if((wp != rp) & re)		gb2 <= #1 1'b0;

always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)				full_r <= #1 1'b0;
	else
	if(clr)					full_r <= #1 1'b0;
	else
	if(we & ((wp_pl1 == rp) & gb2) & !re)	full_r <= #1 1'b1;
	else
	if(re & ((wp_pl1 != rp) | !gb2) & !we)	full_r <= #1 1'b0;

always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)				empty_r <= #1 1'b1;
	else
	if(clr)					empty_r <= #1 1'b1;
	else
	if(we & ((wp != rp_pl1) | gb2) & !re)	empty_r <= #1 1'b0;
	else
	if(re & ((wp == rp_pl1) & !gb2) & !we)	empty_r <= #1 1'b1;

////////////////////////////////////////////////////////////////////
//
// Combinatorial Full_n & Empty_n Flags
//

assign empty_n = cnt < n;
assign full_n  = !(cnt < (max_size-n+1));
assign level = {2{cnt[aw]}} | cnt[aw-1:aw-2];

// N entries status
always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)	cnt <= #1 {aw+1{1'b0}};
	else
	if(clr)		cnt <= #1 {aw+1{1'b0}};
	else
	if( re & !we)	cnt <= #1 cnt + { {aw{1'b1}}, 1'b1};
	else
	if(!re &  we)	cnt <= #1 cnt + { {aw{1'b0}}, 1'b1};

////////////////////////////////////////////////////////////////////
//
// Registered Full_n & Empty_n Flags
//

always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)				empty_n_r <= #1 1'b1;
	else
	if(clr)					empty_n_r <= #1 1'b1;
	else
	if(we & (cnt >= (n-1) ) & !re)		empty_n_r <= #1 1'b0;
	else
	if(re & (cnt <= n ) & !we)		empty_n_r <= #1 1'b1;

always @(posedge clk `SC_FIFO_ASYNC_RESET)
	if(!rst)				full_n_r <= #1 1'b0;
	else
	if(clr)					full_n_r <= #1 1'b0;
	else
	if(we & (cnt >= (max_size-n) ) & !re)	full_n_r <= #1 1'b1;
	else
	if(re & (cnt <= (max_size-n+1)) & !we)	full_n_r <= #1 1'b0;

////////////////////////////////////////////////////////////////////
//
// Sanity Check
//

// synopsys translate_off
always @(posedge clk)
	if(we & full)
		$display("%m WARNING: Writing while fifo is FULL (%t)",$time);

always @(posedge clk)
	if(re & empty)
		$display("%m WARNING: Reading while fifo is EMPTY (%t)",$time);
// synopsys translate_on

endmodule
Commit	Line	Data
96e85c4d	1	/////////////////////////////////////////////////////////////////////
	2	//// ////
	3	//// Universal FIFO Single Clock ////
	4	//// ////
	5	//// ////
	6	//// Author: Rudolf Usselmann ////
	7	//// rudi@asics.ws ////
	8	//// ////
	9	//// ////
	10	//// D/L from: http://www.opencores.org/cores/generic_fifos/ ////
	11	//// ////
	12	/////////////////////////////////////////////////////////////////////
	13	//// ////
	14	//// Copyright (C) 2000-2002 Rudolf Usselmann ////
	15	//// www.asics.ws ////
	16	//// rudi@asics.ws ////
	17	//// ////
	18	//// This source file may be used and distributed without ////
	19	//// restriction provided that this copyright statement is not ////
	20	//// removed from the file and that any derivative work contains ////
	21	//// the original copyright notice and the associated disclaimer.////
	22	//// ////
	23	//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
	24	//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
	25	//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
	26	//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
	27	//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
	28	//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
	29	//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
	30	//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
	31	//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
	32	//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
	33	//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
	34	//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
	35	//// POSSIBILITY OF SUCH DAMAGE. ////
	36	//// ////
	37	/////////////////////////////////////////////////////////////////////
	38
	39	// CVS Log
	40	//
	41	// $Id: generic_fifo_sc_a.v,v 1.1 2007-02-11 21:58:30 sithglan Exp $
	42	//
	43	// $Date: 2007-02-11 21:58:30 $
	44	// $Revision: 1.1 $
	45	// $Author: sithglan $
	46	// $Locker: $
	47	// $State: Exp $
	48	//
	49	// Change History:
	50	// $Log: generic_fifo_sc_a.v,v $
	51	// Revision 1.1 2007-02-11 21:58:30 sithglan
	52	// += fifo
	53	//
	54	// Revision 1.1.1.1 2002/09/25 05:42:06 rudi
	55	// Initial Checkin
	56	//
	57	//
	58	//
	59	//
	60	//
	61	//
	62	//
	63	//
	64	//
65	//
66	//
67
68	`include "timescale.v"
69
70	/*
71
72	Description
73	===========
74
75	I/Os
76	----
77	rst low active, either sync. or async. master reset (see below how to select)
78	clr synchronous clear (just like reset but always synchronous), high active
79	re read enable, synchronous, high active
80	we read enable, synchronous, high active
81	din Data Input
82	dout Data Output
83
84	full Indicates the FIFO is full (combinatorial output)
85	full_r same as above, but registered output (see note below)
86	empty Indicates the FIFO is empty
87	empty_r same as above, but registered output (see note below)
88
89	full_n Indicates if the FIFO has space for N entries (combinatorial output)
90	full_n_r same as above, but registered output (see note below)
91	empty_n Indicates the FIFO has at least N entries (combinatorial output)
92	empty_n_r same as above, but registered output (see note below)
93
94	level indicates the FIFO level:
95	2'b00 0-25% full
96	2'b01 25-50% full
97	2'b10 50-75% full
98	2'b11 %75-100% full
99
100	combinatorial vs. registered status outputs
101	-------------------------------------------
102	Both the combinatorial and registered status outputs have exactly the same
103	synchronous timing. Meaning they are being asserted immediately at the clock
104	edge after the last read or write. The combinatorial outputs however, pass
105	through several levels of logic before they are output. The registered status
106	outputs are direct outputs of a flip-flop. The reason both are provided, is
107	that the registered outputs require quite a bit of additional logic inside
108	the FIFO. If you can meet timing of your device with the combinatorial
109	outputs, use them ! The FIFO will be smaller. If the status signals are
110	in the critical pass, use the registered outputs, they have a much smaller
111	output delay (actually only Tcq).
112
113	Parameters
114	----------
115	The FIFO takes 3 parameters:
116	dw Data bus width
117	aw Address bus width (Determines the FIFO size by evaluating 2^aw)
118	n N is a second status threshold constant for full_n and empty_n
119	If you have no need for the second status threshold, do not
120	connect the outputs and the logic should be removed by your
121	synthesis tool.
122
123	Synthesis Results
124	-----------------
125	In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs
126	at about 116 MHz (IO insertion disabled). The registered status outputs
127	are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be
128	available.
129
130
131	Misc
132	----
133	This design assumes you will do appropriate status checking externally.
134
135	IMPORTANT ! writing while the FIFO is full or reading while the FIFO is
136	empty will place the FIFO in an undefined state.
137
138	*/
139
140
141	// Selecting Sync. or Async Reset
142	// ------------------------------
143	// Uncomment one of the two lines below. The first line for
144	// synchronous reset, the second for asynchronous reset
145
146	`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset
147	//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset
148
149
150	module generic_fifo_sc_a(clk, rst, clr, din, we, dout, re,
151	full, empty, full_r, empty_r,
152	full_n, empty_n, full_n_r, empty_n_r,
153	level);
154
155	parameter dw=8;
156	parameter aw=8;
157	parameter n=32;
158	parameter max_size = 1<<aw;
159
160	input clk, rst, clr;
161	input [dw-1:0] din;
162	input we;
163	output [dw-1:0] dout;
164	input re;
165	output full, full_r;
166	output empty, empty_r;
167	output full_n, full_n_r;
168	output empty_n, empty_n_r;
169	output [1:0] level;
170
171	////////////////////////////////////////////////////////////////////
172	//
173	// Local Wires
174	//
175
176	reg [aw-1:0] wp;
177	wire [aw-1:0] wp_pl1;
178	wire [aw-1:0] wp_pl2;
179	reg [aw-1:0] rp;
180	wire [aw-1:0] rp_pl1;
181	reg full_r;
182	reg empty_r;
183	reg gb;
184	reg gb2;
185	reg [aw:0] cnt;
186	wire full_n, empty_n;
187	reg full_n_r, empty_n_r;
188
189	////////////////////////////////////////////////////////////////////
190	//
191	// Memory Block
192	//
193
194	generic_dpram #(aw,dw) u0(
195	.rclk( clk ),
196	.rrst( !rst ),
197	.rce( 1'b1 ),
198	.oe( 1'b1 ),
199	.raddr( rp ),
200	.do( dout ),
201	.wclk( clk ),
202	.wrst( !rst ),
203	.wce( 1'b1 ),
204	.we( we ),
205	.waddr( wp ),
206	.di( din )
207	);
208
209	////////////////////////////////////////////////////////////////////
210	//
211	// Misc Logic
212	//
213
214	always @(posedge clk `SC_FIFO_ASYNC_RESET)
215	if(!rst) wp <= #1 {aw{1'b0}};
216	else
217	if(clr) wp <= #1 {aw{1'b0}};
218	else
219	if(we) wp <= #1 wp_pl1;
220
221	assign wp_pl1 = wp + { {aw-1{1'b0}}, 1'b1};
222	assign wp_pl2 = wp + { {aw-2{1'b0}}, 2'b10};
223
224	always @(posedge clk `SC_FIFO_ASYNC_RESET)
225	if(!rst) rp <= #1 {aw{1'b0}};
226	else
227	if(clr) rp <= #1 {aw{1'b0}};
228	else
229	if(re) rp <= #1 rp_pl1;
230
231	assign rp_pl1 = rp + { {aw-1{1'b0}}, 1'b1};
232
233	////////////////////////////////////////////////////////////////////
234	//
235	// Combinatorial Full & Empty Flags
236	//
237
238	assign empty = ((wp == rp) & !gb);
239	assign full = ((wp == rp) & gb);
240
241	// Guard Bit ...
242	always @(posedge clk `SC_FIFO_ASYNC_RESET)
243	if(!rst) gb <= #1 1'b0;
244	else
245	if(clr) gb <= #1 1'b0;
246	else
247	if((wp_pl1 == rp) & we) gb <= #1 1'b1;
248	else
249	if(re) gb <= #1 1'b0;
250
251	////////////////////////////////////////////////////////////////////
252	//
253	// Registered Full & Empty Flags
254	//
255
256	// Guard Bit ...
257	always @(posedge clk `SC_FIFO_ASYNC_RESET)
258	if(!rst) gb2 <= #1 1'b0;
259	else
260	if(clr) gb2 <= #1 1'b0;
261	else
262	if((wp_pl2 == rp) & we) gb2 <= #1 1'b1;
263	else
264	if((wp != rp) & re) gb2 <= #1 1'b0;
265
266	always @(posedge clk `SC_FIFO_ASYNC_RESET)
267	if(!rst) full_r <= #1 1'b0;
268	else
269	if(clr) full_r <= #1 1'b0;
270	else
271	if(we & ((wp_pl1 == rp) & gb2) & !re) full_r <= #1 1'b1;
272	else
273	if(re & ((wp_pl1 != rp) \| !gb2) & !we) full_r <= #1 1'b0;
274
275	always @(posedge clk `SC_FIFO_ASYNC_RESET)
276	if(!rst) empty_r <= #1 1'b1;
277	else
278	if(clr) empty_r <= #1 1'b1;
279	else
280	if(we & ((wp != rp_pl1) \| gb2) & !re) empty_r <= #1 1'b0;
281	else
282	if(re & ((wp == rp_pl1) & !gb2) & !we) empty_r <= #1 1'b1;
283
284	////////////////////////////////////////////////////////////////////
285	//
286	// Combinatorial Full_n & Empty_n Flags
287	//
288
289	assign empty_n = cnt < n;
290	assign full_n = !(cnt < (max_size-n+1));
291	assign level = {2{cnt[aw]}} \| cnt[aw-1:aw-2];
292
293	// N entries status
294	always @(posedge clk `SC_FIFO_ASYNC_RESET)
295	if(!rst) cnt <= #1 {aw+1{1'b0}};
296	else
297	if(clr) cnt <= #1 {aw+1{1'b0}};
298	else
299	if( re & !we) cnt <= #1 cnt + { {aw{1'b1}}, 1'b1};
300	else
301	if(!re & we) cnt <= #1 cnt + { {aw{1'b0}}, 1'b1};
302
303	////////////////////////////////////////////////////////////////////
304	//
305	// Registered Full_n & Empty_n Flags
306	//
307
308	always @(posedge clk `SC_FIFO_ASYNC_RESET)
309	if(!rst) empty_n_r <= #1 1'b1;
310	else
311	if(clr) empty_n_r <= #1 1'b1;
312	else
313	if(we & (cnt >= (n-1) ) & !re) empty_n_r <= #1 1'b0;
314	else
315	if(re & (cnt <= n ) & !we) empty_n_r <= #1 1'b1;
316
317	always @(posedge clk `SC_FIFO_ASYNC_RESET)
318	if(!rst) full_n_r <= #1 1'b0;
319	else
320	if(clr) full_n_r <= #1 1'b0;
321	else
322	if(we & (cnt >= (max_size-n) ) & !re) full_n_r <= #1 1'b1;
323	else
324	if(re & (cnt <= (max_size-n+1)) & !we) full_n_r <= #1 1'b0;
325
326	////////////////////////////////////////////////////////////////////
327	//
328	// Sanity Check
329	//
330
331	// synopsys translate_off
332	always @(posedge clk)
333	if(we & full)
334	$display("%m WARNING: Writing while fifo is FULL (%t)",$time);
335
336	always @(posedge clk)
337	if(re & empty)
338	$display("%m WARNING: Reading while fifo is EMPTY (%t)",$time);
339	// synopsys translate_on
340
341	endmodule
342