// CVS Revision History
//
// $Log: generic_dpram.v,v $
-// Revision 1.2 2007-02-11 22:15:39 sithglan
+// Revision 1.3 2007-02-11 22:18:24 michael
+// component for dram
+//
+// Revision 1.2 2007/02/11 22:15:39 sithglan
// define xilinix and fpga
//
// Revision 1.1 2007/02/11 22:05:26 sithglan
//
// Default address and data buses width
//
- parameter aw = 5; // number of bits in address-bus
- parameter dw = 16; // number of bits in data-bus
+ parameter aw = 12; // number of bits in address-bus
+ parameter dw = 8; // number of bits in data-bus
//
// Generic synchronous double-port RAM interface
);\r
end component;\r
\r
+component generic_dpram\r
+port (\r
+ rclk : in std_logic;\r
+ rrst : in std_logic;\r
+ rce : in std_logic;\r
+ oe : in std_logic;\r
+ raddr : in std_logic_vector(11 downto 0);\r
+ do : out std_logic_vector(7 downto 0);\r
+ wclk : in std_logic;\r
+ wrst : in std_logic;\r
+ wce : in std_logic;\r
+ we : in std_logic;\r
+ waddr : in std_logic_vector(11 downto 0);\r
+ di : in std_logic_vector(7 downto 0);\r
+);\r
+end component;\r
+\r
\r
--+-----------------------------------------------------------------------------+\r
--| CONSTANTS |\r