[raggedstone] / dhwk / icon_core.xco

# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s1500
SET devicefamily = spartan3
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fg456
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.02.a
# END Select
# BEGIN Parameters
CSET component_name=icon
CSET number_control_ports=2
CSET use_ext_bscan=false
CSET use_jtag_bufg=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
GENERATE
Commit	Line	Data
40a64bf1 MG	1	# BEGIN Project Options
	2	SET addpads = False
	3	SET asysymbol = False
	4	SET busformat = BusFormatAngleBracketNotRipped
	5	SET createndf = False
	6	SET designentry = VHDL
	7	SET device = xc3s1500
	8	SET devicefamily = spartan3
	9	SET flowvendor = Other
	10	SET formalverification = False
	11	SET foundationsym = False
	12	SET implementationfiletype = Ngc
	13	SET package = fg456
	14	SET removerpms = False
	15	SET simulationfiles = Structural
	16	SET speedgrade = -4
	17	SET verilogsim = False
	18	SET vhdlsim = True
	19	# END Project Options
	20	# BEGIN Select
	21	SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.02.a
	22	# END Select
	23	# BEGIN Parameters
	24	CSET component_name=icon
	25	CSET number_control_ports=2
	26	CSET use_ext_bscan=false
	27	CSET use_jtag_bufg=false
	28	CSET use_unused_bscan=false
	29	CSET user_scan_chain=USER1
	30	# END Parameters
	31	GENERATE