[raggedstone] / ethernet / source / top.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;

entity ethernet is
PORT(
        PCI_AD : INOUT std_logic_vector(31 downto 0);
        PCI_CLOCK : IN std_logic;
        PCI_IDSEL : IN std_logic;
        PCI_CBEn : INOUT std_logic_vector (3 downto 0);
        PCI_FRAMEn : INOUT std_logic;
        PCI_IRDYn : INOUT std_logic;
        PCI_RSTn : INOUT std_logic;
        PCI_DEVSELn : INOUT std_logic;
        PCI_INTAn : INOUT std_logic;
        PCI_PERRn : INOUT std_logic;
        PCI_SERRn : INOUT std_logic;
        PCI_STOPn : INOUT std_logic;
        PCI_TRDYn : INOUT std_logic;
        PCI_PAR   : INOUT std_logic;
        PCI_REQn  : OUT std_logic;
        PCI_GNTn : IN std_logic;

        MTX_CLK_PAD_I : IN std_logic;
        MTXD_PAD_O : OUT std_logic_vector (3 downto 0);
        MTXEN_PAD_O : OUT std_logic;
        MRX_CLK_PAD_I : IN std_logic;
        MRXD_PAD_I : IN std_logic_vector (3 downto 0);
        MRXDV_PAD_I : IN std_logic;
        MRXERR_PAD_I : IN std_logic;
        MCOLL_PAD_I : IN std_logic;
        MCRS_PAD_I : IN std_logic;
        MD_PAD_IO : INOUT std_logic;
        MDC_PAD_O : OUT std_logic;

	PHY_CLOCK : OUT std_logic;

	LED_2 : OUT std_logic
);
end ethernet;

architecture ethernet_arch of ethernet is

COMPONENT eth_top
PORT(
        wb_clk_i : IN std_logic;
        wb_rst_i : IN std_logic;
        wb_dat_i : IN std_logic_vector(31 downto 0);
        wb_adr_i : IN std_logic_vector(11 downto 2);
        wb_sel_i : IN std_logic_vector(3 downto 0);
        wb_we_i : IN std_logic;
        wb_cyc_i : IN std_logic;
        wb_stb_i : IN std_logic;
        m_wb_dat_i : IN std_logic_vector(31 downto 0);
        m_wb_ack_i : IN std_logic;
        m_wb_err_i : IN std_logic;
        mtx_clk_pad_i : IN std_logic;
        mrx_clk_pad_i : IN std_logic;
        mrxd_pad_i : IN std_logic_vector(3 downto 0);
        mrxdv_pad_i : IN std_logic;
        mrxerr_pad_i : IN std_logic;
        mcoll_pad_i : IN std_logic;
        mcrs_pad_i : IN std_logic;
        md_pad_i : IN std_logic;          
        wb_dat_o : OUT std_logic_vector(31 downto 0);
        wb_ack_o : OUT std_logic;
        wb_err_o : OUT std_logic;
        m_wb_adr_o : OUT std_logic_vector(31 downto 0);
        m_wb_sel_o : OUT std_logic_vector(3 downto 0);
        m_wb_we_o : OUT std_logic;
        m_wb_dat_o : OUT std_logic_vector(31 downto 0);
        m_wb_cyc_o : OUT std_logic;
        m_wb_stb_o : OUT std_logic;
        mtxd_pad_o : OUT std_logic_vector(3 downto 0);
        mtxen_pad_o : OUT std_logic;
        mtxerr_pad_o : OUT std_logic;
        mdc_pad_o : OUT std_logic;
        md_pad_o : OUT std_logic;
        md_padoe_o : OUT std_logic;
        m_wb_cti_o : OUT std_logic_vector(2 downto 0);
        m_wb_bte_o : OUT std_logic_vector(1 downto 0);
        int_o : OUT std_logic
        );
END COMPONENT;

COMPONENT pci_bridge32
PORT(
        wb_clk_i : IN std_logic;
        wb_rst_i : IN std_logic;
        wb_int_i : IN std_logic;
        wbs_adr_i : IN std_logic_vector(31 downto 0);
        wbs_dat_i : IN std_logic_vector(31 downto 0);
        wbs_sel_i : IN std_logic_vector(3 downto 0);
        wbs_cyc_i : IN std_logic;
        wbs_stb_i : IN std_logic;
        wbs_we_i : IN std_logic;
        wbs_cti_i : IN std_logic_vector(2 downto 0);
        wbs_bte_i : IN std_logic_vector(1 downto 0);
        wbm_dat_i : IN std_logic_vector(31 downto 0);
        wbm_ack_i : IN std_logic;
        wbm_rty_i : IN std_logic;
        wbm_err_i : IN std_logic;
        pci_clk_i : IN std_logic;
        pci_rst_i : IN std_logic;
        pci_inta_i : IN std_logic;
        pci_gnt_i : IN std_logic;
        pci_frame_i : IN std_logic;
        pci_irdy_i : IN std_logic;
        pci_idsel_i : IN std_logic;
        pci_devsel_i : IN std_logic;
        pci_trdy_i : IN std_logic;
        pci_stop_i : IN std_logic;
        pci_ad_i : IN std_logic_vector(31 downto 0);
        pci_cbe_i : IN std_logic_vector(3 downto 0);
        pci_par_i : IN std_logic;
        pci_perr_i : IN std_logic;          
        wb_rst_o : OUT std_logic;
        wb_int_o : OUT std_logic;
        wbs_dat_o : OUT std_logic_vector(31 downto 0);
        wbs_ack_o : OUT std_logic;
        wbs_rty_o : OUT std_logic;
        wbs_err_o : OUT std_logic;
        wbm_adr_o : OUT std_logic_vector(31 downto 0);
        wbm_dat_o : OUT std_logic_vector(31 downto 0);
        wbm_sel_o : OUT std_logic_vector(3 downto 0);
        wbm_cyc_o : OUT std_logic;
        wbm_stb_o : OUT std_logic;
        wbm_we_o : OUT std_logic;
        wbm_cti_o : OUT std_logic_vector(2 downto 0);
        wbm_bte_o : OUT std_logic_vector(1 downto 0);
        pci_rst_o : OUT std_logic;
        pci_inta_o : OUT std_logic;
        pci_rst_oe_o : OUT std_logic;
        pci_inta_oe_o : OUT std_logic;
        pci_req_o : OUT std_logic;
        pci_req_oe_o : OUT std_logic;
        pci_frame_o : OUT std_logic;
        pci_frame_oe_o : OUT std_logic;
        pci_irdy_oe_o : OUT std_logic;
        pci_devsel_oe_o : OUT std_logic;
        pci_trdy_oe_o : OUT std_logic;
        pci_stop_oe_o : OUT std_logic;
        pci_ad_oe_o : OUT std_logic_vector(31 downto 0);
        pci_cbe_oe_o : OUT std_logic_vector(3 downto 0);
        pci_irdy_o : OUT std_logic;
        pci_devsel_o : OUT std_logic;
        pci_trdy_o : OUT std_logic;
        pci_stop_o : OUT std_logic;
        pci_ad_o : OUT std_logic_vector(31 downto 0);
        pci_cbe_o : OUT std_logic_vector(3 downto 0);
        pci_par_o : OUT std_logic;
        pci_par_oe_o : OUT std_logic;
        pci_perr_o : OUT std_logic;
        pci_perr_oe_o : OUT std_logic;
        pci_serr_o : OUT std_logic;
        pci_serr_oe_o : OUT std_logic
        );
END COMPONENT;

component icon
port (
	control0 : out std_logic_vector(35 downto 0)
	);
end component;

component ila
port (
	control : in std_logic_vector(35 downto 0);
	clk : in std_logic;
	data : in std_logic_vector(63 downto 0);
	trig0 : in std_logic_vector(31 downto 0)
	);
end component;

component phydcm is
port ( CLKIN_IN        : in    std_logic;
       RST_IN          : in    std_logic;
       CLKFX_OUT       : out   std_logic;
       CLK0_OUT        : out   std_logic;
       LOCKED_OUT      : out   std_logic);
end component;

signal pci_rst_i : std_logic;
signal pci_rst_o : std_logic;
signal pci_rst_oe_o : std_logic;
signal pci_inta_i : std_logic;
signal pci_inta_o : std_logic;
signal pci_inta_oe_o : std_logic;
signal pci_req_o : std_logic;
signal pci_req_oe_o : std_logic;
signal pci_frame_i : std_logic;
signal pci_frame_o : std_logic;
signal pci_frame_oe_o : std_logic;
signal pci_irdy_i : std_logic;
signal pci_irdy_o : std_logic;
signal pci_irdy_oe_o : std_logic;
signal pci_devsel_i : std_logic;
signal pci_devsel_o : std_logic;
signal pci_devsel_oe_o : std_logic;
signal pci_trdy_i : std_logic;
signal pci_trdy_o : std_logic;
signal pci_trdy_oe_o : std_logic;
signal pci_stop_i : std_logic;
signal pci_stop_o : std_logic;
signal pci_stop_oe_o : std_logic;
signal pci_par_i : std_logic;
signal pci_par_o : std_logic;
signal pci_par_oe_o : std_logic;
signal pci_perr_i : std_logic;
signal pci_perr_o : std_logic;
signal pci_perr_oe_o : std_logic;
signal pci_serr_i : std_logic;
signal pci_serr_o : std_logic;
signal pci_serr_oe_o : std_logic;
signal pci_ad_oe_o : std_logic_vector(31 downto 0);
signal pci_cbe_oe_o : std_logic_vector(3 downto 0);
signal pci_ad_i : std_logic_vector (31 downto 0);
signal pci_ad_o : std_logic_vector (31 downto 0);
signal pci_cbe_i : std_logic_vector (3 downto 0);
signal pci_cbe_o : std_logic_vector (3 downto 0);

signal wb_clk_i : std_logic;
signal wb_rst_i : std_logic;
signal wb_dat_i : std_logic_vector (31 downto 0);
signal wb_dat_o : std_logic_vector (31 downto 0);
signal wb_adr_i : std_logic_vector (11 downto 2);
signal wb_sel_i : std_logic_vector (3 downto 0);
signal wb_we_i : std_logic;
signal wb_cyc_i : std_logic;
signal wb_stb_i : std_logic;
signal wb_ack_o : std_logic;
signal wb_err_o : std_logic;
signal m_wb_adr_o : std_logic_vector(31 downto 0);
signal m_wb_sel_o : std_logic_vector(3 downto 0);
signal m_wb_we_o : std_logic;
signal m_wb_dat_o : std_logic_vector(31 downto 0);
signal m_wb_dat_i : std_logic_vector(31 downto 0);
signal m_wb_cyc_o : std_logic;
signal m_wb_stb_o : std_logic;
signal m_wb_ack_i : std_logic;
signal m_wb_err_i : std_logic;
signal md_pad_i : std_logic;
signal md_pad_o : std_logic;
signal md_padoe_o : std_logic;
signal int_o : std_logic;
signal wbm_adr_o : std_logic_vector(31 downto 0);
signal mdc_pad_o_watch : std_logic;

signal m_wb_cti_o : std_logic_vector(2 downto 0);
signal m_wb_bte_o : std_logic_vector(1 downto 0);

signal control0 : std_logic_vector(35 downto 0);
signal data : std_logic_vector(63 downto 0);
signal trig0 : std_logic_vector(31 downto 0);


BEGIN

IOBUF_PCI_RSTn: IOBUF
port map (
	IO => PCI_RSTn,
	T => pci_rst_oe_o,
	I => pci_rst_o,
	O => pci_rst_i
);
IOBUF_PCI_INTAn: IOBUF
port map (
	IO => PCI_INTAn,
	T => pci_inta_oe_o,
	I => pci_inta_o,
	O => pci_inta_i
);
OBUFT_PCI_REQn: OBUFT
port map (
	O => PCI_REQn,
	T => pci_req_oe_o,
	I => pci_req_o
);
IOBUF_PCI_FRAMEn: IOBUF
port map (
	IO => PCI_FRAMEn,
	T => pci_frame_oe_o,
	I => pci_frame_o,
	O => pci_frame_i
);
IOBUF_PCI_IRDYn: IOBUF
port map (
	IO => PCI_IRDYn,
	T => pci_irdy_oe_o,
	I => pci_irdy_o,
	O => pci_irdy_i
);
IOBUF_PCI_DEVSELn: IOBUF
port map (
	IO => PCI_DEVSELn,
	T => pci_devsel_oe_o,
	I => pci_devsel_o,
	O => pci_devsel_i
);
IOBUF_PCI_TRDYn: IOBUF
port map (
	IO => PCI_TRDYn,
	T => pci_trdy_oe_o,
	I => pci_trdy_o,
	O => pci_trdy_i
);
IOBUF_PCI_STOPn: IOBUF
port map (
	IO => PCI_STOPn,
	T => pci_stop_oe_o,
	I => pci_stop_o,
	O => pci_stop_i
);
IOBUF_PCI_PAR: IOBUF
port map (
	IO => PCI_PAR,
	T => pci_par_oe_o,
	I => pci_par_o,
	O => pci_par_i
);
IOBUF_PCI_PERRn: IOBUF
port map (
	IO => PCI_PERRn,
	T => pci_perr_oe_o,
	I => pci_perr_o,
	O => pci_perr_i
);
IOBUF_PCI_SERRn: IOBUF
port map (
	IO => PCI_SERRn,
	T => pci_serr_oe_o,
	I => pci_serr_o,
	O => pci_serr_i
);
IOBUF_MD_PAD_IO: IOBUF
port map (
	IO => MD_PAD_IO,
	T => md_padoe_o,
	I => md_pad_o,
	O => md_pad_i
);

BLA1: FOR i in 31 downto 0 generate
IOBUF_PCI_AD: IOBUF
port map (
	IO => PCI_AD(i),
	T => pci_ad_oe_o(i),
	I => pci_ad_o(i),
	O => pci_ad_i(i)
);
end generate;

BLA2: FOR i in 3 downto 0 generate
IOBUF_PCI_CBEn: IOBUF
port map (
	IO => PCI_CBEn(i),
	T => pci_cbe_oe_o(i),
	I => pci_cbe_o(i),
	O => pci_cbe_i(i)
);
end generate;

wb_adr_i(11 downto 8) <= (others => '0');
wb_adr_i(7 downto 2)  <= wbm_adr_o (7 downto 2);

wb_clk_i <= PCI_CLOCK;

data(31 downto 0)  <= wbm_adr_o;
data(39 downto 32) <= wbm_adr_o (7 downto 0);
data(40) <= md_pad_i;
data(41) <= md_pad_o;
data(42) <= md_padoe_o;
data(43) <= mdc_pad_o_watch;
data(44) <= pci_inta_o;
data(63 downto 45) <= (others => '0');

MDC_PAD_O <= mdc_pad_o_watch;

trig0(31 downto 0) <= (
	0 => wb_stb_i,
	1 => md_pad_i,
	2 => md_pad_o,
	3 => md_padoe_o,
	others => '0'
);

Inst_pci_bridge32: pci_bridge32 PORT MAP(
        wb_clk_i => wb_clk_i ,
        wb_rst_i => '0',
        wb_rst_o => wb_rst_i,
        wb_int_i => int_o,
        -- wb_int_o => ,
        wbs_adr_i => m_wb_adr_o ,
        wbs_dat_i => m_wb_dat_o,
        wbs_dat_o => m_wb_dat_i,
        wbs_sel_i => m_wb_sel_o,
        wbs_cyc_i => m_wb_cyc_o,
        wbs_stb_i => m_wb_stb_o,
        wbs_we_i => m_wb_we_o,
        wbs_cti_i => m_wb_cti_o,
        wbs_bte_i => m_wb_bte_o,
        wbs_ack_o => m_wb_ack_i,
        -- wbs_rty_o => ,
        wbs_err_o => m_wb_err_i,
        wbm_adr_o => wbm_adr_o,
        wbm_dat_i => wb_dat_o,
        wbm_dat_o => wb_dat_i,
        wbm_sel_o => wb_sel_i,
        wbm_cyc_o => wb_cyc_i,
        wbm_stb_o => wb_stb_i,
        wbm_we_o => wb_we_i,
        -- wbm_cti_o => ,
        -- wbm_bte_o => ,
        wbm_ack_i => wb_ack_o ,
        wbm_rty_i => '0',
        wbm_err_i => wb_err_o,
        pci_clk_i => PCI_CLOCK,
        pci_rst_i => pci_rst_i,
        pci_rst_o => pci_rst_o ,
        pci_rst_oe_o => pci_rst_oe_o,
        pci_inta_i => pci_inta_i,
        pci_inta_o => pci_inta_o,
        pci_inta_oe_o => pci_inta_oe_o,
        pci_req_o => pci_req_o,
        pci_req_oe_o => pci_req_oe_o,
        pci_gnt_i => PCI_GNTn,
        pci_frame_i => pci_frame_i,
        pci_frame_o => pci_frame_o,
        pci_frame_oe_o => pci_frame_oe_o,
        pci_irdy_oe_o => pci_irdy_oe_o,
        pci_devsel_oe_o => pci_devsel_oe_o,
        pci_trdy_oe_o => pci_trdy_oe_o,
        pci_stop_oe_o => pci_stop_oe_o,
        pci_ad_oe_o => pci_ad_oe_o,
        pci_cbe_oe_o => pci_cbe_oe_o,
        pci_irdy_i => pci_irdy_i,
        pci_irdy_o => pci_irdy_o,
        pci_idsel_i => PCI_IDSEL,
        pci_devsel_i => pci_devsel_i,
        pci_devsel_o => pci_devsel_o,
        pci_trdy_i => pci_trdy_i,
        pci_trdy_o => pci_trdy_o,
        pci_stop_i => pci_stop_i,
        pci_stop_o => pci_stop_o,
        pci_ad_i => pci_ad_i,
        pci_ad_o => pci_ad_o,
        pci_cbe_i => pci_cbe_i,
        pci_cbe_o => pci_cbe_o,
        pci_par_i => pci_par_i,
        pci_par_o => pci_par_o,
        pci_par_oe_o => pci_par_oe_o,
        pci_perr_i => pci_perr_i,
        pci_perr_o => pci_perr_o,
        pci_perr_oe_o => pci_perr_oe_o,
        pci_serr_o => pci_serr_o,
        pci_serr_oe_o =>  pci_serr_oe_o
);

Inst_eth_top: eth_top PORT MAP(
        wb_clk_i   => wb_clk_i  ,
        wb_rst_i   => wb_rst_i  ,
        wb_dat_i   => wb_dat_i  ,
        wb_dat_o   => wb_dat_o  ,
        wb_adr_i   => wb_adr_i  ,
        wb_sel_i   => wb_sel_i  ,
        wb_we_i    => wb_we_i   ,
        wb_cyc_i   => wb_cyc_i  ,
        wb_stb_i   => wb_stb_i,
        wb_ack_o   => wb_ack_o  ,
        wb_err_o   => wb_err_o  ,
        m_wb_adr_o => m_wb_adr_o,
        m_wb_sel_o => m_wb_sel_o,
        m_wb_we_o  => m_wb_we_o ,
        m_wb_dat_o => m_wb_dat_o,
        m_wb_dat_i => m_wb_dat_i,
        m_wb_cyc_o => m_wb_cyc_o,
        m_wb_stb_o => m_wb_stb_o,
        m_wb_ack_i => m_wb_ack_i,
        m_wb_err_i => m_wb_err_i,
        mtx_clk_pad_i => MTX_CLK_PAD_I,
        mtxd_pad_o => MTXD_PAD_O,
        mtxen_pad_o => MTXEN_PAD_O,
        mtxerr_pad_o => LED_2,
        mrx_clk_pad_i => MRX_CLK_PAD_I,
        mrxd_pad_i => MRXD_PAD_I,
        mrxdv_pad_i => MRXDV_PAD_I,
        mrxerr_pad_i => MRXERR_PAD_I,
        mcoll_pad_i => MCOLL_PAD_I,
        mcrs_pad_i => MCRS_PAD_I,
        mdc_pad_o => mdc_pad_o_watch,
        md_pad_i => md_pad_i,
        md_pad_o => md_pad_o,
        md_padoe_o => md_padoe_o,
        m_wb_cti_o => m_wb_cti_o,
        m_wb_bte_o => m_wb_bte_o, 
        int_o => int_o
);

i_icon : icon
port map (
	control0 => control0
	);

i_ila : ila
port map (
	control => control0,
	clk => PCI_CLOCK,
	data => data,
	trig0 => trig0
	);

eth_dcm : phydcm
port map (
	CLKIN_IN => PCI_CLOCK,
	RST_IN => not pci_rst_i,
	CLKFX_OUT => PHY_CLOCK,
	CLK0_OUT => open,
	LOCKED_OUT => open
	);

end architecture ethernet_arch;
Commit	Line	Data
27f6f620	1	LIBRARY ieee;
27f6f620	2	USE ieee.std_logic_1164.ALL;
b98e21a5 MG	3	Library UNISIM;
b98e21a5 MG	4	use UNISIM.vcomponents.all;
27f6f620	5
27f6f620	6	entity ethernet is
40a1f26c	7	PORT(
	8	PCI_AD : INOUT std_logic_vector(31 downto 0);
	9	PCI_CLOCK : IN std_logic;
	10	PCI_IDSEL : IN std_logic;
	11	PCI_CBEn : INOUT std_logic_vector (3 downto 0);
	12	PCI_FRAMEn : INOUT std_logic;
	13	PCI_IRDYn : INOUT std_logic;
	14	PCI_RSTn : INOUT std_logic;
	15	PCI_DEVSELn : INOUT std_logic;
	16	PCI_INTAn : INOUT std_logic;
	17	PCI_PERRn : INOUT std_logic;
	18	PCI_SERRn : INOUT std_logic;
	19	PCI_STOPn : INOUT std_logic;
	20	PCI_TRDYn : INOUT std_logic;
	21	PCI_PAR : INOUT std_logic;
	22	PCI_REQn : OUT std_logic;
	23	PCI_GNTn : IN std_logic;
	24
	25	MTX_CLK_PAD_I : IN std_logic;
	26	MTXD_PAD_O : OUT std_logic_vector (3 downto 0);
	27	MTXEN_PAD_O : OUT std_logic;
	28	MRX_CLK_PAD_I : IN std_logic;
	29	MRXD_PAD_I : IN std_logic_vector (3 downto 0);
	30	MRXDV_PAD_I : IN std_logic;
	31	MRXERR_PAD_I : IN std_logic;
	32	MCOLL_PAD_I : IN std_logic;
	33	MCRS_PAD_I : IN std_logic;
	34	MD_PAD_IO : INOUT std_logic;
4d7b5fdd	35	MDC_PAD_O : OUT std_logic;
4d7b5fdd	36
7a6a1ff7	37	PHY_CLOCK : OUT std_logic;
7a6a1ff7	38
4d7b5fdd	39	LED_2 : OUT std_logic
40a1f26c	40	);
27f6f620	41	end ethernet;
40a1f26c	42
27f6f620	43	architecture ethernet_arch of ethernet is
40a1f26c	44
	45	COMPONENT eth_top
	46	PORT(
	47	wb_clk_i : IN std_logic;
	48	wb_rst_i : IN std_logic;
	49	wb_dat_i : IN std_logic_vector(31 downto 0);
	50	wb_adr_i : IN std_logic_vector(11 downto 2);
	51	wb_sel_i : IN std_logic_vector(3 downto 0);
	52	wb_we_i : IN std_logic;
	53	wb_cyc_i : IN std_logic;
	54	wb_stb_i : IN std_logic;
	55	m_wb_dat_i : IN std_logic_vector(31 downto 0);
	56	m_wb_ack_i : IN std_logic;
	57	m_wb_err_i : IN std_logic;
	58	mtx_clk_pad_i : IN std_logic;
	59	mrx_clk_pad_i : IN std_logic;
	60	mrxd_pad_i : IN std_logic_vector(3 downto 0);
	61	mrxdv_pad_i : IN std_logic;
	62	mrxerr_pad_i : IN std_logic;
	63	mcoll_pad_i : IN std_logic;
	64	mcrs_pad_i : IN std_logic;
	65	md_pad_i : IN std_logic;
	66	wb_dat_o : OUT std_logic_vector(31 downto 0);
	67	wb_ack_o : OUT std_logic;
	68	wb_err_o : OUT std_logic;
	69	m_wb_adr_o : OUT std_logic_vector(31 downto 0);
	70	m_wb_sel_o : OUT std_logic_vector(3 downto 0);
	71	m_wb_we_o : OUT std_logic;
	72	m_wb_dat_o : OUT std_logic_vector(31 downto 0);
	73	m_wb_cyc_o : OUT std_logic;
	74	m_wb_stb_o : OUT std_logic;
	75	mtxd_pad_o : OUT std_logic_vector(3 downto 0);
	76	mtxen_pad_o : OUT std_logic;
	77	mtxerr_pad_o : OUT std_logic;
	78	mdc_pad_o : OUT std_logic;
	79	md_pad_o : OUT std_logic;
	80	md_padoe_o : OUT std_logic;
361ec26f	81	m_wb_cti_o : OUT std_logic_vector(2 downto 0);
361ec26f	82	m_wb_bte_o : OUT std_logic_vector(1 downto 0);
40a1f26c	83	int_o : OUT std_logic
	84	);
	85	END COMPONENT;
	86
	87	COMPONENT pci_bridge32
	88	PORT(
	89	wb_clk_i : IN std_logic;
	90	wb_rst_i : IN std_logic;
	91	wb_int_i : IN std_logic;
	92	wbs_adr_i : IN std_logic_vector(31 downto 0);
	93	wbs_dat_i : IN std_logic_vector(31 downto 0);
	94	wbs_sel_i : IN std_logic_vector(3 downto 0);
	95	wbs_cyc_i : IN std_logic;
	96	wbs_stb_i : IN std_logic;
	97	wbs_we_i : IN std_logic;
	98	wbs_cti_i : IN std_logic_vector(2 downto 0);
	99	wbs_bte_i : IN std_logic_vector(1 downto 0);
	100	wbm_dat_i : IN std_logic_vector(31 downto 0);
	101	wbm_ack_i : IN std_logic;
	102	wbm_rty_i : IN std_logic;
	103	wbm_err_i : IN std_logic;
	104	pci_clk_i : IN std_logic;
	105	pci_rst_i : IN std_logic;
	106	pci_inta_i : IN std_logic;
	107	pci_gnt_i : IN std_logic;
	108	pci_frame_i : IN std_logic;
	109	pci_irdy_i : IN std_logic;
	110	pci_idsel_i : IN std_logic;
	111	pci_devsel_i : IN std_logic;
	112	pci_trdy_i : IN std_logic;
	113	pci_stop_i : IN std_logic;
	114	pci_ad_i : IN std_logic_vector(31 downto 0);
	115	pci_cbe_i : IN std_logic_vector(3 downto 0);
	116	pci_par_i : IN std_logic;
	117	pci_perr_i : IN std_logic;
	118	wb_rst_o : OUT std_logic;
	119	wb_int_o : OUT std_logic;
	120	wbs_dat_o : OUT std_logic_vector(31 downto 0);
	121	wbs_ack_o : OUT std_logic;
	122	wbs_rty_o : OUT std_logic;
	123	wbs_err_o : OUT std_logic;
	124	wbm_adr_o : OUT std_logic_vector(31 downto 0);
	125	wbm_dat_o : OUT std_logic_vector(31 downto 0);
	126	wbm_sel_o : OUT std_logic_vector(3 downto 0);
	127	wbm_cyc_o : OUT std_logic;
	128	wbm_stb_o : OUT std_logic;
	129	wbm_we_o : OUT std_logic;
	130	wbm_cti_o : OUT std_logic_vector(2 downto 0);
	131	wbm_bte_o : OUT std_logic_vector(1 downto 0);
	132	pci_rst_o : OUT std_logic;
	133	pci_inta_o : OUT std_logic;
	134	pci_rst_oe_o : OUT std_logic;
	135	pci_inta_oe_o : OUT std_logic;
	136	pci_req_o : OUT std_logic;
	137	pci_req_oe_o : OUT std_logic;
	138	pci_frame_o : OUT std_logic;
	139	pci_frame_oe_o : OUT std_logic;
	140	pci_irdy_oe_o : OUT std_logic;
	141	pci_devsel_oe_o : OUT std_logic;
	142	pci_trdy_oe_o : OUT std_logic;
	143	pci_stop_oe_o : OUT std_logic;
	144	pci_ad_oe_o : OUT std_logic_vector(31 downto 0);
	145	pci_cbe_oe_o : OUT std_logic_vector(3 downto 0);
	146	pci_irdy_o : OUT std_logic;
147	pci_devsel_o : OUT std_logic;
148	pci_trdy_o : OUT std_logic;
149	pci_stop_o : OUT std_logic;
150	pci_ad_o : OUT std_logic_vector(31 downto 0);
151	pci_cbe_o : OUT std_logic_vector(3 downto 0);
152	pci_par_o : OUT std_logic;
153	pci_par_oe_o : OUT std_logic;
154	pci_perr_o : OUT std_logic;
155	pci_perr_oe_o : OUT std_logic;
156	pci_serr_o : OUT std_logic;
157	pci_serr_oe_o : OUT std_logic
158	);
159	END COMPONENT;
160
c8b3e197	161	component icon
	162	port (
	163	control0 : out std_logic_vector(35 downto 0)
70f633de	164	);
c8b3e197	165	end component;
	166
	167	component ila
	168	port (
	169	control : in std_logic_vector(35 downto 0);
	170	clk : in std_logic;
	171	data : in std_logic_vector(63 downto 0);
	172	trig0 : in std_logic_vector(31 downto 0)
	173	);
	174	end component;
70f633de	175
ac5b8271	176	component phydcm is
	177	port ( CLKIN_IN : in std_logic;
	178	RST_IN : in std_logic;
	179	CLKFX_OUT : out std_logic;
ac5b8271	180	CLK0_OUT : out std_logic;
	181	LOCKED_OUT : out std_logic);
	182	end component;
	183
b98e21a5	184	signal pci_rst_i : std_logic;
40a1f26c	185	signal pci_rst_o : std_logic;
40a1f26c	186	signal pci_rst_oe_o : std_logic;
b98e21a5	187	signal pci_inta_i : std_logic;
40a1f26c	188	signal pci_inta_o : std_logic;
	189	signal pci_inta_oe_o : std_logic;
	190	signal pci_req_o : std_logic;
	191	signal pci_req_oe_o : std_logic;
b98e21a5	192	signal pci_frame_i : std_logic;
40a1f26c	193	signal pci_frame_o : std_logic;
40a1f26c	194	signal pci_frame_oe_o : std_logic;
b98e21a5	195	signal pci_irdy_i : std_logic;
40a1f26c	196	signal pci_irdy_o : std_logic;
40a1f26c	197	signal pci_irdy_oe_o : std_logic;
b98e21a5	198	signal pci_devsel_i : std_logic;
40a1f26c	199	signal pci_devsel_o : std_logic;
40a1f26c	200	signal pci_devsel_oe_o : std_logic;
b98e21a5	201	signal pci_trdy_i : std_logic;
40a1f26c	202	signal pci_trdy_o : std_logic;
40a1f26c	203	signal pci_trdy_oe_o : std_logic;
b98e21a5	204	signal pci_stop_i : std_logic;
40a1f26c	205	signal pci_stop_o : std_logic;
40a1f26c	206	signal pci_stop_oe_o : std_logic;
b98e21a5	207	signal pci_par_i : std_logic;
40a1f26c	208	signal pci_par_o : std_logic;
40a1f26c	209	signal pci_par_oe_o : std_logic;
b98e21a5	210	signal pci_perr_i : std_logic;
40a1f26c	211	signal pci_perr_o : std_logic;
40a1f26c	212	signal pci_perr_oe_o : std_logic;
b98e21a5	213	signal pci_serr_i : std_logic;
40a1f26c	214	signal pci_serr_o : std_logic;
40a1f26c	215	signal pci_serr_oe_o : std_logic;
27f6f620	216	signal pci_ad_oe_o : std_logic_vector(31 downto 0);
27f6f620	217	signal pci_cbe_oe_o : std_logic_vector(3 downto 0);
b98e21a5	218	signal pci_ad_i : std_logic_vector (31 downto 0);
40a1f26c	219	signal pci_ad_o : std_logic_vector (31 downto 0);
b98e21a5	220	signal pci_cbe_i : std_logic_vector (3 downto 0);
40a1f26c	221	signal pci_cbe_o : std_logic_vector (3 downto 0);
40a1f26c	222
27f6f620	223	signal wb_clk_i : std_logic;
	224	signal wb_rst_i : std_logic;
	225	signal wb_dat_i : std_logic_vector (31 downto 0);
	226	signal wb_dat_o : std_logic_vector (31 downto 0);
	227	signal wb_adr_i : std_logic_vector (11 downto 2);
	228	signal wb_sel_i : std_logic_vector (3 downto 0);
	229	signal wb_we_i : std_logic;
	230	signal wb_cyc_i : std_logic;
	231	signal wb_stb_i : std_logic;
	232	signal wb_ack_o : std_logic;
	233	signal wb_err_o : std_logic;
	234	signal m_wb_adr_o : std_logic_vector(31 downto 0);
	235	signal m_wb_sel_o : std_logic_vector(3 downto 0);
	236	signal m_wb_we_o : std_logic;
	237	signal m_wb_dat_o : std_logic_vector(31 downto 0);
	238	signal m_wb_dat_i : std_logic_vector(31 downto 0);
	239	signal m_wb_cyc_o : std_logic;
	240	signal m_wb_stb_o : std_logic;
	241	signal m_wb_ack_i : std_logic;
	242	signal m_wb_err_i : std_logic;
b98e21a5	243	signal md_pad_i : std_logic;
27f6f620	244	signal md_pad_o : std_logic;
	245	signal md_padoe_o : std_logic;
	246	signal int_o : std_logic;
	247	signal wbm_adr_o : std_logic_vector(31 downto 0);
4b4adc0d	248	signal mdc_pad_o_watch : std_logic;
27f6f620	249
361ec26f	250	signal m_wb_cti_o : std_logic_vector(2 downto 0);
	251	signal m_wb_bte_o : std_logic_vector(1 downto 0);
	252
c8b3e197	253	signal control0 : std_logic_vector(35 downto 0);
	254	signal data : std_logic_vector(63 downto 0);
	255	signal trig0 : std_logic_vector(31 downto 0);
	256
	257
40a1f26c	258	BEGIN
40a1f26c	259
b98e21a5 MG	260	IOBUF_PCI_RSTn: IOBUF
	261	port map (
	262	IO => PCI_RSTn,
	263	T => pci_rst_oe_o,
	264	I => pci_rst_o,
	265	O => pci_rst_i
	266	);
	267	IOBUF_PCI_INTAn: IOBUF
	268	port map (
	269	IO => PCI_INTAn,
	270	T => pci_inta_oe_o,
	271	I => pci_inta_o,
	272	O => pci_inta_i
	273	);
	274	OBUFT_PCI_REQn: OBUFT
	275	port map (
	276	O => PCI_REQn,
	277	T => pci_req_oe_o,
	278	I => pci_req_o
	279	);
	280	IOBUF_PCI_FRAMEn: IOBUF
	281	port map (
	282	IO => PCI_FRAMEn,
	283	T => pci_frame_oe_o,
	284	I => pci_frame_o,
	285	O => pci_frame_i
	286	);
	287	IOBUF_PCI_IRDYn: IOBUF
	288	port map (
	289	IO => PCI_IRDYn,
	290	T => pci_irdy_oe_o,
	291	I => pci_irdy_o,
	292	O => pci_irdy_i
	293	);
	294	IOBUF_PCI_DEVSELn: IOBUF
	295	port map (
	296	IO => PCI_DEVSELn,
	297	T => pci_devsel_oe_o,
	298	I => pci_devsel_o,
	299	O => pci_devsel_i
	300	);
	301	IOBUF_PCI_TRDYn: IOBUF
	302	port map (
	303	IO => PCI_TRDYn,
	304	T => pci_trdy_oe_o,
	305	I => pci_trdy_o,
	306	O => pci_trdy_i
	307	);
	308	IOBUF_PCI_STOPn: IOBUF
	309	port map (
	310	IO => PCI_STOPn,
	311	T => pci_stop_oe_o,
	312	I => pci_stop_o,
	313	O => pci_stop_i
	314	);
	315	IOBUF_PCI_PAR: IOBUF
	316	port map (
	317	IO => PCI_PAR,
	318	T => pci_par_oe_o,
	319	I => pci_par_o,
	320	O => pci_par_i
	321	);
	322	IOBUF_PCI_PERRn: IOBUF
	323	port map (
324	IO => PCI_PERRn,
325	T => pci_perr_oe_o,
326	I => pci_perr_o,
327	O => pci_perr_i
328	);
329	IOBUF_PCI_SERRn: IOBUF
330	port map (
331	IO => PCI_SERRn,
332	T => pci_serr_oe_o,
333	I => pci_serr_o,
334	O => pci_serr_i
335	);
336	IOBUF_MD_PAD_IO: IOBUF
337	port map (
338	IO => MD_PAD_IO,
339	T => md_padoe_o,
340	I => md_pad_o,
341	O => md_pad_i
342	);
27f6f620	343
27f6f620	344	BLA1: FOR i in 31 downto 0 generate
b98e21a5 MG	345	IOBUF_PCI_AD: IOBUF
	346	port map (
	347	IO => PCI_AD(i),
	348	T => pci_ad_oe_o(i),
	349	I => pci_ad_o(i),
	350	O => pci_ad_i(i)
	351	);
27f6f620	352	end generate;
	353
	354	BLA2: FOR i in 3 downto 0 generate
b98e21a5 MG	355	IOBUF_PCI_CBEn: IOBUF
	356	port map (
	357	IO => PCI_CBEn(i),
	358	T => pci_cbe_oe_o(i),
	359	I => pci_cbe_o(i),
	360	O => pci_cbe_i(i)
	361	);
27f6f620	362	end generate;
27f6f620	363
1a94112a	364	wb_adr_i(11 downto 8) <= (others => '0');
1a94112a	365	wb_adr_i(7 downto 2) <= wbm_adr_o (7 downto 2);
23944ea1	366
2c4b2f25	367	wb_clk_i <= PCI_CLOCK;
2c4b2f25	368
23944ea1	369	data(31 downto 0) <= wbm_adr_o;
fcff4515	370	data(39 downto 32) <= wbm_adr_o (7 downto 0);
b98e21a5	371	data(40) <= md_pad_i;
fcff4515	372	data(41) <= md_pad_o;
	373	data(42) <= md_padoe_o;
	374	data(43) <= mdc_pad_o_watch;
de64fba0	375	data(44) <= pci_inta_o;
de64fba0	376	data(63 downto 45) <= (others => '0');
c8b3e197	377
b98e21a5 MG	378	MDC_PAD_O <= mdc_pad_o_watch;
b98e21a5 MG	379
0d71737f	380	trig0(31 downto 0) <= (
c8b3e197	381	0 => wb_stb_i,
b98e21a5	382	1 => md_pad_i,
4b4adc0d	383	2 => md_pad_o,
4b4adc0d	384	3 => md_padoe_o,
c8b3e197	385	others => '0'
	386	);
	387
40a1f26c	388	Inst_pci_bridge32: pci_bridge32 PORT MAP(
27f6f620	389	wb_clk_i => wb_clk_i ,
	390	wb_rst_i => '0',
	391	wb_rst_o => wb_rst_i,
	392	wb_int_i => int_o,
	393	-- wb_int_o => ,
	394	wbs_adr_i => m_wb_adr_o ,
	395	wbs_dat_i => m_wb_dat_o,
	396	wbs_dat_o => m_wb_dat_i,
	397	wbs_sel_i => m_wb_sel_o,
	398	wbs_cyc_i => m_wb_cyc_o,
	399	wbs_stb_i => m_wb_stb_o,
	400	wbs_we_i => m_wb_we_o,
361ec26f	401	wbs_cti_i => m_wb_cti_o,
361ec26f	402	wbs_bte_i => m_wb_bte_o,
27f6f620	403	wbs_ack_o => m_wb_ack_i,
	404	-- wbs_rty_o => ,
	405	wbs_err_o => m_wb_err_i,
	406	wbm_adr_o => wbm_adr_o,
	407	wbm_dat_i => wb_dat_o,
	408	wbm_dat_o => wb_dat_i,
	409	wbm_sel_o => wb_sel_i,
	410	wbm_cyc_o => wb_cyc_i,
	411	wbm_stb_o => wb_stb_i,
	412	wbm_we_o => wb_we_i,
	413	-- wbm_cti_o => ,
	414	-- wbm_bte_o => ,
	415	wbm_ack_i => wb_ack_o ,
	416	wbm_rty_i => '0',
	417	wbm_err_i => wb_err_o,
40a1f26c	418	pci_clk_i => PCI_CLOCK,
b98e21a5	419	pci_rst_i => pci_rst_i,
40a1f26c	420	pci_rst_o => pci_rst_o ,
40a1f26c	421	pci_rst_oe_o => pci_rst_oe_o,
b98e21a5	422	pci_inta_i => pci_inta_i,
40a1f26c	423	pci_inta_o => pci_inta_o,
	424	pci_inta_oe_o => pci_inta_oe_o,
	425	pci_req_o => pci_req_o,
	426	pci_req_oe_o => pci_req_oe_o,
221bd70b	427	pci_gnt_i => PCI_GNTn,
b98e21a5	428	pci_frame_i => pci_frame_i,
40a1f26c	429	pci_frame_o => pci_frame_o,
	430	pci_frame_oe_o => pci_frame_oe_o,
	431	pci_irdy_oe_o => pci_irdy_oe_o,
	432	pci_devsel_oe_o => pci_devsel_oe_o,
	433	pci_trdy_oe_o => pci_trdy_oe_o,
	434	pci_stop_oe_o => pci_stop_oe_o,
	435	pci_ad_oe_o => pci_ad_oe_o,
	436	pci_cbe_oe_o => pci_cbe_oe_o,
b98e21a5	437	pci_irdy_i => pci_irdy_i,
40a1f26c	438	pci_irdy_o => pci_irdy_o,
40a1f26c	439	pci_idsel_i => PCI_IDSEL,
b98e21a5	440	pci_devsel_i => pci_devsel_i,
40a1f26c	441	pci_devsel_o => pci_devsel_o,
b98e21a5	442	pci_trdy_i => pci_trdy_i,
40a1f26c	443	pci_trdy_o => pci_trdy_o,
b98e21a5	444	pci_stop_i => pci_stop_i,
40a1f26c	445	pci_stop_o => pci_stop_o,
b98e21a5	446	pci_ad_i => pci_ad_i,
40a1f26c	447	pci_ad_o => pci_ad_o,
b98e21a5	448	pci_cbe_i => pci_cbe_i,
40a1f26c	449	pci_cbe_o => pci_cbe_o,
b98e21a5	450	pci_par_i => pci_par_i,
40a1f26c	451	pci_par_o => pci_par_o,
40a1f26c	452	pci_par_oe_o => pci_par_oe_o,
b98e21a5	453	pci_perr_i => pci_perr_i,
40a1f26c	454	pci_perr_o => pci_perr_o,
	455	pci_perr_oe_o => pci_perr_oe_o,
	456	pci_serr_o => pci_serr_o,
	457	pci_serr_oe_o => pci_serr_oe_o
	458	);
	459
	460	Inst_eth_top: eth_top PORT MAP(
27f6f620	461	wb_clk_i => wb_clk_i ,
	462	wb_rst_i => wb_rst_i ,
	463	wb_dat_i => wb_dat_i ,
	464	wb_dat_o => wb_dat_o ,
	465	wb_adr_i => wb_adr_i ,
	466	wb_sel_i => wb_sel_i ,
	467	wb_we_i => wb_we_i ,
	468	wb_cyc_i => wb_cyc_i ,
3f7aa675	469	wb_stb_i => wb_stb_i,
27f6f620	470	wb_ack_o => wb_ack_o ,
	471	wb_err_o => wb_err_o ,
	472	m_wb_adr_o => m_wb_adr_o,
	473	m_wb_sel_o => m_wb_sel_o,
	474	m_wb_we_o => m_wb_we_o ,
	475	m_wb_dat_o => m_wb_dat_o,
	476	m_wb_dat_i => m_wb_dat_i,
	477	m_wb_cyc_o => m_wb_cyc_o,
	478	m_wb_stb_o => m_wb_stb_o,
	479	m_wb_ack_i => m_wb_ack_i,
	480	m_wb_err_i => m_wb_err_i,
	481	mtx_clk_pad_i => MTX_CLK_PAD_I,
	482	mtxd_pad_o => MTXD_PAD_O,
	483	mtxen_pad_o => MTXEN_PAD_O,
4d7b5fdd	484	mtxerr_pad_o => LED_2,
27f6f620	485	mrx_clk_pad_i => MRX_CLK_PAD_I,
	486	mrxd_pad_i => MRXD_PAD_I,
	487	mrxdv_pad_i => MRXDV_PAD_I,
	488	mrxerr_pad_i => MRXERR_PAD_I,
	489	mcoll_pad_i => MCOLL_PAD_I,
	490	mcrs_pad_i => MCRS_PAD_I,
4b4adc0d	491	mdc_pad_o => mdc_pad_o_watch,
b98e21a5	492	md_pad_i => md_pad_i,
27f6f620	493	md_pad_o => md_pad_o,
27f6f620	494	md_padoe_o => md_padoe_o,
361ec26f	495	m_wb_cti_o => m_wb_cti_o,
361ec26f	496	m_wb_bte_o => m_wb_bte_o,
27f6f620	497	int_o => int_o
40a1f26c	498	);
40a1f26c	499
c8b3e197	500	i_icon : icon
	501	port map (
	502	control0 => control0
	503	);
	504
	505	i_ila : ila
	506	port map (
	507	control => control0,
	508	clk => PCI_CLOCK,
	509	data => data,
	510	trig0 => trig0
	511	);
70f633de	512
ac5b8271	513	eth_dcm : phydcm
	514	port map (
	515	CLKIN_IN => PCI_CLOCK,
b98e21a5	516	RST_IN => not pci_rst_i,
675f45d0	517	CLKFX_OUT => PHY_CLOCK,
	518	CLK0_OUT => open,
	519	LOCKED_OUT => open
ac5b8271	520	);
ac5b8271	521
27f6f620	522	end architecture ethernet_arch;