cvs.zerfleddert.de Git - raggedstone/blob - ethernet/source/top.vhd

   1 LIBRARY ieee;
   2 USE ieee.std_logic_1164.ALL;
   3 Library UNISIM;
   4 use UNISIM.vcomponents.all;
   5
   6 entity ethernet is
   7 PORT(
   8         PCI_AD : INOUT std_logic_vector(31 downto 0);
   9         PCI_CLOCK : IN std_logic;
  10         PCI_IDSEL : IN std_logic;
  11         PCI_CBEn : INOUT std_logic_vector (3 downto 0);
  12         PCI_FRAMEn : INOUT std_logic;
  13         PCI_IRDYn : INOUT std_logic;
  14         PCI_RSTn : INOUT std_logic;
  15         PCI_DEVSELn : INOUT std_logic;
  16         PCI_INTAn : INOUT std_logic;
  17         PCI_PERRn : INOUT std_logic;
  18         PCI_SERRn : INOUT std_logic;
  19         PCI_STOPn : INOUT std_logic;
  20         PCI_TRDYn : INOUT std_logic;
  21         PCI_PAR   : INOUT std_logic;
  22         PCI_REQn  : OUT std_logic;
  23         PCI_GNTn : IN std_logic;
  24
  25         MTX_CLK_PAD_I : IN std_logic;
  26         MTXD_PAD_O : OUT std_logic_vector (3 downto 0);
  27         MTXEN_PAD_O : OUT std_logic;
  28         MRX_CLK_PAD_I : IN std_logic;
  29         MRXD_PAD_I : IN std_logic_vector (3 downto 0);
  30         MRXDV_PAD_I : IN std_logic;
  31         MRXERR_PAD_I : IN std_logic;
  32         MCOLL_PAD_I : IN std_logic;
  33         MCRS_PAD_I : IN std_logic;
  34         MD_PAD_IO : INOUT std_logic;
  35         MDC_PAD_O : OUT std_logic;
  36
  37         PHY_CLOCK : OUT std_logic;
  38
  39         LED_2 : OUT std_logic
  40 );
  41 end ethernet;
  42
  43 architecture ethernet_arch of ethernet is
  44
  45 COMPONENT eth_top
  46 PORT(
  47         wb_clk_i : IN std_logic;
  48         wb_rst_i : IN std_logic;
  49         wb_dat_i : IN std_logic_vector(31 downto 0);
  50         wb_adr_i : IN std_logic_vector(11 downto 2);
  51         wb_sel_i : IN std_logic_vector(3 downto 0);
  52         wb_we_i : IN std_logic;
  53         wb_cyc_i : IN std_logic;
  54         wb_stb_i : IN std_logic;
  55         m_wb_dat_i : IN std_logic_vector(31 downto 0);
  56         m_wb_ack_i : IN std_logic;
  57         m_wb_err_i : IN std_logic;
  58         mtx_clk_pad_i : IN std_logic;
  59         mrx_clk_pad_i : IN std_logic;
  60         mrxd_pad_i : IN std_logic_vector(3 downto 0);
  61         mrxdv_pad_i : IN std_logic;
  62         mrxerr_pad_i : IN std_logic;
  63         mcoll_pad_i : IN std_logic;
  64         mcrs_pad_i : IN std_logic;
  65         md_pad_i : IN std_logic;
  66         wb_dat_o : OUT std_logic_vector(31 downto 0);
  67         wb_ack_o : OUT std_logic;
  68         wb_err_o : OUT std_logic;
  69         m_wb_adr_o : OUT std_logic_vector(31 downto 0);
  70         m_wb_sel_o : OUT std_logic_vector(3 downto 0);
  71         m_wb_we_o : OUT std_logic;
  72         m_wb_dat_o : OUT std_logic_vector(31 downto 0);
  73         m_wb_cyc_o : OUT std_logic;
  74         m_wb_stb_o : OUT std_logic;
  75         mtxd_pad_o : OUT std_logic_vector(3 downto 0);
  76         mtxen_pad_o : OUT std_logic;
  77         mtxerr_pad_o : OUT std_logic;
  78         mdc_pad_o : OUT std_logic;
  79         md_pad_o : OUT std_logic;
  80         md_padoe_o : OUT std_logic;
  81         m_wb_cti_o : OUT std_logic_vector(2 downto 0);
  82         m_wb_bte_o : OUT std_logic_vector(1 downto 0);
  83         int_o : OUT std_logic
  84         );
  85 END COMPONENT;
  86
  87 COMPONENT pci_bridge32
  88 PORT(
  89         wb_clk_i : IN std_logic;
  90         wb_rst_i : IN std_logic;
  91         wb_int_i : IN std_logic;
  92         wbs_adr_i : IN std_logic_vector(31 downto 0);
  93         wbs_dat_i : IN std_logic_vector(31 downto 0);
  94         wbs_sel_i : IN std_logic_vector(3 downto 0);
  95         wbs_cyc_i : IN std_logic;
  96         wbs_stb_i : IN std_logic;
  97         wbs_we_i : IN std_logic;
  98         wbs_cti_i : IN std_logic_vector(2 downto 0);
  99         wbs_bte_i : IN std_logic_vector(1 downto 0);
 100         wbm_dat_i : IN std_logic_vector(31 downto 0);
 101         wbm_ack_i : IN std_logic;
 102         wbm_rty_i : IN std_logic;
 103         wbm_err_i : IN std_logic;
 104         pci_clk_i : IN std_logic;
 105         pci_rst_i : IN std_logic;
 106         pci_inta_i : IN std_logic;
 107         pci_gnt_i : IN std_logic;
 108         pci_frame_i : IN std_logic;
 109         pci_irdy_i : IN std_logic;
 110         pci_idsel_i : IN std_logic;
 111         pci_devsel_i : IN std_logic;
 112         pci_trdy_i : IN std_logic;
 113         pci_stop_i : IN std_logic;
 114         pci_ad_i : IN std_logic_vector(31 downto 0);
 115         pci_cbe_i : IN std_logic_vector(3 downto 0);
 116         pci_par_i : IN std_logic;
 117         pci_perr_i : IN std_logic;
 118         wb_rst_o : OUT std_logic;
 119         wb_int_o : OUT std_logic;
 120         wbs_dat_o : OUT std_logic_vector(31 downto 0);
 121         wbs_ack_o : OUT std_logic;
 122         wbs_rty_o : OUT std_logic;
 123         wbs_err_o : OUT std_logic;
 124         wbm_adr_o : OUT std_logic_vector(31 downto 0);
 125         wbm_dat_o : OUT std_logic_vector(31 downto 0);
 126         wbm_sel_o : OUT std_logic_vector(3 downto 0);
 127         wbm_cyc_o : OUT std_logic;
 128         wbm_stb_o : OUT std_logic;
 129         wbm_we_o : OUT std_logic;
 130         wbm_cti_o : OUT std_logic_vector(2 downto 0);
 131         wbm_bte_o : OUT std_logic_vector(1 downto 0);
 132         pci_rst_o : OUT std_logic;
 133         pci_inta_o : OUT std_logic;
 134         pci_rst_oe_o : OUT std_logic;
 135         pci_inta_oe_o : OUT std_logic;
 136         pci_req_o : OUT std_logic;
 137         pci_req_oe_o : OUT std_logic;
 138         pci_frame_o : OUT std_logic;
 139         pci_frame_oe_o : OUT std_logic;
 140         pci_irdy_oe_o : OUT std_logic;
 141         pci_devsel_oe_o : OUT std_logic;
 142         pci_trdy_oe_o : OUT std_logic;
 143         pci_stop_oe_o : OUT std_logic;
 144         pci_ad_oe_o : OUT std_logic_vector(31 downto 0);
 145         pci_cbe_oe_o : OUT std_logic_vector(3 downto 0);
 146         pci_irdy_o : OUT std_logic;
 147         pci_devsel_o : OUT std_logic;
 148         pci_trdy_o : OUT std_logic;
 149         pci_stop_o : OUT std_logic;
 150         pci_ad_o : OUT std_logic_vector(31 downto 0);
 151         pci_cbe_o : OUT std_logic_vector(3 downto 0);
 152         pci_par_o : OUT std_logic;
 153         pci_par_oe_o : OUT std_logic;
 154         pci_perr_o : OUT std_logic;
 155         pci_perr_oe_o : OUT std_logic;
 156         pci_serr_o : OUT std_logic;
 157         pci_serr_oe_o : OUT std_logic
 158         );
 159 END COMPONENT;
 160
 161 component icon
 162 port (
 163         control0 : out std_logic_vector(35 downto 0)
 164         );
 165 end component;
 166
 167 component ila
 168 port (
 169         control : in std_logic_vector(35 downto 0);
 170         clk : in std_logic;
 171         data : in std_logic_vector(63 downto 0);
 172         trig0 : in std_logic_vector(31 downto 0)
 173         );
 174 end component;
 175
 176 component phydcm is
 177 port ( CLKIN_IN        : in    std_logic;
 178        RST_IN          : in    std_logic;
 179        CLKFX_OUT       : out   std_logic;
 180        CLK0_OUT        : out   std_logic;
 181        LOCKED_OUT      : out   std_logic);
 182 end component;
 183
 184 signal pci_rst_i : std_logic;
 185 signal pci_rst_o : std_logic;
 186 signal pci_rst_oe_o : std_logic;
 187 signal pci_inta_i : std_logic;
 188 signal pci_inta_o : std_logic;
 189 signal pci_inta_oe_o : std_logic;
 190 signal pci_req_o : std_logic;
 191 signal pci_req_oe_o : std_logic;
 192 signal pci_frame_i : std_logic;
 193 signal pci_frame_o : std_logic;
 194 signal pci_frame_oe_o : std_logic;
 195 signal pci_irdy_i : std_logic;
 196 signal pci_irdy_o : std_logic;
 197 signal pci_irdy_oe_o : std_logic;
 198 signal pci_devsel_i : std_logic;
 199 signal pci_devsel_o : std_logic;
 200 signal pci_devsel_oe_o : std_logic;
 201 signal pci_trdy_i : std_logic;
 202 signal pci_trdy_o : std_logic;
 203 signal pci_trdy_oe_o : std_logic;
 204 signal pci_stop_i : std_logic;
 205 signal pci_stop_o : std_logic;
 206 signal pci_stop_oe_o : std_logic;
 207 signal pci_par_i : std_logic;
 208 signal pci_par_o : std_logic;
 209 signal pci_par_oe_o : std_logic;
 210 signal pci_perr_i : std_logic;
 211 signal pci_perr_o : std_logic;
 212 signal pci_perr_oe_o : std_logic;
 213 signal pci_serr_i : std_logic;
 214 signal pci_serr_o : std_logic;
 215 signal pci_serr_oe_o : std_logic;
 216 signal pci_ad_oe_o : std_logic_vector(31 downto 0);
 217 signal pci_cbe_oe_o : std_logic_vector(3 downto 0);
 218 signal pci_ad_i : std_logic_vector (31 downto 0);
 219 signal pci_ad_o : std_logic_vector (31 downto 0);
 220 signal pci_cbe_i : std_logic_vector (3 downto 0);
 221 signal pci_cbe_o : std_logic_vector (3 downto 0);
 222
 223 signal wb_clk_i : std_logic;
 224 signal wb_rst_i : std_logic;
 225 signal wb_dat_i : std_logic_vector (31 downto 0);
 226 signal wb_dat_o : std_logic_vector (31 downto 0);
 227 signal wb_adr_i : std_logic_vector (11 downto 2);
 228 signal wb_sel_i : std_logic_vector (3 downto 0);
 229 signal wb_we_i : std_logic;
 230 signal wb_cyc_i : std_logic;
 231 signal wb_stb_i : std_logic;
 232 signal wb_ack_o : std_logic;
 233 signal wb_err_o : std_logic;
 234 signal m_wb_adr_o : std_logic_vector(31 downto 0);
 235 signal m_wb_sel_o : std_logic_vector(3 downto 0);
 236 signal m_wb_we_o : std_logic;
 237 signal m_wb_dat_o : std_logic_vector(31 downto 0);
 238 signal m_wb_dat_i : std_logic_vector(31 downto 0);
 239 signal m_wb_cyc_o : std_logic;
 240 signal m_wb_stb_o : std_logic;
 241 signal m_wb_ack_i : std_logic;
 242 signal m_wb_err_i : std_logic;
 243 signal md_pad_i : std_logic;
 244 signal md_pad_o : std_logic;
 245 signal md_padoe_o : std_logic;
 246 signal int_o : std_logic;
 247 signal wbm_adr_o : std_logic_vector(31 downto 0);
 248 signal mdc_pad_o_watch : std_logic;
 249
 250 signal m_wb_cti_o : std_logic_vector(2 downto 0);
 251 signal m_wb_bte_o : std_logic_vector(1 downto 0);
 252
 253 signal control0 : std_logic_vector(35 downto 0);
 254 signal data : std_logic_vector(63 downto 0);
 255 signal trig0 : std_logic_vector(31 downto 0);
 256
 257
 258 BEGIN
 259
 260 IOBUF_PCI_RSTn: IOBUF
 261 port map (
 262         IO => PCI_RSTn,
 263         T => pci_rst_oe_o,
 264         I => pci_rst_o,
 265         O => pci_rst_i
 266 );
 267 IOBUF_PCI_INTAn: IOBUF
 268 port map (
 269         IO => PCI_INTAn,
 270         T => pci_inta_oe_o,
 271         I => pci_inta_o,
 272         O => pci_inta_i
 273 );
 274 OBUFT_PCI_REQn: OBUFT
 275 port map (
 276         O => PCI_REQn,
 277         T => pci_req_oe_o,
 278         I => pci_req_o
 279 );
 280 IOBUF_PCI_FRAMEn: IOBUF
 281 port map (
 282         IO => PCI_FRAMEn,
 283         T => pci_frame_oe_o,
 284         I => pci_frame_o,
 285         O => pci_frame_i
 286 );
 287 IOBUF_PCI_IRDYn: IOBUF
 288 port map (
 289         IO => PCI_IRDYn,
 290         T => pci_irdy_oe_o,
 291         I => pci_irdy_o,
 292         O => pci_irdy_i
 293 );
 294 IOBUF_PCI_DEVSELn: IOBUF
 295 port map (
 296         IO => PCI_DEVSELn,
 297         T => pci_devsel_oe_o,
 298         I => pci_devsel_o,
 299         O => pci_devsel_i
 300 );
 301 IOBUF_PCI_TRDYn: IOBUF
 302 port map (
 303         IO => PCI_TRDYn,
 304         T => pci_trdy_oe_o,
 305         I => pci_trdy_o,
 306         O => pci_trdy_i
 307 );
 308 IOBUF_PCI_STOPn: IOBUF
 309 port map (
 310         IO => PCI_STOPn,
 311         T => pci_stop_oe_o,
 312         I => pci_stop_o,
 313         O => pci_stop_i
 314 );
 315 IOBUF_PCI_PAR: IOBUF
 316 port map (
 317         IO => PCI_PAR,
 318         T => pci_par_oe_o,
 319         I => pci_par_o,
 320         O => pci_par_i
 321 );
 322 IOBUF_PCI_PERRn: IOBUF
 323 port map (
 324         IO => PCI_PERRn,
 325         T => pci_perr_oe_o,
 326         I => pci_perr_o,
 327         O => pci_perr_i
 328 );
 329 IOBUF_PCI_SERRn: IOBUF
 330 port map (
 331         IO => PCI_SERRn,
 332         T => pci_serr_oe_o,
 333         I => pci_serr_o,
 334         O => pci_serr_i
 335 );
 336 IOBUF_MD_PAD_IO: IOBUF
 337 port map (
 338         IO => MD_PAD_IO,
 339         T => md_padoe_o,
 340         I => md_pad_o,
 341         O => md_pad_i
 342 );
 343
 344 BLA1: FOR i in 31 downto 0 generate
 345 IOBUF_PCI_AD: IOBUF
 346 port map (
 347         IO => PCI_AD(i),
 348         T => pci_ad_oe_o(i),
 349         I => pci_ad_o(i),
 350         O => pci_ad_i(i)
 351 );
 352 end generate;
 353
 354 BLA2: FOR i in 3 downto 0 generate
 355 IOBUF_PCI_CBEn: IOBUF
 356 port map (
 357         IO => PCI_CBEn(i),
 358         T => pci_cbe_oe_o(i),
 359         I => pci_cbe_o(i),
 360         O => pci_cbe_i(i)
 361 );
 362 end generate;
 363
 364 wb_adr_i(11 downto 8) <= (others => '0');
 365 wb_adr_i(7 downto 2)  <= wbm_adr_o (7 downto 2);
 366
 367 wb_clk_i <= PCI_CLOCK;
 368
 369 data(31 downto 0)  <= wbm_adr_o;
 370 data(39 downto 32) <= wbm_adr_o (7 downto 0);
 371 data(40) <= md_pad_i;
 372 data(41) <= md_pad_o;
 373 data(42) <= md_padoe_o;
 374 data(43) <= mdc_pad_o_watch;
 375 data(44) <= pci_inta_o;
 376 data(63 downto 45) <= (others => '0');
 377
 378 MDC_PAD_O <= mdc_pad_o_watch;
 379
 380 trig0(31 downto 0) <= (
 381         0 => wb_stb_i,
 382         1 => md_pad_i,
 383         2 => md_pad_o,
 384         3 => md_padoe_o,
 385         others => '0'
 386 );
 387
 388 Inst_pci_bridge32: pci_bridge32 PORT MAP(
 389         wb_clk_i => wb_clk_i ,
 390         wb_rst_i => '0',
 391         wb_rst_o => wb_rst_i,
 392         wb_int_i => int_o,
 393         -- wb_int_o => ,
 394         wbs_adr_i => m_wb_adr_o ,
 395         wbs_dat_i => m_wb_dat_o,
 396         wbs_dat_o => m_wb_dat_i,
 397         wbs_sel_i => m_wb_sel_o,
 398         wbs_cyc_i => m_wb_cyc_o,
 399         wbs_stb_i => m_wb_stb_o,
 400         wbs_we_i => m_wb_we_o,
 401         wbs_cti_i => m_wb_cti_o,
 402         wbs_bte_i => m_wb_bte_o,
 403         wbs_ack_o => m_wb_ack_i,
 404         -- wbs_rty_o => ,
 405         wbs_err_o => m_wb_err_i,
 406         wbm_adr_o => wbm_adr_o,
 407         wbm_dat_i => wb_dat_o,
 408         wbm_dat_o => wb_dat_i,
 409         wbm_sel_o => wb_sel_i,
 410         wbm_cyc_o => wb_cyc_i,
 411         wbm_stb_o => wb_stb_i,
 412         wbm_we_o => wb_we_i,
 413         -- wbm_cti_o => ,
 414         -- wbm_bte_o => ,
 415         wbm_ack_i => wb_ack_o ,
 416         wbm_rty_i => '0',
 417         wbm_err_i => wb_err_o,
 418         pci_clk_i => PCI_CLOCK,
 419         pci_rst_i => pci_rst_i,
 420         pci_rst_o => pci_rst_o ,
 421         pci_rst_oe_o => pci_rst_oe_o,
 422         pci_inta_i => pci_inta_i,
 423         pci_inta_o => pci_inta_o,
 424         pci_inta_oe_o => pci_inta_oe_o,
 425         pci_req_o => pci_req_o,
 426         pci_req_oe_o => pci_req_oe_o,
 427         pci_gnt_i => PCI_GNTn,
 428         pci_frame_i => pci_frame_i,
 429         pci_frame_o => pci_frame_o,
 430         pci_frame_oe_o => pci_frame_oe_o,
 431         pci_irdy_oe_o => pci_irdy_oe_o,
 432         pci_devsel_oe_o => pci_devsel_oe_o,
 433         pci_trdy_oe_o => pci_trdy_oe_o,
 434         pci_stop_oe_o => pci_stop_oe_o,
 435         pci_ad_oe_o => pci_ad_oe_o,
 436         pci_cbe_oe_o => pci_cbe_oe_o,
 437         pci_irdy_i => pci_irdy_i,
 438         pci_irdy_o => pci_irdy_o,
 439         pci_idsel_i => PCI_IDSEL,
 440         pci_devsel_i => pci_devsel_i,
 441         pci_devsel_o => pci_devsel_o,
 442         pci_trdy_i => pci_trdy_i,
 443         pci_trdy_o => pci_trdy_o,
 444         pci_stop_i => pci_stop_i,
 445         pci_stop_o => pci_stop_o,
 446         pci_ad_i => pci_ad_i,
 447         pci_ad_o => pci_ad_o,
 448         pci_cbe_i => pci_cbe_i,
 449         pci_cbe_o => pci_cbe_o,
 450         pci_par_i => pci_par_i,
 451         pci_par_o => pci_par_o,
 452         pci_par_oe_o => pci_par_oe_o,
 453         pci_perr_i => pci_perr_i,
 454         pci_perr_o => pci_perr_o,
 455         pci_perr_oe_o => pci_perr_oe_o,
 456         pci_serr_o => pci_serr_o,
 457         pci_serr_oe_o =>  pci_serr_oe_o
 458 );
 459
 460 Inst_eth_top: eth_top PORT MAP(
 461         wb_clk_i   => wb_clk_i  ,
 462         wb_rst_i   => wb_rst_i  ,
 463         wb_dat_i   => wb_dat_i  ,
 464         wb_dat_o   => wb_dat_o  ,
 465         wb_adr_i   => wb_adr_i  ,
 466         wb_sel_i   => wb_sel_i  ,
 467         wb_we_i    => wb_we_i   ,
 468         wb_cyc_i   => wb_cyc_i  ,
 469         wb_stb_i   => wb_stb_i,
 470         wb_ack_o   => wb_ack_o  ,
 471         wb_err_o   => wb_err_o  ,
 472         m_wb_adr_o => m_wb_adr_o,
 473         m_wb_sel_o => m_wb_sel_o,
 474         m_wb_we_o  => m_wb_we_o ,
 475         m_wb_dat_o => m_wb_dat_o,
 476         m_wb_dat_i => m_wb_dat_i,
 477         m_wb_cyc_o => m_wb_cyc_o,
 478         m_wb_stb_o => m_wb_stb_o,
 479         m_wb_ack_i => m_wb_ack_i,
 480         m_wb_err_i => m_wb_err_i,
 481         mtx_clk_pad_i => MTX_CLK_PAD_I,
 482         mtxd_pad_o => MTXD_PAD_O,
 483         mtxen_pad_o => MTXEN_PAD_O,
 484         mtxerr_pad_o => LED_2,
 485         mrx_clk_pad_i => MRX_CLK_PAD_I,
 486         mrxd_pad_i => MRXD_PAD_I,
 487         mrxdv_pad_i => MRXDV_PAD_I,
 488         mrxerr_pad_i => MRXERR_PAD_I,
 489         mcoll_pad_i => MCOLL_PAD_I,
 490         mcrs_pad_i => MCRS_PAD_I,
 491         mdc_pad_o => mdc_pad_o_watch,
 492         md_pad_i => md_pad_i,
 493         md_pad_o => md_pad_o,
 494         md_padoe_o => md_padoe_o,
 495         m_wb_cti_o => m_wb_cti_o,
 496         m_wb_bte_o => m_wb_bte_o,
 497         int_o => int_o
 498 );
 499
 500 i_icon : icon
 501 port map (
 502         control0 => control0
 503         );
 504
 505 i_ila : ila
 506 port map (
 507         control => control0,
 508         clk => PCI_CLOCK,
 509         data => data,
 510         trig0 => trig0
 511         );
 512
 513 eth_dcm : phydcm
 514 port map (
 515         CLKIN_IN => PCI_CLOCK,
 516         RST_IN => not pci_rst_i,
 517         CLKFX_OUT => PHY_CLOCK,
 518         CLK0_OUT => open,
 519         LOCKED_OUT => open
 520         );
 521
 522 end architecture ethernet_arch;