irgendwie gehts

[raggedstone] / dhwk / source / io_mux_reg.vhd

-- VHDL model created from schematic io_mux_reg.sch -- Jan 09 09:34:13 2007\r
\r
\r
\r
LIBRARY ieee;\r
\r
USE ieee.std_logic_1164.ALL;\r
USE ieee.numeric_std.ALL;\r
\r
\r
entity IO_MUX_REG is\r
      Port ( CONFIG_DATA : In    std_logic_vector (31 downto 0);\r
             LOAD_ADDR_REG : In    std_logic;\r
             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
             PCI_FRAMEn : In    std_logic;\r
             PCI_IDSEL : In    std_logic;\r
             PCI_IRDYn : In    std_logic;\r
             PCI_PAR : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             READ_SEL : In    std_logic_vector (1 downto 0);\r
             USER_DATA : In    std_logic_vector (31 downto 0);\r
              PCI_AD : InOut std_logic_vector (31 downto 0);\r
              AD_REG : Out   std_logic_vector (31 downto 0);\r
             ADDR_REG : Out   std_logic_vector (31 downto 0);\r
             CBE_REGn : Out   std_logic_vector (3 downto 0);\r
             FRAME_REGn : Out   std_logic;\r
             IDSEL_REG : Out   std_logic;\r
             IRDY_REGn : Out   std_logic;\r
             PAR_REG : Out   std_logic );\r
end IO_MUX_REG;\r
\r
architecture SCHEMATIC of IO_MUX_REG is\r
\r
   SIGNAL gnd : std_logic := '0';\r
   SIGNAL vcc : std_logic := '1';\r
\r
   signal  IO_DATA : std_logic_vector (31 downto 0);\r
   signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
\r
   component ADDR_REGI\r
      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
             LOAD_ADDR_REG : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             ADDR_REG : Out   std_logic_vector (31 downto 0) );\r
   end component;\r
\r
   component IO_REG\r
      Port ( IO_DATA : In    std_logic_vector (31 downto 0);\r
             OE_PCI_AD : In    std_logic;\r
             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
             PCI_FRAMEn : In    std_logic;\r
             PCI_IDSEL : In    std_logic;\r
             PCI_IRDYn : In    std_logic;\r
             PCI_PAR : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
              AD_REG : Out   std_logic_vector (31 downto 0);\r
             CBE_REGn : Out   std_logic_vector (3 downto 0);\r
             FRAME_REGn : Out   std_logic;\r
             IDSEL_REG : Out   std_logic;\r
             IRDY_REGn : Out   std_logic;\r
             PAR_REG : Out   std_logic;\r
              PCI_AD : Out   std_logic_vector (31 downto 0) );\r
   end component;\r
\r
   component IO_MUX\r
      Port ( CONFIG_DATA : In    std_logic_vector (31 downto 0);\r
              PCI_AD : In    std_logic_vector (31 downto 0);\r
             READ_SEL : In    std_logic_vector (1 downto 0);\r
             USER_DATA : In    std_logic_vector (31 downto 0);\r
             IO_DATA : Out   std_logic_vector (31 downto 0) );\r
   end component;\r
\r
begin\r
\r
   AD_REG <= AD_REG_DUMMY;\r
\r
   I5 : ADDR_REGI\r
      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
                 LOAD_ADDR_REG=>LOAD_ADDR_REG, PCI_CLOCK=>PCI_CLOCK,\r
                 PCI_RSTn=>PCI_RSTn,\r
                 ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0) );\r
   I1 : IO_REG\r
      Port Map ( IO_DATA(31 downto 0)=>IO_DATA(31 downto 0),\r
                 OE_PCI_AD=>READ_SEL(1),\r
                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
                 PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,\r
                 AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
                 IRDY_REGn=>IRDY_REGn, PAR_REG=>PAR_REG,\r
                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0) );\r
   I2 : IO_MUX\r
      Port Map ( CONFIG_DATA(31 downto 0)=>CONFIG_DATA(31 downto 0),\r
                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
                 USER_DATA(31 downto 0)=>USER_DATA(31 downto 0),\r
                 IO_DATA(31 downto 0)=>IO_DATA(31 downto 0) );\r
\r
end SCHEMATIC;\r