irgendwie gehts

diff --git a/dhwk/source/CONT_FSM.vhd b/dhwk/source/CONT_FSM.vhd
index 67fc8a719fe803d4f68e5bbf37b757e76e36292a..025c1e7a155f82c85b60b7e8647a3614fba7bd3a 100644 (file)
--- a/dhwk/source/CONT_FSM.vhd
+++ b/dhwk/source/CONT_FSM.vhd
@@ -57,7 +57,7 @@ architecture CONT_FSM_DESIGN of CONT_FSM is
        constant        ST_READ_3                       :std_logic_vector (9 downto 0) := "0100111111" ;-- 13F\r
 \r
        constant        ST_RD_FIFO_1    :std_logic_vector (9 downto 0) := "0000110011" ;-- 033\r
-       constant        ST_RD_FIFO_2    :std_logic_vector (9 downto 0) := "1000110011" ;-- 233\r
+       constant        ST_RD_FIFO_2    :std_logic_vector (9 downto 0) := "1100110011" ;-- 233\r
 \r
 \r
        constant        ST_WRITE_1              :std_logic_vector (9 downto 0) := "0111110010" ;-- 1F2\r

diff --git a/dhwk/source/fifo_control.vhd b/dhwk/source/fifo_control.vhd
index 1c2d52ea88c3bf00fc17e17e78b10958c20862b2..9a934046a5d88c7ba0e9a623724d37160c2befbe 100644 (file)
--- a/dhwk/source/fifo_control.vhd
+++ b/dhwk/source/fifo_control.vhd
@@ -44,7 +44,8 @@ entity FIFO_CONTROL is
              SPC_RDY_OUT : Out   std_logic;\r
              SR_ERROR : Out   std_logic;\r
              SYNC_FLAG : Out   std_logic_vector (7 downto 0);\r
-            PAR_SER_IN : Out std_logic_vector (7 downto 0));\r
+            PAR_SER_IN : Out std_logic_vector (7 downto 0);\r
+            SER_PAR_OUT : Out std_logic_vector (7 downto 0));\r
 end FIFO_CONTROL;\r
 \r
 architecture SCHEMATIC of FIFO_CONTROL is\r
@@ -56,6 +57,7 @@ architecture SCHEMATIC of FIFO_CONTROL is
    signal XXXS_FIFO_READn : std_logic;\r
    signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);\r
    signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);\r
+   signal watcher : std_logic_vector (7 downto 0);\r
 \r
    component SER_PAR_CON\r
       Port ( PCI_CLOCK : In    std_logic;\r
@@ -129,14 +131,15 @@ begin
 \r
    SYNC_FLAG <= SYNC_FLAG_DUMMY;\r
    PAR_SER_IN <= S_FIFO_Q_OUT;\r
-\r
+   SER_PAR_OUT <= watcher;\r
+   R_FIFO_D_IN(7 downto 0) <= watcher;\r
 \r
    RESERVE <= gnd;\r
    I23 : SER_PAR_CON\r
       Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
                  SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,\r
                  SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
-                 PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
+                 PAR_OUT(7 downto 0)=>watcher,\r
                  R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );\r
    I22 : PAR_SER_CON\r
       Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index e2f307c0e6266ff027978c13b07d9ba352ff5594..2d25fcd56fbfd04c0d1db0c626379d5b2d7ba114 100644 (file)
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -170,6 +170,7 @@ architecture SCHEMATIC of dhwk is
              SPC_RDY_OUT : Out   std_logic;\r
              SR_ERROR : Out   std_logic;\r
             PAR_SER_IN : Out std_logic_vector (7 downto 0);\r
+            SER_PAR_OUT : Out std_logic_vector (7 downto 0);\r
              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
    end component;\r
 \r
@@ -251,7 +252,7 @@ begin
        LED_4 <= '0';\r
        LED_5 <= not watch;\r
        PCI_INTAn <= watch;\r
-       trig0(7 downto 0) <= (0 => watch, others => '0');\r
+       trig0(7 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');\r
        data(0) <= watch;\r
        \r
        data(1) <= R_EFn;\r
@@ -272,6 +273,7 @@ begin
        data(16) <= SPC_RDY_IN;\r
        data(17) <= SERIAL_OUT;\r
        data(18) <= SPC_RDY_OUT;\r
+       data(34 downto 27) <= R_FIFO_Q_OUT;\r
 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r