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[raggedstone] / dhwk / source / reg_io.vhd

-- VHDL model created from schematic reg_io.sch -- Jan 09 09:34:12 2007\r
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LIBRARY ieee;\r
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USE ieee.std_logic_1164.ALL;\r
USE ieee.numeric_std.ALL;\r
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entity REG_IO is\r
      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
               RESET : In    std_logic;\r
             WRITE_XX1_0 : In    std_logic;\r
             WRITE_XX7_6 : In    std_logic;\r
             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0) );\r
end REG_IO;\r
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architecture SCHEMATIC of REG_IO is\r
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   SIGNAL gnd : std_logic := '0';\r
   SIGNAL vcc : std_logic := '1';\r
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   component REG\r
      Port (   CLOCK : In    std_logic;\r
              REG_IN : In    std_logic_vector (7 downto 0);\r
               RESET : In    std_logic;\r
               WRITE : In    std_logic;\r
             REG_OUT : Out   std_logic_vector (7 downto 0) );\r
   end component;\r
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begin\r
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   I14 : REG\r
      Port Map ( CLOCK=>PCI_CLOCK,\r
                 REG_IN(7 downto 0)=>AD_REG(7 downto 0), RESET=>RESET,\r
                 WRITE=>WRITE_XX1_0,\r
                 REG_OUT(7 downto 0)=>REG_OUT_XX0(7 downto 0) );\r
   I15 : REG\r
      Port Map ( CLOCK=>PCI_CLOCK,\r
                 REG_IN(7 downto 0)=>AD_REG(31 downto 24), RESET=>RESET,\r
                 WRITE=>WRITE_XX7_6,\r
                 REG_OUT(7 downto 0)=>REG_OUT_XX7(7 downto 0) );\r
   I16 : REG\r
      Port Map ( CLOCK=>PCI_CLOCK,\r
                 REG_IN(7 downto 0)=>AD_REG(23 downto 16), RESET=>RESET,\r
                 WRITE=>WRITE_XX7_6,\r
                 REG_OUT(7 downto 0)=>REG_OUT_XX6(7 downto 0) );\r
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end SCHEMATIC;\r