cvs.zerfleddert.de Git - raggedstone/blob - heartbeat/source/wb_7seg.v

   1 module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i,
   2         wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, DISP_SEL, DISP_LED);
   3
   4         input clk_i;
   5         input nrst_i;
   6         input [24:1] wb_adr_i;
   7         output [15:0] wb_dat_o;
   8         input [15:0] wb_dat_i;
   9         input [1:0] wb_sel_i;
  10         input wb_we_i;
  11         input wb_stb_i;
  12         input wb_cyc_i;
  13         output wb_ack_o;
  14         output wb_err_o;
  15         output wb_int_o;
  16         output reg [3:0] DISP_SEL;
  17         output reg [6:0] DISP_LED;
  18
  19         reg [15:0]      data_reg;
  20         reg     [6:0]   disp_cnt;
  21         reg     [3:0]   disp_data;
  22         wire    [6:0]   disp_data_led;
  23         reg     [3:0]   disp_pos;
  24
  25         always @(posedge clk_i or negedge nrst_i)
  26         begin
  27                 if (nrst_i == 0)
  28                         data_reg <= 16'hABCD;
  29                 else
  30                         if (wb_stb_i && wb_we_i)
  31                                 data_reg <= wb_dat_i;
  32         end
  33
  34         assign wb_ack_o = wb_stb_i;
  35         assign wb_err_o = 1'b0;
  36         assign wb_int_o = 1'b0;
  37         assign wb_dat_o = data_reg;
  38
  39         always @(posedge clk_i or negedge nrst_i)
  40         begin
  41                 if (nrst_i == 0)
  42                         disp_cnt <= 7'b0000000;
  43                 else
  44                         disp_cnt <= disp_cnt + 1;
  45         end
  46
  47         always @(posedge clk_i or negedge nrst_i)
  48         begin
  49                 if (nrst_i == 0)
  50                         disp_pos <= 4'b0010;
  51                 else
  52                         if (disp_cnt == 7'b1111111)
  53                                 disp_pos <= {DISP_SEL[2] , DISP_SEL[1] , DISP_SEL[0] , DISP_SEL[3]};
  54         end
  55
  56         always @(posedge clk_i or negedge nrst_i)
  57         begin
  58                 if (nrst_i == 0)
  59                         disp_data <= 4'b0000;
  60                 else
  61                         case (DISP_SEL)
  62                                 4'b1000: disp_data <= data_reg[3:0];
  63                                 4'b0100: disp_data <= data_reg[7:4];
  64                                 4'b0010: disp_data <= data_reg[11:8];
  65                                 4'b0001: disp_data <= data_reg[15:12];
  66                         endcase
  67         end
  68
  69         disp_dec u0 (disp_data, disp_data_led);
  70
  71         always @(posedge clk_i or negedge nrst_i)
  72         begin
  73                 if (nrst_i == 0)
  74                         DISP_LED <= 7'b0000000;
  75                 else
  76                         DISP_LED <= disp_data_led;
  77         end
  78
  79         always @(posedge clk_i or negedge nrst_i)
  80         begin
  81                 if (nrst_i == 0)
  82                         DISP_SEL <= 0;
  83                 else
  84                         DISP_SEL <= disp_pos;
  85         end
  86
  87 endmodule