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[raggedstone] / heartbeat / source / new_pci32tlite.vhd
1 --+-------------------------------------------------------------------------------------------------+
2 --| |
3 --| File: pci32tlite.vhd |
4 --| |
5 --| Components: pcidec_new.vhd |
6 --| pciwbsequ.vhd |
7 --| pcidmux.vhd |
8 --| pciregs.vhd |
9 --| pcipargen.vhd |
10 --| -- Libs -- |
11 --| ona.vhd |
12 --| |
13 --| Description: TARGET PCI : |
14 --| |
15 --| * PCI Target 32 Bits |
16 --| * BAR0 32MByte address space |
17 --| * Whisbone compatible: D16, 32MB address space |
18 --| |
19 --+-------------------------------------------------------------------------------------------------+
20 --| |
21 --| Revision history : |
22 --| Date Version Author Description |
23 --| 2005-05-13 R00A00 PAU First alfa revision (eng) |
24 --| 2006-01-05 R00B00 MS inverted reset nres |
25 --| and added debug signals debug_init and debug_access | |
26 --| |
27 --| To do: |
28 --| |
29 --+-------------------------------------------------------------------------------------------------+
30 --+-----------------------------------------------------------------+
31 --| |
32 --| Copyright (C) 2005 Peio Azkarate, peio@opencores.org |
33 --| |
34 --| This source file may be used and distributed without |
35 --| restriction provided that this copyright statement is not |
36 --| removed from the file and that any derivative work contains |
37 --| the original copyright notice and the associated disclaimer. |
38 --| |
39 --| This source file is free software; you can redistribute it |
40 --| and/or modify it under the terms of the GNU Lesser General |
41 --| Public License as published by the Free Software Foundation; |
42 --| either version 2.1 of the License, or (at your option) any |
43 --| later version. |
44 --| |
45 --| This source is distributed in the hope that it will be |
46 --| useful, but WITHOUT ANY WARRANTY; without even the implied |
47 --| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
48 --| PURPOSE. See the GNU Lesser General Public License for more |
49 --| details. |
50 --| |
51 --| You should have received a copy of the GNU Lesser General |
52 --| Public License along with this source; if not, download it |
53 --| from http://www.opencores.org/lgpl.shtml |
54 --| |
55 --+-----------------------------------------------------------------+
56
57 --+-----------------------------------------------------------------------------+
58 --| LIBRARIES |
59 --+-----------------------------------------------------------------------------+
60
61 library ieee;
62 use ieee.std_logic_1164.all;
63
64 --+-----------------------------------------------------------------------------+
65 --| ENTITY |
66 --+-----------------------------------------------------------------------------+
67
68 entity pci32tlite is
69 generic (
70
71 vendorID : std_logic_vector(15 downto 0) := x"10EE";
72 deviceID : std_logic_vector(15 downto 0) := x"0100";
73 revisionID : std_logic_vector(7 downto 0) := x"37";
74 subsystemID : std_logic_vector(15 downto 0) := x"1558";
75 subsystemvID : std_logic_vector(15 downto 0) := x"0480";
76 jcarr1ID : std_logic_vector(31 downto 0) := x"12345671";
77 jcarr2ID : std_logic_vector(31 downto 0) := x"12345672";
78 jcarr3ID : std_logic_vector(31 downto 0) := x"12345673";
79 jcarr4ID : std_logic_vector(31 downto 0) := x"12345674";
80 jcarr5ID : std_logic_vector(31 downto 0) := x"12345675";
81 jcarr6ID : std_logic_vector(31 downto 0) := x"12345676";
82 jcarr7ID : std_logic_vector(31 downto 0) := x"12345677";
83 jcarr8ID : std_logic_vector(31 downto 0) := x"12345678";
84 jcarr9ID : std_logic_vector(31 downto 0) := x"12345679";
85 jcarr10ID : std_logic_vector(31 downto 0) := x"12345680";
86 jcarr11ID : std_logic_vector(31 downto 0) := x"12345681";
87 jcarr12ID : std_logic_vector(31 downto 0) := x"12345682";
88 jcarr13ID : std_logic_vector(31 downto 0) := x"12345683";
89 jcarr14ID : std_logic_vector(31 downto 0) := x"12345684";
90 jcarr15ID : std_logic_vector(31 downto 0) := x"12345685";
91 jcarr16ID : std_logic_vector(31 downto 0) := x"12345686";
92 jcarr17ID : std_logic_vector(31 downto 0) := x"12345687";
93 jcarr18ID : std_logic_vector(31 downto 0) := x"12345688";
94 jcarr19ID : std_logic_vector(31 downto 0) := x"12345689";
95 jcarr20ID : std_logic_vector(31 downto 0) := x"12345690";
96 jcarr21ID : std_logic_vector(31 downto 0) := x"12345691";
97 jcarr22ID : std_logic_vector(31 downto 0) := x"12345692";
98 jcarr23ID : std_logic_vector(31 downto 0) := x"12345693";
99 jcarr24ID : std_logic_vector(31 downto 0) := x"12345694";
100 jcarr25ID : std_logic_vector(31 downto 0) := x"12345695";
101 jcarr26ID : std_logic_vector(31 downto 0) := x"12345696";
102 jcarr27ID : std_logic_vector(31 downto 0) := x"12345697";
103 jcarr28ID : std_logic_vector(31 downto 0) := x"12345698";
104 jcarr29ID : std_logic_vector(31 downto 0) := x"12345699";
105 jcarr30ID : std_logic_vector(31 downto 0) := x"12345700";
106 jcarr31ID : std_logic_vector(31 downto 0) := x"12345701";
107 jcarr32ID : std_logic_vector(31 downto 0) := x"12345702";
108 jcarr33ID : std_logic_vector(31 downto 0) := x"12345703";
109 jcarr34ID : std_logic_vector(31 downto 0) := x"12345704";
110 jcarr35ID : std_logic_vector(31 downto 0) := x"12345705";
111 jcarr36ID : std_logic_vector(31 downto 0) := x"12345706";
112 jcarr37ID : std_logic_vector(31 downto 0) := x"12345707";
113 jcarr38ID : std_logic_vector(31 downto 0) := x"12345708";
114 jcarr39ID : std_logic_vector(31 downto 0) := x"12345709";
115 jcarr40ID : std_logic_vector(31 downto 0) := x"12345710";
116 jcarr41ID : std_logic_vector(31 downto 0) := x"12345711";
117 jcarr42ID : std_logic_vector(31 downto 0) := x"12345712"
118
119 );
120 port (
121
122 -- General
123 clk33 : in std_logic;
124 nrst : in std_logic;
125
126 -- PCI target 32bits
127 ad : inout std_logic_vector(31 downto 0);
128 cbe : in std_logic_vector(3 downto 0);
129 par : out std_logic;
130 frame : in std_logic;
131 irdy : in std_logic;
132 trdy : out std_logic;
133 devsel : out std_logic;
134 stop : out std_logic;
135 idsel : in std_logic;
136 perr : out std_logic;
137 serr : out std_logic;
138 intb : out std_logic;
139
140 -- Master whisbone
141 wb_adr_o : out std_logic_vector(24 downto 1);
142 wb_dat_i : in std_logic_vector(15 downto 0);
143 wb_dat_o : out std_logic_vector(15 downto 0);
144 wb_sel_o : out std_logic_vector(1 downto 0);
145 wb_we_o : out std_logic;
146 wb_stb_o : inout std_logic;
147 wb_cyc_o : out std_logic;
148 wb_ack_i : in std_logic;
149 wb_err_i : in std_logic;
150 wb_int_i : in std_logic;
151
152 -- debug signals
153 debug_init : out std_logic;
154 debug_access : out std_logic
155
156 );
157 end pci32tlite;
158
159
160 --+-----------------------------------------------------------------------------+
161 --| ARCHITECTURE |
162 --+-----------------------------------------------------------------------------+
163
164 architecture rtl of pci32tlite is
165
166
167 --+-----------------------------------------------------------------------------+
168 --| COMPONENTS |
169 --+-----------------------------------------------------------------------------+
170
171
172 component pcidec_new
173 port (
174
175 clk_i : in std_logic;
176 nrst_i : in std_logic;
177 --
178 ad_i : in std_logic_vector(31 downto 0);
179 cbe_i : in std_logic_vector(3 downto 0);
180 idsel_i : in std_logic;
181 bar0_i : in std_logic_vector(31 downto 25);
182 memEN_i : in std_logic;
183 pciadrLD_i : in std_logic;
184 adrcfg_o : out std_logic;
185 adrmem_o : out std_logic;
186 adr_o : out std_logic_vector(24 downto 1);
187 cmd_o : out std_logic_vector(3 downto 0)
188
189 );
190 end component;
191
192
193 component pciwbsequ
194 port (
195
196 -- General
197 clk_i : in std_logic;
198 nrst_i : in std_logic;
199 -- pci
200 cmd_i : in std_logic_vector(3 downto 0);
201 cbe_i : in std_logic_vector(3 downto 0);
202 frame_i : in std_logic;
203 irdy_i : in std_logic;
204 devsel_o : out std_logic;
205 trdy_o : out std_logic;
206 -- control
207 adrcfg_i : in std_logic;
208 adrmem_i : in std_logic;
209 pciadrLD_o : out std_logic;
210 pcidOE_o : out std_logic;
211 parOE_o : out std_logic;
212 wbdatLD_o : out std_logic;
213 wbrgdMX_o : out std_logic;
214 wbd16MX_o : out std_logic;
215 wrcfg_o : out std_logic;
216 rdcfg_o : out std_logic;
217 -- whisbone
218 wb_sel_o : out std_logic_vector(1 downto 0);
219 wb_we_o : out std_logic;
220 wb_stb_o : inout std_logic;
221 wb_cyc_o : out std_logic;
222 wb_ack_i : in std_logic;
223 wb_err_i : in std_logic;
224 -- debug signals
225 debug_init : out std_logic;
226 debug_access : out std_logic
227 );
228 end component;
229
230
231 component pcidmux
232 port (
233
234 clk_i : in std_logic;
235 nrst_i : in std_logic;
236 --
237 d_io : inout std_logic_vector(31 downto 0);
238 pcidatout_o : out std_logic_vector(31 downto 0);
239 pcidOE_i : in std_logic;
240 wbdatLD_i : in std_logic;
241 wbrgdMX_i : in std_logic;
242 wbd16MX_i : in std_logic;
243 wb_dat_i : in std_logic_vector(15 downto 0);
244 wb_dat_o : out std_logic_vector(15 downto 0);
245 rg_dat_i : in std_logic_vector(31 downto 0);
246 rg_dat_o : out std_logic_vector(31 downto 0)
247
248 );
249 end component;
250
251
252 component pciregs
253 generic (
254
255 vendorID : std_logic_vector(15 downto 0);
256 deviceID : std_logic_vector(15 downto 0);
257 revisionID : std_logic_vector(7 downto 0);
258 subsystemID : std_logic_vector(15 downto 0);
259 subsystemvID : std_logic_vector(15 downto 0);
260 jcarr1ID : std_logic_vector(31 downto 0);
261 jcarr2ID : std_logic_vector(31 downto 0);
262 jcarr3ID : std_logic_vector(31 downto 0);
263 jcarr4ID : std_logic_vector(31 downto 0);
264 jcarr5ID : std_logic_vector(31 downto 0);
265 jcarr6ID : std_logic_vector(31 downto 0);
266 jcarr7ID : std_logic_vector(31 downto 0);
267 jcarr8ID : std_logic_vector(31 downto 0);
268 jcarr9ID : std_logic_vector(31 downto 0);
269 jcarr10ID : std_logic_vector(31 downto 0);
270 jcarr11ID : std_logic_vector(31 downto 0);
271 jcarr12ID : std_logic_vector(31 downto 0);
272 jcarr13ID : std_logic_vector(31 downto 0);
273 jcarr14ID : std_logic_vector(31 downto 0);
274 jcarr15ID : std_logic_vector(31 downto 0);
275 jcarr16ID : std_logic_vector(31 downto 0);
276 jcarr17ID : std_logic_vector(31 downto 0);
277 jcarr18ID : std_logic_vector(31 downto 0);
278 jcarr19ID : std_logic_vector(31 downto 0);
279 jcarr20ID : std_logic_vector(31 downto 0);
280 jcarr21ID : std_logic_vector(31 downto 0);
281 jcarr22ID : std_logic_vector(31 downto 0);
282 jcarr23ID : std_logic_vector(31 downto 0);
283 jcarr24ID : std_logic_vector(31 downto 0);
284 jcarr25ID : std_logic_vector(31 downto 0);
285 jcarr26ID : std_logic_vector(31 downto 0);
286 jcarr27ID : std_logic_vector(31 downto 0);
287 jcarr28ID : std_logic_vector(31 downto 0);
288 jcarr29ID : std_logic_vector(31 downto 0);
289 jcarr30ID : std_logic_vector(31 downto 0);
290 jcarr31ID : std_logic_vector(31 downto 0);
291 jcarr32ID : std_logic_vector(31 downto 0);
292 jcarr33ID : std_logic_vector(31 downto 0);
293 jcarr34ID : std_logic_vector(31 downto 0);
294 jcarr35ID : std_logic_vector(31 downto 0);
295 jcarr36ID : std_logic_vector(31 downto 0);
296 jcarr37ID : std_logic_vector(31 downto 0);
297 jcarr38ID : std_logic_vector(31 downto 0);
298 jcarr39ID : std_logic_vector(31 downto 0);
299 jcarr40ID : std_logic_vector(31 downto 0);
300 jcarr41ID : std_logic_vector(31 downto 0);
301 jcarr42ID : std_logic_vector(31 downto 0)
302
303 );
304 port (
305
306 clk_i : in std_logic;
307 nrst_i : in std_logic;
308 --
309 adr_i : in std_logic_vector(7 downto 2);
310 cbe_i : in std_logic_vector(3 downto 0);
311 dat_i : in std_logic_vector(31 downto 0);
312 dat_o : out std_logic_vector(31 downto 0);
313 wrcfg_i : in std_logic;
314 rdcfg_i : in std_logic;
315 perr_i : in std_logic;
316 serr_i : in std_logic;
317 tabort_i : in std_logic;
318 bar0_o : out std_logic_vector(31 downto 25);
319 perrEN_o : out std_logic;
320 serrEN_o : out std_logic;
321 memEN_o : out std_logic
322
323 );
324 end component;
325
326
327 component pcipargen
328 port (
329
330 clk_i : in std_logic;
331 pcidatout_i : in std_logic_vector(31 downto 0);
332 cbe_i : in std_logic_vector(3 downto 0);
333 parOE_i : in std_logic;
334 par_o : out std_logic
335
336 );
337 end component;
338
339
340 --+-----------------------------------------------------------------------------+
341 --| CONSTANTS |
342 --+-----------------------------------------------------------------------------+
343 --+-----------------------------------------------------------------------------+
344 --| SIGNALS |
345 --+-----------------------------------------------------------------------------+
346
347 signal bar0 : std_logic_vector(31 downto 25);
348 signal memEN : std_logic;
349 signal pciadrLD : std_logic;
350 signal adrcfg : std_logic;
351 signal adrmem : std_logic;
352 signal adr : std_logic_vector(24 downto 1);
353 signal cmd : std_logic_vector(3 downto 0);
354 signal pcidOE : std_logic;
355 signal parOE : std_logic;
356 signal wbdatLD : std_logic;
357 signal wbrgdMX : std_logic;
358 signal wbd16MX : std_logic;
359 signal wrcfg : std_logic;
360 signal rdcfg : std_logic;
361 signal pcidatread : std_logic_vector(31 downto 0);
362 signal pcidatwrite : std_logic_vector(31 downto 0);
363 signal pcidatout : std_logic_vector(31 downto 0);
364 signal parerr : std_logic;
365 signal syserr : std_logic;
366 signal tabort : std_logic;
367 signal perrEN : std_logic;
368 signal serrEN : std_logic;
369
370 begin
371
372
373 --+-------------------------------------------------------------------------+
374 --| Component instances |
375 --+-------------------------------------------------------------------------+
376
377 --+-----------------------------------------+
378 --| PCI decoder |
379 --+-----------------------------------------+
380
381 u1: component pcidec_new
382 port map (
383
384 clk_i => clk33,
385 nrst_i => nrst,
386 --
387 ad_i => ad,
388 cbe_i => cbe,
389 idsel_i => idsel,
390 bar0_i => bar0,
391 memEN_i => memEN,
392 pciadrLD_i => pciadrLD,
393 adrcfg_o => adrcfg,
394 adrmem_o => adrmem,
395 adr_o => adr,
396 cmd_o => cmd
397
398 );
399
400
401 --+-----------------------------------------+
402 --| PCI-WB Sequencer |
403 --+-----------------------------------------+
404
405 u2: component pciwbsequ
406 port map (
407
408 -- General
409 clk_i => clk33,
410 nrst_i => nrst,
411 -- pci
412 cmd_i => cmd,
413 cbe_i => cbe,
414 frame_i => frame,
415 irdy_i => irdy,
416 devsel_o => devsel,
417 trdy_o => trdy,
418 -- control
419 adrcfg_i => adrcfg,
420 adrmem_i => adrmem,
421 pciadrLD_o => pciadrLD,
422 pcidOE_o => pcidOE,
423 parOE_o => parOE,
424 wbdatLD_o => wbdatLD,
425 wbrgdMX_o => wbrgdMX,
426 wbd16MX_o => wbd16MX,
427 wrcfg_o => wrcfg,
428 rdcfg_o => rdcfg,
429 -- whisbone
430 wb_sel_o => wb_sel_o,
431 wb_we_o => wb_we_o,
432 wb_stb_o => wb_stb_o,
433 wb_cyc_o => wb_cyc_o,
434 wb_ack_i => wb_ack_i,
435 wb_err_i => wb_err_i,
436 -- debug signals
437 debug_init => debug_init,
438 debug_access => debug_access
439 );
440
441
442 --+-----------------------------------------+
443 --| PCI-wb datamultiplexer |
444 --+-----------------------------------------+
445
446 u3: component pcidmux
447 port map (
448
449 clk_i => clk33,
450 nrst_i => nrst,
451 --
452 d_io => ad,
453 pcidatout_o => pcidatout,
454 pcidOE_i => pcidOE,
455 wbdatLD_i => wbdatLD,
456 wbrgdMX_i => wbrgdMX,
457 wbd16MX_i => wbd16MX,
458 wb_dat_i => wb_dat_i,
459 wb_dat_o => wb_dat_o,
460 rg_dat_i => pcidatread,
461 rg_dat_o => pcidatwrite
462
463 );
464
465
466 --+-----------------------------------------+
467 --| PCI registers |
468 --+-----------------------------------------+
469
470 u4: component pciregs
471 generic map (
472
473 vendorID => vendorID,
474 deviceID => deviceID,
475 revisionID => revisionID,
476 subsystemID => subsystemID,
477 subsystemvID => subsystemvID,
478 jcarr1ID => jcarr1ID,
479 jcarr2ID => jcarr2ID,
480 jcarr3ID => jcarr3ID,
481 jcarr4ID => jcarr4ID,
482 jcarr5ID => jcarr5ID,
483 jcarr6ID => jcarr6ID,
484 jcarr7ID => jcarr7ID,
485 jcarr8ID => jcarr8ID,
486 jcarr9ID => jcarr9ID,
487 jcarr10ID => jcarr10ID,
488 jcarr11ID => jcarr11ID,
489 jcarr12ID => jcarr12ID,
490 jcarr13ID => jcarr13ID,
491 jcarr14ID => jcarr14ID,
492 jcarr15ID => jcarr15ID,
493 jcarr16ID => jcarr16ID,
494 jcarr17ID => jcarr17ID,
495 jcarr18ID => jcarr18ID,
496 jcarr19ID => jcarr19ID,
497 jcarr20ID => jcarr20ID,
498 jcarr21ID => jcarr21ID,
499 jcarr22ID => jcarr22ID,
500 jcarr23ID => jcarr23ID,
501 jcarr24ID => jcarr24ID,
502 jcarr25ID => jcarr25ID,
503 jcarr26ID => jcarr26ID,
504 jcarr27ID => jcarr27ID,
505 jcarr28ID => jcarr28ID,
506 jcarr29ID => jcarr29ID,
507 jcarr30ID => jcarr30ID,
508 jcarr31ID => jcarr31ID,
509 jcarr32ID => jcarr32ID,
510 jcarr33ID => jcarr33ID,
511 jcarr34ID => jcarr34ID,
512 jcarr35ID => jcarr35ID,
513 jcarr36ID => jcarr36ID,
514 jcarr37ID => jcarr37ID,
515 jcarr38ID => jcarr38ID,
516 jcarr39ID => jcarr39ID,
517 jcarr40ID => jcarr40ID,
518 jcarr41ID => jcarr41ID,
519 jcarr42ID => jcarr42ID
520
521 )
522 port map (
523
524 clk_i => clk33,
525 nrst_i => nrst,
526 --
527 adr_i => adr(7 downto 2),
528 cbe_i => cbe,
529 dat_i => pcidatwrite,
530 dat_o => pcidatread,
531 wrcfg_i => wrcfg,
532 rdcfg_i => rdcfg,
533 perr_i => parerr,
534 serr_i => syserr,
535 tabort_i => tabort,
536 bar0_o => bar0,
537 perrEN_o => perrEN,
538 serrEN_o => serrEN,
539 memEN_o => memEN
540
541 );
542
543 --+-----------------------------------------+
544 --| PCI Parity Gnerator |
545 --+-----------------------------------------+
546
547 u5: component pcipargen
548 port map (
549
550 clk_i => clk33,
551 pcidatout_i => pcidatout,
552 cbe_i => cbe,
553 parOE_i => parOE,
554 par_o => par
555
556 );
557
558
559 --+-----------------------------------------+
560 --| Whisbone Address bus |
561 --+-----------------------------------------+
562
563 wb_adr_o <= adr;
564
565
566 --+-----------------------------------------+
567 --| unimplemented |
568 --+-----------------------------------------+
569
570 parerr <= '0';
571 syserr <= '0';
572 tabort <= '0';
573
574
575 --+-----------------------------------------+
576 --| unused outputs |
577 --+-----------------------------------------+
578 -- #stop: Curret TARGET indicates to Master stop current transaction
579 -- #perr:
580 -- #serr:
581
582 perr <= 'Z';
583 serr <= 'Z';
584 stop <= 'Z';
585 intb <= '0' when ( wb_int_i = '1' ) else 'Z';
586
587
588 end rtl;
589
590
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