cvs.zerfleddert.de Git - raggedstone/blob - dhwk/source/Io_mux.vhd

   1 -- J.STELZNER
   2 -- INFORMATIK-3 LABOR
   3 -- 23.08.2006
   4 -- File: IO_MUX.VHD
   5
   6 library IEEE;
   7 use IEEE.std_logic_1164.all;
   8
   9 entity IO_MUX is
  10         port
  11         (
  12         READ_SEL                        :in             std_logic_vector ( 1 downto 0);
  13         USER_DATA                       :in             std_logic_vector (31 downto 0);
  14         CONFIG_DATA             :in             std_logic_vector (31 downto 0);
  15         PCI_AD                          :in             std_logic_vector (31 downto 0);
  16         IO_DATA                         :out    std_logic_vector (31 downto 0)
  17         );
  18 end entity IO_MUX;
  19
  20 architecture IO_MUX_DESIGN of IO_MUX is
  21
  22         signal  MUX             :std_logic_vector (31 downto 0);
  23
  24 begin
  25
  26         MUX     <=      PCI_AD                  when    READ_SEL        =       "00"    else    -- WRITE_CONFIG
  27                                         PCI_AD                  when    READ_SEL        =       "01"    else    -- WRITE_IO
  28                                         CONFIG_DATA     when    READ_SEL        =       "10"    else    -- READ_CONFIG
  29                                         USER_DATA               when    READ_SEL        =       "11"    else    -- READ_IO
  30                                         CONFIG_DATA;
  31
  32 --                                      MUX;
  33
  34         IO_DATA <= MUX;
  35
  36 end architecture IO_MUX_DESIGN;