cvs.zerfleddert.de Git - raggedstone/blob - dhwk/vio_core.xco

   1 # BEGIN Project Options
   2 SET addpads = False
   3 SET asysymbol = False
   4 SET busformat = BusFormatAngleBracketNotRipped
   5 SET createndf = False
   6 SET designentry = VHDL
   7 SET device = xc3s1500
   8 SET devicefamily = spartan3
   9 SET flowvendor = Other
  10 SET formalverification = False
  11 SET foundationsym = False
  12 SET implementationfiletype = Ngc
  13 SET package = fg456
  14 SET removerpms = False
  15 SET simulationfiles = Structural
  16 SET speedgrade = -4
  17 SET verilogsim = False
  18 SET vhdlsim = True
  19 # END Project Options
  20 # BEGIN Select
  21 SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.02.a
  22 # END Select
  23 # BEGIN Parameters
  24 CSET asynchronous_input_port_width=4
  25 CSET asynchronous_output_port_width=8
  26 CSET component_name=vio
  27 CSET enable_asynchronous_input_port=true
  28 CSET enable_asynchronous_output_port=false
  29 CSET enable_synchronous_input_port=false
  30 CSET enable_synchronous_output_port=true
  31 CSET invert_clock_input=false
  32 CSET synchronous_input_port_width=8
  33 CSET synchronous_output_port_width=1
  34 # END Parameters
  35 GENERATE