cvs.zerfleddert.de Git - raggedstone/blob - ethernet/source/pci/pci_target32_interface.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  File name: pci_target32_interface.v                         ////
   4 ////                                                              ////
   5 ////  This file is part of the "PCI bridge" project               ////
   6 ////  http://www.opencores.org/cores/pci/                         ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Tadej Markovic, tadej@opencores.org                   ////
  10 ////                                                              ////
  11 ////  All additional information is avaliable in the README.txt   ////
  12 ////  file.                                                       ////
  13 ////                                                              ////
  14 ////                                                              ////
  15 //////////////////////////////////////////////////////////////////////
  16 ////                                                              ////
  17 //// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org       ////
  18 ////                                                              ////
  19 //// This source file may be used and distributed without         ////
  20 //// restriction provided that this copyright statement is not    ////
  21 //// removed from the file and that any derivative work contains  ////
  22 //// the original copyright notice and the associated disclaimer. ////
  23 ////                                                              ////
  24 //// This source file is free software; you can redistribute it   ////
  25 //// and/or modify it under the terms of the GNU Lesser General   ////
  26 //// Public License as published by the Free Software Foundation; ////
  27 //// either version 2.1 of the License, or (at your option) any   ////
  28 //// later version.                                               ////
  29 ////                                                              ////
  30 //// This source is distributed in the hope that it will be       ////
  31 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  32 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  33 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  34 //// details.                                                     ////
  35 ////                                                              ////
  36 //// You should have received a copy of the GNU Lesser General    ////
  37 //// Public License along with this source; if not, download it   ////
  38 //// from http://www.opencores.org/lgpl.shtml                     ////
  39 ////                                                              ////
  40 //////////////////////////////////////////////////////////////////////
  41 //
  42 // CVS Revision History
  43 //
  44 // $Log: pci_target32_interface.v,v $
  45 // Revision 1.1  2007-03-20 17:50:56  sithglan
  46 // add shit
  47 //
  48 // Revision 1.11  2004/08/19 15:27:34  mihad
  49 // Changed minimum pci image size to 256 bytes because
  50 // of some PC system problems with size of IO images.
  51 //
  52 // Revision 1.10  2003/12/19 11:11:30  mihad
  53 // Compact PCI Hot Swap support added.
  54 // New testcases added.
  55 // Specification updated.
  56 // Test application changed to support WB B3 cycles.
  57 //
  58 // Revision 1.9  2003/08/21 20:55:14  tadejm
  59 // Corrected bug when writing to FIFO (now it is registered).
  60 //
  61 // Revision 1.8  2003/08/08 16:36:33  tadejm
  62 // Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
  63 //
  64 // Revision 1.7  2003/01/27 16:49:31  mihad
  65 // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
  66 //
  67 // Revision 1.6  2003/01/21 16:06:56  mihad
  68 // Bug fixes, testcases added.
  69 //
  70 // Revision 1.5  2002/08/22 13:28:04  mihad
  71 // Updated for synthesis purposes. Gate level simulation was failing in some configurations
  72 //
  73 // Revision 1.4  2002/02/19 16:32:37  mihad
  74 // Modified testbench and fixed some bugs
  75 //
  76 // Revision 1.3  2002/02/01 15:25:12  mihad
  77 // Repaired a few bugs, updated specification, added test bench files and design document
  78 //
  79 // Revision 1.2  2001/10/05 08:14:30  mihad
  80 // Updated all files with inclusion of timescale file for simulation purposes.
  81 //
  82 // Revision 1.1.1.1  2001/10/02 15:33:47  mihad
  83 // New project directory structure
  84 //
  85 //
  86
  87 `include "bus_commands.v"
  88 `include "pci_constants.v"
  89
  90 // synopsys translate_off
  91 `include "timescale.v"
  92 // synopsys translate_on
  93
  94 module pci_target32_interface
  95 (
  96     // system inputs
  97     clk_in,
  98     reset_in,
  99
 100     // PCI Target side of INTERFACE
 101     address_in,
 102     addr_claim_out,
 103     bc_in,
 104     bc0_in,
 105     data_in,
 106     data_out,
 107     be_in,
 108     next_be_in,
 109     req_in,
 110     rdy_in,
 111     addr_phase_in,
 112     bckp_devsel_in,
 113     bckp_trdy_in,
 114     bckp_stop_in,
 115     last_reg_in,
 116     frame_reg_in,
 117     fetch_pcir_fifo_in,
 118     load_medium_reg_in,
 119     sel_fifo_mreg_in,
 120     sel_conf_fifo_in,
 121     load_to_pciw_fifo_in,
 122     load_to_conf_in,
 123     same_read_out,
 124
 125         norm_access_to_config_out,
 126         read_completed_out,
 127         read_processing_out,
 128         target_abort_out,
 129         disconect_wo_data_out,
 130         disconect_w_data_out,
 131         pciw_fifo_full_out,
 132         pcir_fifo_data_err_out,
 133         wbw_fifo_empty_out,
 134         wbu_del_read_comp_pending_out,
 135
 136         // Delayed synchronizacion module signals
 137         req_out,
 138     done_out,
 139     in_progress_out,
 140         req_req_pending_in,
 141     req_comp_pending_in,
 142         addr_out,
 143     be_out,
 144     we_out,
 145     bc_out,
 146     burst_ok_out,
 147         strd_addr_in,
 148         strd_bc_in,
 149     status_in,
 150     comp_flush_in,
 151
 152         // FIFO signals
 153         pcir_fifo_renable_out,
 154         pcir_fifo_data_in,
 155         pcir_fifo_be_in,
 156         pcir_fifo_control_in,
 157         pcir_fifo_flush_out,
 158         pcir_fifo_almost_empty_in,
 159         pcir_fifo_empty_in,
 160         pciw_fifo_wenable_out,
 161         pciw_fifo_addr_data_out,
 162         pciw_fifo_cbe_out,
 163         pciw_fifo_control_out,
 164         pciw_fifo_three_left_in,
 165         pciw_fifo_two_left_in,
 166         pciw_fifo_almost_full_in,
 167         pciw_fifo_full_in,
 168         wbw_fifo_empty_in,
 169         wbu_del_read_comp_pending_in,
 170
 171         // Configuration space signals
 172         conf_addr_out,
 173         conf_data_out,
 174         conf_data_in,
 175         conf_be_out,
 176         conf_we_out,
 177         conf_re_out,
 178         mem_enable_in,
 179         io_enable_in,
 180         mem_io_addr_space0_in,
 181         mem_io_addr_space1_in,
 182         mem_io_addr_space2_in,
 183         mem_io_addr_space3_in,
 184         mem_io_addr_space4_in,
 185         mem_io_addr_space5_in,
 186         pre_fetch_en0_in,
 187         pre_fetch_en1_in,
 188         pre_fetch_en2_in,
 189         pre_fetch_en3_in,
 190         pre_fetch_en4_in,
 191         pre_fetch_en5_in,
 192         pci_base_addr0_in,
 193         pci_base_addr1_in,
 194         pci_base_addr2_in,
 195         pci_base_addr3_in,
 196         pci_base_addr4_in,
 197         pci_base_addr5_in,
 198         pci_addr_mask0_in,
 199         pci_addr_mask1_in,
 200         pci_addr_mask2_in,
 201         pci_addr_mask3_in,
 202         pci_addr_mask4_in,
 203         pci_addr_mask5_in,
 204         pci_tran_addr0_in,
 205         pci_tran_addr1_in,
 206         pci_tran_addr2_in,
 207         pci_tran_addr3_in,
 208         pci_tran_addr4_in,
 209         pci_tran_addr5_in,
 210         addr_tran_en0_in,
 211         addr_tran_en1_in,
 212         addr_tran_en2_in,
 213         addr_tran_en3_in,
 214         addr_tran_en4_in,
 215         addr_tran_en5_in
 216 ) ;
 217
 218 `ifdef HOST
 219     `ifdef NO_CNF_IMAGE
 220         parameter pci_ba0_width = `PCI_NUM_OF_DEC_ADDR_LINES ;
 221     `else
 222         parameter pci_ba0_width = 20    ;
 223     `endif
 224 `endif
 225
 226 `ifdef GUEST
 227     parameter pci_ba0_width = 20 ;
 228 `endif
 229
 230 parameter pci_ba1_5_width = `PCI_NUM_OF_DEC_ADDR_LINES ;
 231
 232 /*==================================================================================================================
 233 System inputs.
 234 ==================================================================================================================*/
 235 // PCI side clock and reset
 236 input   clk_in,
 237         reset_in ;
 238
 239
 240 /*==================================================================================================================
 241 Side of the PCI Target state machine
 242 ==================================================================================================================*/
 243 // Data, byte enables, bus commands and address ports
 244 input   [31:0]  address_in ;            // current request address input - registered
 245 output          addr_claim_out ;        // current request address claim output
 246 input   [3:0]   bc_in ;                         // current request bus command input - registered
 247 input                   bc0_in ;                        // current cycle RW signal
 248 output  [31:0]  data_out ;                      // for read operations - current dataphase data output
 249 input   [31:0]  data_in ;                       // for write operations - current request data input - registered
 250 input   [3:0]   be_in ;                         // current dataphase byte enable inputs - registered
 251 input   [3:0]   next_be_in ;                    // next dataphase byte enable inputs - NOT registered
 252 // Port connection control signals from PCI FSM
 253 input           req_in ;                // Read is requested to WB master from PCI side
 254 input           rdy_in ;                // DATA / ADDRESS selection from PCI side when read or write - registered
 255 input                   addr_phase_in ;         // Indicates address phase and also fast-back-to-back address phase - registered
 256 input                   bckp_devsel_in ;        // DEVSEL input (which is registered) equivalent
 257 input                   bckp_trdy_in ;          // TRDY input (which is registered) equivalent
 258 input                   bckp_stop_in ;          // STOP input (which is registered) equivalent
 259 input               last_reg_in ;               // Indicates last data phase - registered
 260 input                   frame_reg_in ;          // FRAME input signal - registered
 261 input               fetch_pcir_fifo_in ;// Read enable for PCIR_FIFO when when read is finishen on WB side
 262 input               load_medium_reg_in ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
 263 input               sel_fifo_mreg_in ;  // Read data selection between PCIR_FIFO and medium register
 264 input               sel_conf_fifo_in ;  // Read data selection between Configuration registers and "FIFO"
 265 input               load_to_pciw_fifo_in ;// Write enable to PCIW_FIFO
 266 input               load_to_conf_in ;   // Write enable to Configuration space registers
 267
 268
 269 /*==================================================================================================================
 270 Status outputs to PCI side (FSM)
 271 ==================================================================================================================*/
 272 output                  same_read_out ;                         // Indicates the same read request (important when read is finished on WB side)
 273 output                  norm_access_to_config_out ;     // Indicates the access to Configuration space with MEMORY commands
 274 output                  read_completed_out ;            // Indicates that read request is completed on WB side
 275 output                  read_processing_out ;           // Indicates that read request is processing on WB side
 276 output                  target_abort_out ;                      // Indicates target abort termination
 277 output                  disconect_wo_data_out ;         // Indicates disconnect without data termination
 278 output                  disconect_w_data_out ;          // Indicates disconnect with data termination
 279 output                  pciw_fifo_full_out ;            // Indicates that write PCIW_FIFO is full
 280 output                  pcir_fifo_data_err_out ;        // Indicates data error on current data read from PCIR_FIFO
 281 output                  wbw_fifo_empty_out ;            // Indicates that WB SLAVE has no data to be written to PCI bus
 282 output                  wbu_del_read_comp_pending_out ; // Indicates that WB Unit has a delayed read poending!
 283
 284 /*==================================================================================================================
 285 Read request interface through Delayed sinchronization module to WB Master
 286 ==================================================================================================================*/
 287 // request, completion, done and progress indicator outputs for delayed_sync module where they are synchronized
 288 output                  req_out,                // request qualifier - when 1 it indicates that valid data is provided on outputs
 289                         done_out,               // done output - when 1 indicates that PCI Target has completed a cycle on its bus
 290                         in_progress_out ;       // out progress indicator - indicates that current completion is in progress on
 291                                                                         //   PCI Target side
 292 // pending indication inputs - PCI Target side must know about requests and completions
 293 input                   req_req_pending_in ;    // request pending input for PCI Target side
 294 input                   req_comp_pending_in ;   // completion pending input for PCI Target side - it indicates when completion
 295                                                                                 //   is ready for completing on PCI Target bus
 296 // various data outputs - PCI Target sets address, bus command, byte enables, write enable and burst
 297 output  [31:0]  addr_out ;   // address bus output
 298 output  [3:0]   be_out ;     // byte enable output
 299 output          we_out ;     // write enable output - read/write request indication 1 = write request / 0 = read request
 300 output  [3:0]   bc_out ;     // bus command output
 301 output                  burst_ok_out ;  // pre-fetch enable & burst read - qualifies pre-fetch for access to current image space
 302
 303 // completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion
 304 input   [31:0]  strd_addr_in ;  // Stored requested read access address
 305 input   [3:0]   strd_bc_in ;    // Stored requested read access bus command
 306 input                   status_in ;     // Error status reported - NOT USED because FIFO control bits determin data error status
 307 input               comp_flush_in ;     // If completition counter (2^16 clk periods) has expired, PCIR_FIFO must flush data
 308
 309
 310 /*==================================================================================================================
 311 PCIR_PCIW_FIFO signals from pci side
 312 ==================================================================================================================*/
 313 // PCIR_FIFO control signals used for fetching data from PCIR_FIFO
 314 output                  pcir_fifo_renable_out ;                 // read enable output to PCIR_FIFO
 315 input   [31:0]  pcir_fifo_data_in ;                             // data input from PCIR_FIFO
 316 input   [3:0]   pcir_fifo_be_in ;                               // byte enable input from PCIR_FIFO
 317 input   [3:0]   pcir_fifo_control_in ;                  // control signals input from PCIR_FIFO
 318 output                  pcir_fifo_flush_out ;                   // flush PCIR_FIFO
 319 input                   pcir_fifo_almost_empty_in ;             // almost empty indicator from PCIR_FIFO
 320 input                   pcir_fifo_empty_in ;                    // empty indicator
 321
 322 // PCIW_FIFO control signals used for sinking data into PCIW_FIFO and status monitoring
 323 output                  pciw_fifo_wenable_out ;         // write enable output to PCIW_FIFO
 324 wire            pciw_fifo_wenable ; // not registered we
 325 output  [31:0]  pciw_fifo_addr_data_out ;       // address / data output signals to PCIW_FIFO
 326 output  [3:0]   pciw_fifo_cbe_out ;                     // command / byte enable signals to PCIW_FIFO
 327 output  [3:0]   pciw_fifo_control_out ;         // control signals to PCIW_FIFO
 328 input           pciw_fifo_three_left_in ;       // three data spaces left in PCIW_FIFO
 329 input           pciw_fifo_two_left_in ;         // two data spaces left in PCIW_FIFO
 330 input                   pciw_fifo_almost_full_in ;      // almost full indicator from PCIW_FIFO
 331 input                   pciw_fifo_full_in ;                     // full indicator from PCIW_FIFO
 332
 333 // WBW_FIFO empy control signal used when delayed read is complete in PCIR_FIFO
 334 input                   wbw_fifo_empty_in ;                     // empty indicator from WBW_FIFO
 335 input                   wbu_del_read_comp_pending_in ; // delayed read pending indicator from WB Unit
 336
 337
 338 /*==================================================================================================================
 339 Configuration space signals - from and to registers
 340 ==================================================================================================================*/
 341 // BUS for reading and writing to configuration space registers
 342 output  [11:0]  conf_addr_out ; // address to configuration space when there is access to it
 343 output  [31:0]  conf_data_out ; // data to configuration space - for writing to registers
 344 input   [31:0]  conf_data_in ;  // data from configuration space - for reading from registers
 345 output  [3:0]   conf_be_out ;   // byte enables used for correct writing to configuration space
 346 output                  conf_we_out ;   // write enable control signal - 1 for writing / 0 for nothing
 347 output                  conf_re_out ;   // read enable control signal - 1 for reading / 0 for nothing
 348
 349 // Inputs for image control registers
 350 input                   mem_enable_in ; // allowed access to memory mapped image
 351 input                   io_enable_in ;  // allowed access to io mapped image
 352
 353 // Inputs needed for determining if image is assigned to memory or io space with pre-fetch and address translation
 354 input                   mem_io_addr_space0_in ; // bit-0 in pci_base_addr0 register
 355 input                   mem_io_addr_space1_in ; // bit-0 in pci_base_addr1 register
 356 input                   mem_io_addr_space2_in ; // bit-0 in pci_base_addr2 register
 357 input                   mem_io_addr_space3_in ; // bit-0 in pci_base_addr3 register
 358 input                   mem_io_addr_space4_in ; // bit-0 in pci_base_addr4 register
 359 input                   mem_io_addr_space5_in ; // bit-0 in pci_base_addr5 register
 360 input                   pre_fetch_en0_in ;      // bit-1 in pci_image_ctr0 register
 361 input                   pre_fetch_en1_in ;      // bit-1 in pci_image_ctr1 register
 362 input                   pre_fetch_en2_in ;      // bit-1 in pci_image_ctr2 register
 363 input                   pre_fetch_en3_in ;      // bit-1 in pci_image_ctr3 register
 364 input                   pre_fetch_en4_in ;      // bit-1 in pci_image_ctr4 register
 365 input                   pre_fetch_en5_in ;      // bit-1 in pci_image_ctr5 register
 366
 367 // Input from image registers - register values needed for decoder to work properly
 368 input   [pci_ba0_width   - 1:0] pci_base_addr0_in ;     // base address from base address register
 369 input   [pci_ba1_5_width - 1:0] pci_base_addr1_in ; // base address from base address register
 370 input   [pci_ba1_5_width - 1:0] pci_base_addr2_in ; // base address from base address register
 371 input   [pci_ba1_5_width - 1:0] pci_base_addr3_in ; // base address from base address register
 372 input   [pci_ba1_5_width - 1:0] pci_base_addr4_in ; // base address from base address register
 373 input   [pci_ba1_5_width - 1:0] pci_base_addr5_in ; // base address from base address register
 374 input   [pci_ba1_5_width - 1:0] pci_addr_mask0_in ; // masking of base address from address mask register
 375 input   [pci_ba1_5_width - 1:0] pci_addr_mask1_in ; // masking of base address from address mask register
 376 input   [pci_ba1_5_width - 1:0] pci_addr_mask2_in ; // masking of base address from address mask register
 377 input   [pci_ba1_5_width - 1:0] pci_addr_mask3_in ; // masking of base address from address mask register
 378 input   [pci_ba1_5_width - 1:0] pci_addr_mask4_in ; // masking of base address from address mask register
 379 input   [pci_ba1_5_width - 1:0] pci_addr_mask5_in ; // masking of base address from address mask register
 380 input   [pci_ba1_5_width - 1:0] pci_tran_addr0_in ; // translation address from address translation register
 381 input   [pci_ba1_5_width - 1:0] pci_tran_addr1_in ; // translation address from address translation register
 382 input   [pci_ba1_5_width - 1:0] pci_tran_addr2_in ; // translation address from address translation register
 383 input   [pci_ba1_5_width - 1:0] pci_tran_addr3_in ; // translation address from address translation register
 384 input   [pci_ba1_5_width - 1:0] pci_tran_addr4_in ; // translation address from address translation register
 385 input   [pci_ba1_5_width - 1:0] pci_tran_addr5_in ; // translation address from address translation register
 386
 387 input                   addr_tran_en0_in ;      // address translation enable bit
 388 input                   addr_tran_en1_in ;      // address translation enable bit
 389 input                   addr_tran_en2_in ;      // address translation enable bit
 390 input                   addr_tran_en3_in ;      // address translation enable bit
 391 input                   addr_tran_en4_in ;      // address translation enable bit
 392 input                   addr_tran_en5_in ;      // address translation enable bit
 393
 394 /*==================================================================================================================
 395 END of input / output PORT DEFINITONS !!!
 396 ==================================================================================================================*/
 397
 398 // address output from address multiplexer
 399 reg             [31:0]  address ;
 400 // prefetch enable for access to selected image space
 401 reg                             pre_fetch_en ;
 402
 403 // Input addresses and image hits from address decoders - addresses are multiplexed to address
 404 `ifdef                  HOST
 405         `ifdef          NO_CNF_IMAGE
 406                 `ifdef  PCI_IMAGE0      // if PCI bridge is HOST and IMAGE0 is assigned as general image space
 407 wire                    hit0_in ;
 408 wire    [31:0]  address0_in ;
 409 wire                    pre_fetch_en0 = pre_fetch_en0_in ;
 410                 `else
 411 wire                    hit0_in         = 1'b0 ;
 412 wire    [31:0]  address0_in     = 32'h0 ;
 413 wire                    pre_fetch_en0 = 1'b0 ;
 414                 `endif
 415         `else
 416 wire                    hit0_in ;
 417 wire    [31:0]  address0_in ;
 418 wire                    pre_fetch_en0 = pre_fetch_en0_in ;
 419         `endif
 420 `else // GUEST
 421 wire                    hit0_in ;
 422 wire    [31:0]  address0_in ;
 423 wire                    pre_fetch_en0 = pre_fetch_en0_in ;
 424 `endif
 425
 426 wire                    hit1_in ;
 427 wire    [31:0]  address1_in ;
 428 wire                    pre_fetch_en1 = pre_fetch_en1_in ;
 429
 430 `ifdef          PCI_IMAGE2
 431 wire                    hit2_in ;
 432 wire    [31:0]  address2_in ;
 433 wire                    pre_fetch_en2 = pre_fetch_en2_in ;
 434 `else
 435 wire                    hit2_in         = 1'b0 ;
 436 wire    [31:0]  address2_in     = 32'h0 ;
 437 wire                    pre_fetch_en2 = 1'b0 ;
 438 `endif
 439
 440 `ifdef          PCI_IMAGE3
 441 wire                    hit3_in ;
 442 wire    [31:0]  address3_in ;
 443 wire                    pre_fetch_en3 = pre_fetch_en3_in ;
 444 `else
 445 wire                    hit3_in         = 1'b0 ;
 446 wire    [31:0]  address3_in     = 32'h0 ;
 447 wire                    pre_fetch_en3 = 1'b0 ;
 448 `endif
 449
 450 `ifdef          PCI_IMAGE4
 451 wire                    hit4_in ;
 452 wire    [31:0]  address4_in ;
 453 wire                    pre_fetch_en4 = pre_fetch_en4_in ;
 454 `else
 455 wire                    hit4_in         = 1'b0 ;
 456 wire    [31:0]  address4_in     = 32'h0 ;
 457 wire                    pre_fetch_en4 = 1'b0 ;
 458 `endif
 459
 460 `ifdef          PCI_IMAGE5
 461 wire                    hit5_in ;
 462 wire    [31:0]  address5_in ;
 463 wire                    pre_fetch_en5 = pre_fetch_en5_in ;
 464 `else
 465 wire                    hit5_in         = 1'b0 ;
 466 wire    [31:0]  address5_in     = 32'h0 ;
 467 wire                    pre_fetch_en5 = 1'b0 ;
 468 `endif
 469
 470 // Include address decoders
 471 `ifdef                  HOST
 472         `ifdef          NO_CNF_IMAGE
 473                 `ifdef  PCI_IMAGE0      // if PCI bridge is HOST and IMAGE0 is assigned as general image space
 474         pci_pci_decoder   #(pci_ba0_width) decoder0
 475                                    (.hit                        (hit0_in),
 476                                         .addr_out               (address0_in),
 477                                         .addr_in                (address_in),
 478                                         .bc_in                  (bc_in),
 479                                         .base_addr              (pci_base_addr0_in),
 480                                         .mask_addr              (pci_addr_mask0_in),
 481                                         .tran_addr              (pci_tran_addr0_in),
 482                                         .at_en                  (addr_tran_en0_in),
 483                                         .mem_io_space   (mem_io_addr_space0_in),
 484                                         .mem_en                 (mem_enable_in),
 485                                         .io_en                  (io_enable_in)
 486                                         ) ;
 487                 `endif
 488         `else
 489         pci_pci_decoder   #(pci_ba0_width) decoder0
 490                                    (.hit                        (hit0_in),
 491                                         .addr_out               (address0_in),
 492                                         .addr_in                (address_in),
 493                                         .bc_in                  (bc_in),
 494                                         .base_addr              (pci_base_addr0_in),
 495                                         .mask_addr              ({pci_ba0_width{1'b1}}),
 496                                         .tran_addr              ({pci_ba0_width{1'b0}}),
 497                                         .at_en                  (1'b0),
 498                                         .mem_io_space   (1'b0),
 499                                         .mem_en                 (mem_enable_in),
 500                                         .io_en                  (1'b0)
 501                                         ) ;
 502         `endif
 503 `else // GUEST
 504         pci_pci_decoder   #(pci_ba0_width) decoder0
 505                                    (.hit                        (hit0_in),
 506                                         .addr_out               (address0_in),
 507                                         .addr_in                (address_in),
 508                                         .bc_in                  (bc_in),
 509                                         .base_addr              (pci_base_addr0_in),
 510                                         .mask_addr              ({pci_ba0_width{1'b1}}),
 511                                         .tran_addr              ({pci_ba0_width{1'b0}}),
 512                                         .at_en                  (1'b0),
 513                                         .mem_io_space   (1'b0),
 514                                         .mem_en                 (mem_enable_in),
 515                                         .io_en                  (1'b0)
 516                                         ) ;
 517 `endif
 518         pci_pci_decoder   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder1
 519                                    (.hit                        (hit1_in),
 520                                         .addr_out               (address1_in),
 521                                         .addr_in                (address_in),
 522                                         .bc_in                  (bc_in),
 523                                         .base_addr              (pci_base_addr1_in),
 524                                         .mask_addr              (pci_addr_mask1_in),
 525                                         .tran_addr              (pci_tran_addr1_in),
 526                                         .at_en                  (addr_tran_en1_in),
 527                                         .mem_io_space   (mem_io_addr_space1_in),
 528                                         .mem_en                 (mem_enable_in),
 529                                         .io_en                  (io_enable_in)
 530                                         ) ;
 531 `ifdef          PCI_IMAGE2
 532         pci_pci_decoder   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
 533                                    (.hit                        (hit2_in),
 534                                         .addr_out               (address2_in),
 535                                         .addr_in                (address_in),
 536                                         .bc_in                  (bc_in),
 537                                         .base_addr              (pci_base_addr2_in),
 538                                         .mask_addr              (pci_addr_mask2_in),
 539                                         .tran_addr              (pci_tran_addr2_in),
 540                                         .at_en                  (addr_tran_en2_in),
 541                                         .mem_io_space   (mem_io_addr_space2_in),
 542                                         .mem_en                 (mem_enable_in),
 543                                         .io_en                  (io_enable_in)
 544                                         ) ;
 545 `endif
 546 `ifdef          PCI_IMAGE3
 547         pci_pci_decoder   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
 548                                    (.hit                        (hit3_in),
 549                                         .addr_out               (address3_in),
 550                                         .addr_in                (address_in),
 551                                         .bc_in                  (bc_in),
 552                                         .base_addr              (pci_base_addr3_in),
 553                                         .mask_addr              (pci_addr_mask3_in),
 554                                         .tran_addr              (pci_tran_addr3_in),
 555                                         .at_en                  (addr_tran_en3_in),
 556                                         .mem_io_space   (mem_io_addr_space3_in),
 557                                         .mem_en                 (mem_enable_in),
 558                                         .io_en                  (io_enable_in)
 559                                         ) ;
 560 `endif
 561 `ifdef          PCI_IMAGE4
 562         pci_pci_decoder   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
 563                                    (.hit                        (hit4_in),
 564                                         .addr_out               (address4_in),
 565                                         .addr_in                (address_in),
 566                                         .bc_in                  (bc_in),
 567                                         .base_addr              (pci_base_addr4_in),
 568                                         .mask_addr              (pci_addr_mask4_in),
 569                                         .tran_addr              (pci_tran_addr4_in),
 570                                         .at_en                  (addr_tran_en4_in),
 571                                         .mem_io_space   (mem_io_addr_space4_in),
 572                                         .mem_en                 (mem_enable_in),
 573                                         .io_en                  (io_enable_in)
 574                                         ) ;
 575 `endif
 576 `ifdef          PCI_IMAGE5
 577         pci_pci_decoder   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder5
 578                                    (.hit                        (hit5_in),
 579                                         .addr_out               (address5_in),
 580                                         .addr_in                (address_in),
 581                                         .bc_in                  (bc_in),
 582                                         .base_addr              (pci_base_addr5_in),
 583                                         .mask_addr              (pci_addr_mask5_in),
 584                                         .tran_addr              (pci_tran_addr5_in),
 585                                         .at_en                  (addr_tran_en5_in),
 586                                         .mem_io_space   (mem_io_addr_space5_in),
 587                                         .mem_en                 (mem_enable_in),
 588                                         .io_en                  (io_enable_in)
 589                                         ) ;
 590 `endif
 591
 592 // Internal signals for image hit determination
 593 reg                             addr_claim ;// address claim signal is asinchronous set for addr_claim_out signal to PCI Target SM
 594
 595 // Determining if image 0 is assigned to configuration space or as normal pci to wb access!
 596 //   if normal access is allowed to configuration space, then hit0 is hit0_conf
 597 `ifdef          HOST
 598         `ifdef  NO_CNF_IMAGE
 599                         parameter       hit0_conf = 1'b0 ;
 600         `else
 601                         parameter       hit0_conf = 1'b1 ;      // if normal access is allowed to configuration space, then hit0 is hit0_conf
 602         `endif
 603 `else // GUEST
 604                         parameter       hit0_conf = 1'b1 ;      // if normal access is allowed to configuration space, then hit0 is hit0_conf
 605 `endif
 606
 607 // Logic with address mux, determining if address is still in the same image space and if it is prefetced or not
 608 always@(hit5_in or     hit4_in or     hit3_in or     hit2_in or     hit1_in or     hit0_in or
 609                 address5_in or address4_in or address3_in or address2_in or address1_in or address0_in or
 610                 pre_fetch_en5 or
 611                 pre_fetch_en4 or
 612                 pre_fetch_en3 or
 613                 pre_fetch_en2 or
 614                 pre_fetch_en1 or
 615                 pre_fetch_en0
 616                 )
 617 begin
 618         addr_claim <= (hit5_in || hit4_in) || (hit3_in || hit2_in || hit1_in || hit0_in) ;
 619         case ({hit5_in, hit4_in, hit3_in, hit2_in, hit0_in})
 620         5'b10000 :
 621         begin
 622                 address <= address5_in ;
 623                 pre_fetch_en <= pre_fetch_en5 ;
 624         end
 625         5'b01000 :
 626         begin
 627                 address <= address4_in ;
 628                 pre_fetch_en <= pre_fetch_en4 ;
 629         end
 630         5'b00100 :
 631         begin
 632                 address <= address3_in ;
 633                 pre_fetch_en <= pre_fetch_en3 ;
 634         end
 635         5'b00010 :
 636         begin
 637                 address <= address2_in ;
 638                 pre_fetch_en <= pre_fetch_en2 ;
 639         end
 640         5'b00001 :
 641         begin
 642                 address <= address0_in ;
 643                 pre_fetch_en <= pre_fetch_en0 ;
 644         end
 645         default : // IMAGE 1 is always included into PCI bridge
 646         begin
 647                 address <= address1_in ;
 648                 pre_fetch_en <= pre_fetch_en1 ;
 649         end
 650         endcase
 651 end
 652
 653 // Address claim output to PCI Target SM
 654 assign  addr_claim_out = addr_claim ;
 655
 656 reg             [31:0]  norm_address ;          // stored normal address (decoded and translated) for access to WB
 657 reg                             norm_prf_en ;           // stored pre-fetch enable
 658 reg             [3:0]   norm_bc ;                       // stored bus-command
 659 reg                             same_read_reg ;         // stored SAME_READ information
 660 reg                             target_rd ;             // delayed registered TRDY output equivalent signal
 661
 662 always@(posedge clk_in or posedge reset_in)
 663 begin
 664     if (reset_in)
 665         begin
 666                 norm_address <= #`FF_DELAY 32'h0000_0000 ;
 667                 norm_prf_en <= #`FF_DELAY 1'b0 ;
 668                 norm_bc <= #`FF_DELAY 4'h0 ;
 669                 same_read_reg <= #`FF_DELAY 1'b0 ;
 670         end
 671         else
 672         begin
 673                 if (addr_phase_in)
 674                 begin
 675                         norm_address <= #`FF_DELAY address ;
 676                         norm_prf_en <= #`FF_DELAY pre_fetch_en ;
 677                         norm_bc <= #`FF_DELAY bc_in ;
 678                         same_read_reg <= #`FF_DELAY same_read_out ;
 679                 end
 680         end
 681 end
 682
 683 `ifdef          HOST
 684   `ifdef        NO_CNF_IMAGE
 685                         reg              [1:0]  strd_address ;          // stored INPUT address for accessing Configuration space registers
 686   `else
 687                         reg             [11:0]  strd_address ;          // stored INPUT address for accessing Configuration space registers
 688   `endif
 689 `else
 690                         reg             [11:0]  strd_address ;          // stored INPUT address for accessing Configuration space registers
 691 `endif
 692 always@(posedge clk_in or posedge reset_in)
 693 begin
 694     if (reset_in)
 695         begin
 696                 strd_address <= #`FF_DELAY 0 ;
 697         end
 698         else
 699         begin
 700                 if (addr_phase_in)
 701                 begin
 702 `ifdef          HOST
 703   `ifdef        NO_CNF_IMAGE
 704                         strd_address <= #`FF_DELAY address_in[1:0] ;
 705   `else
 706                         strd_address <= #`FF_DELAY address_in[11:0] ;
 707   `endif
 708 `else
 709                         strd_address <= #`FF_DELAY address_in[11:0] ;
 710 `endif
 711                 end
 712         end
 713 end
 714
 715 always@(posedge clk_in or posedge reset_in)
 716 begin
 717     if (reset_in)
 718         begin
 719                 target_rd               <= #`FF_DELAY 1'b0 ;
 720         end
 721         else
 722         begin
 723                 if (same_read_reg && !bckp_trdy_in)
 724                         target_rd       <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
 725                 else if (same_read_reg && bckp_devsel_in && !bckp_stop_in)
 726                         target_rd       <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
 727                 else if ((!same_read_reg) || (last_reg_in && target_rd))
 728                         target_rd       <= #`FF_DELAY 1'b0 ;// Signal indicates when target ready is deaserted on PCI bus
 729         end
 730 end
 731 // '1' indicates asserted TRDY signal when same read operation is performed
 732 wire    target_rd_completed     = target_rd ;
 733
 734 reg                             same_read_request ;
 735
 736 // When delayed read is completed on WB, addres and bc must be compered, if there is the same read request
 737 always@(address or strd_addr_in or bc_in or strd_bc_in)
 738 begin
 739         if ((address == strd_addr_in) & (bc_in == strd_bc_in))
 740                 same_read_request <= 1'b1 ;
 741         else
 742                 same_read_request <= 1'b0 ;
 743 end
 744
 745 assign  same_read_out = (same_read_request) ; // && ~pcir_fifo_empty_in) ;
 746
 747 // Signals for byte enable checking
 748 reg                             addr_burst_ok ;
 749 reg                             io_be_ok ;
 750
 751 // Byte enable checking for IO, MEMORY and CONFIGURATION spaces - be_in is active low!
 752 always@(strd_address or be_in)
 753 begin
 754         case (strd_address[1:0])
 755         2'b11 :
 756         begin
 757                 addr_burst_ok <= 1'b0 ;
 758                 io_be_ok <= (be_in[2] && be_in[1] && be_in[0]) ; // only be3 can be active
 759         end
 760         2'b10 :
 761         begin
 762                 addr_burst_ok <= 1'b0 ;
 763                 io_be_ok <= (~be_in[2] && be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
 764         end
 765         2'b01 :
 766         begin
 767                 addr_burst_ok <= 1'b0 ;
 768                 io_be_ok <= (~be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
 769         end
 770         default :       // 2'b00
 771         begin
 772                 addr_burst_ok <= 1'b1 ;
 773                 io_be_ok <= (~be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
 774         end
 775         endcase
 776 end
 777
 778 wire calc_target_abort = (norm_bc[3:1] == `BC_IO_RW) ? !io_be_ok : 1'b0 ;
 779
 780 wire [3:0]      pcir_fifo_control_input = pcir_fifo_empty_in ? 4'h0 : pcir_fifo_control_in ;
 781
 782 // Medium registers for data and control busses from PCIR_FIFO
 783 reg             [31:0]  pcir_fifo_data_reg ;
 784 reg             [3:0]   pcir_fifo_ctrl_reg ;
 785
 786 always@(posedge clk_in or posedge reset_in)
 787 begin
 788     if (reset_in)
 789     begin
 790         pcir_fifo_data_reg <= #`FF_DELAY 32'h0000_0000 ;
 791         pcir_fifo_ctrl_reg <=  #`FF_DELAY 4'h0 ;
 792     end
 793     else
 794     begin
 795         if (load_medium_reg_in)
 796         begin
 797                 pcir_fifo_data_reg <= #`FF_DELAY pcir_fifo_data_in ;
 798                 pcir_fifo_ctrl_reg <= #`FF_DELAY pcir_fifo_control_input ;
 799         end
 800     end
 801 end
 802
 803 // when disconnect is signalled, the next data written to fifo will be the last
 804 // also when this happens, disconnect must stay asserted until last data is written to the fifo
 805 reg keep_desconnect_wo_data_set ;
 806
 807 // selecting "fifo data" from medium registers or from PCIR_FIFO
 808 wire [31:0]     pcir_fifo_data = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_data_in : pcir_fifo_data_reg ;
 809 wire [3:0]      pcir_fifo_ctrl = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_control_input : pcir_fifo_ctrl_reg ;
 810
 811 // signal assignments to PCI Target FSM
 812 assign  read_completed_out = req_comp_pending_in ; // completion pending input for requesting side of the bridge
 813 assign  read_processing_out = req_req_pending_in ; // request pending input for requesting side
 814   // when '1', the bus command is IO command - not supported commands are checked in pci_decoder modules
 815   wire  io_memory_bus_command = !norm_bc[3] && !norm_bc[2] ;
 816 assign  disconect_wo_data_out = (
 817         ((/*pcir_fifo_ctrl[`LAST_CTRL_BIT] ||*/ pcir_fifo_empty_in || ~burst_ok_out/*addr_burst_ok*/ || io_memory_bus_command) &&
 818                 ~bc0_in && ~frame_reg_in) ||
 819         ((pciw_fifo_full_in || pciw_fifo_almost_full_in || keep_desconnect_wo_data_set || pciw_fifo_two_left_in ||
 820                 (pciw_fifo_three_left_in && pciw_fifo_wenable) || ~addr_burst_ok || io_memory_bus_command) &&
 821                 bc0_in && ~frame_reg_in)
 822                                                                 ) ;
 823 assign  disconect_w_data_out =  (
 824         ( burst_ok_out  && !io_memory_bus_command && ~bc0_in ) ||
 825         ( addr_burst_ok && !io_memory_bus_command && bc0_in )
 826                                                                 ) ;
 827 assign  target_abort_out = ( ~addr_phase_in && calc_target_abort ) ;
 828
 829 `ifdef          HOST
 830         `ifdef  NO_CNF_IMAGE
 831                         // signal assignments to PCI Target FSM
 832                         assign  norm_access_to_config_out = 1'b0 ;
 833                         // control signal assignments to read request sinchronization module
 834                         assign  done_out =  (target_rd_completed && last_reg_in) ;
 835                         assign  in_progress_out = (same_read_reg && ~bckp_trdy_in) ;
 836                         // signal used for PCIR_FIFO flush (with comp_flush_in signal)
 837                         wire    pcir_fifo_flush = (target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
 838         `else
 839                         // signal assignments to PCI Target FSM
 840                         assign  norm_access_to_config_out = (hit0_in && hit0_conf) ;
 841                         // control signal assignments to read request sinchronization module
 842                         assign  done_out =  (~sel_conf_fifo_in && target_rd_completed && last_reg_in) ;
 843                         assign  in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ;
 844                         // signal used for PCIR_FIFO flush (with comp_flush_in signal)
 845                         wire    pcir_fifo_flush = (~sel_conf_fifo_in && target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
 846         `endif
 847 `else
 848                         // signal assignments to PCI Target FSM
 849                         assign  norm_access_to_config_out = (hit0_in && hit0_conf) ;
 850                         // control signal assignments to read request sinchronization module
 851                         assign  done_out =  (~sel_conf_fifo_in && target_rd_completed && last_reg_in) ;
 852                         assign  in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ;
 853                         // signal used for PCIR_FIFO flush (with comp_flush_in signal)
 854                         wire    pcir_fifo_flush = (~sel_conf_fifo_in && target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
 855 `endif
 856
 857 // flush signal for PCIR_FIFO must be registered, since it asinchronously resets some status registers
 858 wire            pcir_fifo_flush_reg ;
 859 pci_async_reset_flop async_reset_as_pcir_flush
 860 (
 861     .data_in              (comp_flush_in || pcir_fifo_flush),
 862     .clk_in               (clk_in),
 863     .async_reset_data_out (pcir_fifo_flush_reg),
 864     .reset_in                     (reset_in)
 865 ) ;
 866
 867 always@(posedge clk_in or posedge reset_in)
 868 begin
 869     if (reset_in)
 870         keep_desconnect_wo_data_set     <= #1 1'b0 ;
 871     else if (keep_desconnect_wo_data_set && pciw_fifo_wenable)
 872         keep_desconnect_wo_data_set     <= #1 1'b0 ;
 873     else if (pciw_fifo_wenable && disconect_wo_data_out)
 874         keep_desconnect_wo_data_set     <= #1 1'b1 ;
 875 end
 876
 877
 878 // signal assignments from fifo to PCI Target FSM
 879 assign  wbw_fifo_empty_out = wbw_fifo_empty_in ;
 880 assign  wbu_del_read_comp_pending_out = wbu_del_read_comp_pending_in ;
 881 assign  pciw_fifo_full_out = (pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in || pciw_fifo_three_left_in) ;
 882 assign  pcir_fifo_data_err_out = pcir_fifo_ctrl[`DATA_ERROR_CTRL_BIT] && !sel_conf_fifo_in ;
 883 // signal assignments to PCIR FIFO fifo
 884 assign  pcir_fifo_flush_out                                                     = pcir_fifo_flush_reg ;
 885 assign  pcir_fifo_renable_out                                           = fetch_pcir_fifo_in && !pcir_fifo_empty_in ;
 886
 887 // signal assignments to PCIW FIFO
 888 reg          pciw_fifo_wenable_out;
 889 assign       pciw_fifo_wenable = load_to_pciw_fifo_in ;
 890 reg   [3:0]  pciw_fifo_control_out;
 891 reg  [31:0]  pciw_fifo_addr_data_out;
 892 reg   [3:0]  pciw_fifo_cbe_out;
 893 always@(posedge clk_in or posedge reset_in)
 894 begin
 895     if (reset_in)
 896     begin
 897         pciw_fifo_wenable_out   <= #1 1'b0;
 898         pciw_fifo_control_out   <= #1 4'h0;
 899         // data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits
 900         pciw_fifo_addr_data_out <= #1 32'h0;
 901         pciw_fifo_cbe_out       <= #1 4'h0;
 902     end
 903     else
 904     begin
 905         pciw_fifo_wenable_out                       <= #1 load_to_pciw_fifo_in ;
 906         pciw_fifo_control_out[`ADDR_CTRL_BIT]       <= #1 ~rdy_in ;
 907         pciw_fifo_control_out[`BURST_BIT]           <= #1 rdy_in ? ~frame_reg_in : 1'b0 ;
 908         // if '1' then next burst BE is not equat to current one => burst will be chopped into single transfers
 909         pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT] <= #1 rdy_in && (next_be_in != be_in) && ~bckp_trdy_in; // valid comp.
 910         pciw_fifo_control_out[`LAST_CTRL_BIT]       <= #1 rdy_in && (frame_reg_in || (bckp_trdy_in && ~bckp_stop_in));
 911         // data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits
 912         pciw_fifo_addr_data_out                     <= #1 rdy_in ? data_in : {norm_address[31:2],
 913                                                                           norm_address[1] && io_memory_bus_command,
 914                                                                           norm_address[0] && io_memory_bus_command} ;
 915         pciw_fifo_cbe_out                           <= #1 rdy_in ? be_in : norm_bc ;
 916     end
 917 end
 918
 919 `ifdef          HOST
 920         `ifdef  NO_CNF_IMAGE
 921                         // data and address outputs assignments to PCI Target FSM
 922                         assign  data_out = pcir_fifo_data ;
 923         `else
 924                         // data and address outputs assignments to PCI Target FSM
 925                         assign  data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ;
 926         `endif
 927 `else
 928                         // data and address outputs assignments to PCI Target FSM
 929                         assign  data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ;
 930 `endif
 931
 932 // data and address outputs assignments to read request sinchronization module
 933 assign  req_out = req_in ;
 934         // this address is stored in delayed_sync module and is connected back as strd_addr_in
 935 assign  addr_out = norm_address[31:0] ; // correction of 2 LSBits is done in wb_master module, original address must be saved
 936 assign  be_out = be_in ;
 937 assign  we_out = 1'b0 ;
 938 assign  bc_out = norm_bc ;
 939 // burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
 940 //   (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00)
 941 assign  burst_ok_out = (norm_bc[3] && addr_burst_ok) || (norm_bc[2] && norm_prf_en && addr_burst_ok) ;
 942 // data and address outputs assignments to Configuration space
 943 `ifdef          HOST
 944         `ifdef  NO_CNF_IMAGE
 945                         assign  conf_data_out   = 32'h0 ;
 946                         assign  conf_addr_out   = 12'h0 ;
 947                         assign  conf_be_out             = 4'b0 ;
 948                         assign  conf_we_out             = 1'h0 ;
 949         `else
 950                         assign  conf_data_out   = data_in ;
 951                         assign  conf_addr_out   = strd_address[11:0] ;
 952                         assign  conf_be_out             = be_in ;
 953                         assign  conf_we_out             = load_to_conf_in ;
 954         `endif
 955 `else
 956                         assign  conf_data_out   = data_in ;
 957                         assign  conf_addr_out   = strd_address[11:0] ;
 958                         assign  conf_be_out             = be_in ;
 959                         assign  conf_we_out             = load_to_conf_in ;
 960 `endif
 961 // NOT USED NOW, SONCE READ IS ASYNCHRONOUS
 962 //assign        conf_re_out = fetch_conf_in ;
 963 assign  conf_re_out = 1'b0 ;
 964
 965 endmodule