cvs.zerfleddert.de Git - raggedstone/blob - heartbeat/source/pcipargen.v

   1 //
   2 //                  PCI Parity Generator.
   3 //
   4 // PCI Target generates PAR in the data phase of a read cycle.
   5 // The 1's sum on AD, CBE and PAR is even.
   6 //
   7 //   Date                 Version       Author  Description
   8 //   2005-05-13   R00A00        PAU             First alfa revision     (eng)
   9 //
  10 //  Copyright (C) 2005 Peio Azkarate, peio@opencores.org
  11 //
  12 //   This source file is free software; you can redistribute it     |
  13 //   and/or modify it under the terms of the GNU Lesser General     |
  14 //   Public License as published by the Free Software Foundation;   |
  15 //   either version 2.1 of the License, or (at your option) any     |
  16 //   later version.                                                 |
  17
  18
  19 module pcipargen_new (clk_i, pcidatout_i, cbe_i, parOE_i, par_o);
  20
  21         input clk_i;
  22         input [31:0] pcidatout_i;
  23         input [3:0] cbe_i;
  24         input parOE_i;
  25         output par_o;
  26
  27
  28         wire [31:0] d;
  29         wire pardat;
  30         wire parcbe;
  31         wire par;
  32         wire par_s;
  33
  34         assign d = pcidatout_i;
  35
  36         assign pardat = d[0]  ^ d[1]  ^ d[2]  ^ d[3]  ^ d[4]  ^ d[5]  ^ d[6]  ^ d[7]  ^
  37                            d[8]  ^ d[9]  ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^
  38                            d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^
  39                            d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
  40
  41         assign parcbe = cbe_i[0] ^ cbe_i[1] ^ cbe_i[2] ^ cbe_i[3];
  42
  43         assign par = pardat ^ parcbe;
  44
  45     // PAR
  46         assign par_o = ( parOE_i == 1 ) ? par_s : 1'bZ;
  47
  48 endmodule
  49 /*
  50 component sync
  51 port (
  52     clk             : in std_logic;
  53     d           : in std_logic;
  54     q               : out std_logic
  55 );
  56 end component;
  57
  58 component sync2
  59 port (
  60     clk             : in std_logic;
  61     d           : in std_logic;
  62     q               : out std_logic
  63 );
  64 end component;
  65
  66 begin
  67
  68
  69
  70     u1: sync2 port map (
  71                 clk => clk_i,
  72                 d => par,
  73                 q => par_s
  74         );
  75
  76
  77
  78
  79 end rtl;
  80 */